Preliminary
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Architecture
3.2.9 Media Independent Interface (MII)
The following sections discuss the operation of the Media Independent Interface (MII) in 10 Mbps and 100
Mbps mode. An IEEE 802.3 compliant Ethernet MAC controls the interface.
3.2.9.1
Data Reception
3.2.9.1.1 Receive Control
Data received from the PHY is interpreted and output to the EMAC receive FIFO. Interpretation involves
detection and removal of the preamble and start-of-frame delimiter, extraction of the address and frame
length, data handling, error checking and reporting, cyclic redundancy checking (CRC), and statistics
control signal generation. Address detection and frame filtering is performed outside the MII interface.
3.2.9.1.2 Receive Inter-Frame Interval
The 802.3 standard requires an interpacket gap (IPG), which is 24 MII clocks (96 bit times). However, the
EMAC can tolerate a reduced IPG (2 MII clocks or 8 bit times) with a correct preamble and start frame
delimiter. This interval between frames must comprise (in the following order):
1. An Interpacket Gap (IPG).
2. A 7-byte preamble (all bytes 55h).
3. A 1-byte start of frame delimiter (5DH).
3.2.9.1.3 Receive Flow Control
When enabled and triggered, receive flow control is initiated to limit the EMAC from further frame
reception. Two forms of receive flow control are implemented on the device:
•
Receive buffer flow control
•
Receive FIFO flow control
When enabled and triggered, receive buffer flow control prevents further frame reception based on the
number of free buffers available. Receive buffer flow control issues flow control collisions in half-duplex
mode and IEEE 802.3X pause frames for full-duplex mode. Receive buffer flow control is triggered when
the number of free buffers in any enabled receive channel free buffer count register (RXn FREEBUFFER)
is less than or equal to the receive channel flow control threshold register (RXn FLOWTHRESH) value.
Receive flow control is independent of receive QOS, except that both use the free buffer values.
When enabled and triggered, receive FIFO flow control prevents further frame reception based on the
number of cells currently in the receive FIFO. Receive FIFO flow control may be enabled only in
full-duplex mode (FULLDUPLEX bit is set in the in the MAC control register, MACCONTROL). Receive
flow control prevents reception of frames on the port until all of the triggering conditions clear, at which
time frames may again be received by the port.
Receive FIFO flow control is triggered when the occupancy of the FIFO is greater than or equal to the
RXFIFOFLOWTHRESH value in the FIFO control register (FIFOCONTROL). The RXFIFOFLOWTHRESH
value must be greater than or equal to 1h and less than or equal to 42h (decimal 66). The
RXFIFOFLOWTHRESH reset value is 2h.
Receive flow control is enabled by the RXBUFFERFLOWEN bit and the RXFIFOFLOWEN bit in
MACCONTROL. The FULLDUPLEX bit in MACCONTROL configures the EMAC for collision or IEEE
802.3X flow control.
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SPRUGX9 – 15 April 2011
EMAC/MDIO Module
© 2011, Texas Instruments Incorporated