0
...
...
b7
b6
b1
b0
...
LSB
MSB
Sequential data
b7
b6
b1
b0
1
SD_DAT0
0
1
SD_DAT0
...
...
...
LSB
MSB
Block data
CRC
Block length * 8
b7
b6
b1
b0
b7
b6
b1
b0
1
0
SD_DAT3
...
b7
b3
b7
b3
LSB
MSB
CRC
1
0
...
b6
b2
b6
b2
CRC
1
0
...
b5
b1
b5
b1
CRC
1
0
...
b4
b0
b4
b0
CRC
Block length * 2
SD_DAT2
SD_DAT1
SD_DAT0
Preliminary
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Architecture
Coding Scheme for Data Token
Data tokens always start with 0 and end with 1 (see
,
,
Figure 9-6. Data Packet for Sequential Transfer (1-Bit)
Figure 9-7. Data Packet for Block Transfer (1-Bit)
Figure 9-8. Data Packet for Block Transfer (4-Bit)
9.2.2 Resets
9.2.2.1
Hardware Reset
The module is reinitialized by the hardware.
The SD_SYSSTATUS[0] RESETDONE bit can be monitored by the software to check if the module is
ready-to-use after a hardware reset.
This hardware reset signal has a global reset action on the module. All configuration registers and all
state machines are reset in all clock domains.
This hardware reset signal has a global reset action on the module. All configuration registers and all
state-machines are reset in all clock domains.
933
SPRUGX9 – 15 April 2011
Secure Digital (SD)/—Secure Digital I/O (SDIO) Card Interface
© 2011, Texas Instruments Incorporated