Preliminary
Registers
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9.4
Registers
lists the SD/SDIO registers.
CAUTION
The SD/SDIO registers are limited to 32-bit data accesses. 16-bit and 8-bit
are not allowed and can corrupt register content.
Table 9-13. SD/SDIO Registers
Address Offset
Acronym
Register Name
Section
0
SD_HL_REV
IP Revision Identifier
4h
SD_HL_HWINFO
Hardware Configuration
10h
SD_HL_SYSCONFIG
Clock Management Configuration
110h
SD_SYSCONFIG
System Configuration
114h
SD_SYSSTATUS
System Status
124h
SD_CSRE
Card status response error
128h
SD_SYSTEST
System Test
12Ch
SD_CON
Configuration
130h
SD_PWCNT
Power counter
200h
SD_SDMASA
SDMA System address:
204h
SD_BLK
Transfer Length Configuration
208h
SD_ARG
Command argument
20Ch
SD_CMD
Command and transfer mode
210h
SD_RSP10
Command Response 0 and 1
214h
SD_RSP32
Command Response 2 and 3
218h
SD_RSP54
Command Response 4 and 5
21Ch
SD_RSP76
Command Response 6 and 7
220h
SD_DATA
Data
224h
SD_PSTATE
Present state
228h
SD_HCTL
Host Control
22Ch
SD_SYSCTL
SD system control
230h
SD_STAT
SD interrupt status
234h
SD_IE
SD interrupt enable
238h
SD_ISE
SD interrupt enable set
23Ch
SD_AC12
Auto CMD12 Error Status
240h
SD_CAPA
Capabilities
248h
SD_CUR_CAPA
Maximum current capabilities
250h
SD_FE
Force Event
254h
SD_ADMAES
ADMA Error Status
258h
SD_ADMASAL
ADMA System address Low bits
25Ch
SD_ADMASAH
ADMA System address High bits
2FCh
SD_REV
Versions
962
Secure Digital (SD)/—Secure Digital I/O (SDIO) Card Interface
SPRUGX9 – 15 April 2011
© 2011, Texas Instruments Incorporated