Preliminary
Architecture
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3.2.8.2
EMAC Module Operational Overview
After reset, initialization, and configuration, the application software running on the host may initiate
transmit operations. Transmit operations are initiated by host writes to the appropriate transmit channel
head descriptor pointer contained in the state RAM block. The transmit DMA controller then fetches the
first packet in the packet chain from memory. The DMA controller writes the packet into the transmit FIFO
in bursts of 64-byte cells. When the threshold number of cells, configurable using the TXCELLTHRESH bit
in the FIFO control register (FIFOCONTROL), have been written to the transmit FIFO, or a complete
packet, whichever is smaller, the MAC transmitter then initiates the packet transmission. The SYNC block
transmits the packet over the MII interfaces in accordance with the 802.3 protocol. Transmit statistics are
counted by the statistics block.
Receive operations are initiated by host writes to the appropriate receive channel head descriptor pointer
after host initialization and configuration. The SYNC submodule receives packets and strips off the
Ethernet related protocol. The packet data is input to the MAC receiver, which checks for address match
and processes errors. Accepted packets are then written to the receive FIFO in bursts of 64-byte cells.
The receive DMA controller then writes the packet data to memory. Receive statistics are counted by the
statistics block.
The EMAC module operates independently of the CPU. It is configured and controlled by its register set
mapped into device memory. Information about data packets is communicated by use of 16-byte
descriptors that are placed in an 8K-byte block of RAM in the EMAC control module.
For transmit operations, each 16-byte descriptor describes a packet or packet fragment in the system's
internal or external memory. For receive operations, each 16-byte descriptor represents a free packet
buffer or buffer fragment. On both transmit and receive, an Ethernet packet is allowed to span one or
more memory fragments, represented by one 16-byte descriptor per fragment. In typical operation, there is
only one descriptor per receive buffer, but transmit packets may be fragmented, depending on the
software architecture.
An interrupt is issued to the CPU whenever a transmit or receive operation has completed. However, it is
not necessary for the CPU to service the interrupt while there are additional resources available. In other
words, the EMAC continues to receive Ethernet packets until its receive descriptor list has been
exhausted. On transmit operations, the transmit descriptors need only be serviced to recover their
associated memory buffer. Thus, it is possible to delay servicing of the EMAC interrupt if there are
real-time tasks to perform.
Eight channels are supplied for both transmit and receive operations. On transmit, the eight channels
represent eight independent transmit queues. The EMAC can be configured to treat these channels as an
equal priority "round-robin" queue or as a set of eight fixed-priority queues. On receive, the eight channels
represent eight independent receive queues with packet classification. Packets are classified based on the
destination MAC address. Each of the eight channels is assigned its own MAC address, enabling the
EMAC module to act like eight virtual MAC adapters. Also, specific types of frames can be sent to specific
channels. For example, multicast, broadcast, or other (promiscuous, error, etc.), can each be received on
a specific receive channel queue.
The EMAC keeps track of 36 different statistics, plus keeps the status of each individual packet in its
corresponding packet descriptor.
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EMAC/MDIO Module
SPRUGX9 – 15 April 2011
© 2011, Texas Instruments Incorporated