Local host or
DMA access
cmd
SDMARREQN
dat0
Buffer Level
Command
Response
Data
Time
Buffer full
Buffer empty
BLEN
bytes
LH sends a
read command
DMA read access
(BLEN reads)
From host
to card
From card
to host
From card
to host
Read transfer active
SD_PSTATE[9]
RTA = 1
Card starts
sending data
into the buffer
Card completes sending
data into the buffer and
DMA request set after
BLEN reached
Request cleared after first
DMA read
Command
complete IRQ
Transfer
complete IRQ
Interrupt request
CRC
status
Data
dat[3:1]
Preliminary
Architecture
www.ti.com
9.2.5.1.1 DMA Receive Mode
In a DMA block read operation (single or multiple), the request signal SDMARREQN is asserted to its
active level when a complete block is written in the buffer. The block size transfer is specified in the
SD_BLK[10:0] BLEN field.
The SDMARREQN signal is deasserted to its inactive level when the sDMA has read one single word
from the buffer. Only one request is sent per block; the DMA controller can make a 1-shot read access
or several DMA bursts, in which case the DMA controller must manage the number of burst accesses,
according to block size BLEN field.
New DMA requests are internally masked if the sDMA has not read exactly BLEN bytes and a new
complete block is not ready. As DMA accesses are in 32-bit, then the number of sDMA read is
Integer(BLEN/4)+1.
The receive buffer never overflows. In multiple block transfers for block size above 512 bytes, when the
buffer gets full, the CLK clock signal (provided to the card) is momentarily stopped until the sDMA or
the MPU performs a read access, which reads a complete block in the buffer.
provides a summary:
•
DMA transfer size = BLEN buffer size in one shot or by burst
•
One DMA request per block
Figure 9-9. DMA Receive Mode
940
Secure Digital (SD)/—Secure Digital I/O (SDIO) Card Interface
SPRUGX9 – 15 April 2011
© 2011, Texas Instruments Incorporated