Preliminary
www.ti.com
Control Module
1.16.1.3.6 DDR Control Register (DDR_CTRL)
The DDR_CTRL register reflects the DDR I/O timing as programmed in the device eFuse and controls
DDR self-refresh operation.
The DDR Control Register (DDR_CTRL) is shown in
and described in
Figure 1-162. DDR Control Register (DDR_CTRL)
31
30
29
28
27
26
25
24
Reserved
FORCE_PHY_RST
DIS_DEV_RST
Reserved
KEEPSREF1
SREF1
R-0
R/W-0
R/W-0
R-0
R/W-0
R/W-0
23
20
19
18
17
16
Reserved
DDRDATA_SLEW1
DDRCMD_SLEW1
R-0
R-eFuse
R-eFuse
15
10
9
8
Reserved
KEEPSREF0
SREF0
R-0
R/W-0
R/W-0
7
4
3
2
1
0
Reserved
DDRDATA_SLEW0
DDRCMD_SLEW0
R-0
R-eFuse
R-eFuse
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 1-203. DDR Control Register (DDR_CTRL) Field Descriptions
Bit
Field
Value
Description
31-30
Reserved
0
Reserved. Read returns 0.
29
FORCE_PHY_RST
1-0
Force DDR Phy Reset. When set, this bit forces a reset of the DDR Phys to allow DDR clock
frequency to be changed.
28
DIS_DEV_RST
1-0
Disable DDR Device Reset. Setting this bit cause the RESETn outputs for the DDR0 and
DDR1 interfaces to be held high. This allows power-down and subsequent power-up of
EMIFs without resetting DDR devices.
27-26
Reserved
0
Reserved. Read returns 0.
25
KEEPSREF1
1-0
Keep DDR1 Self Refreshed. Setting this bit keeps the DDR1 CLKEN driven to maintain self
refresh when the Active power domain is disabled.
24
SREF1
1-0
Enable DDR1 Self Refresh.
23-20
Reserved
0
Reserved. Read returns 0.
19-18
DDRDATA_SLEW1
0-3h
DDR1 Data Slew. Reflects the DDR1 Data Macro slew adjustment programmed in eFuse.
17-16
DDRCMD_SLEW1
0-3h
DDR1 CMD Slew. Reflects the DDR1 CMD Macro slew adjustment programmed in eFuse.
15-10
Reserved
0
Reserved. Read returns 0.
9
KEEPSREF0
1-0
Keep DDR0 Self Refreshed. Setting this bit keeps the DDR0 CLKEN driven to maintain self
refresh when the Active power domain is disabled.
8
SREF0
1-0
Enable DDR0 Self Refresh.
7-4
Reserved
0
Reserved. Read returns 0.
3-2
DDRDATA_SLEW0
0-3h
DDR0 Data Slew. Reflects the DDR0 Data Macro slew adjustment programmed in eFuse.
1-0
DDRCMD_SLEW0
0-3h
DDR0 CMD Slew. Reflects the DDR0 CMD Macro slew adjustment programmed in eFuse.
305
SPRUGX9 – 15 April 2011
Chip Level Resources
© 2011, Texas Instruments Incorporated