Preliminary
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2-50.
PAT Area Description
...................................................................................................
2-51.
DMM Simple Manual Area Refill
.......................................................................................
2-52.
DMM Single Auto-configured Area Refill
..............................................................................
2-53.
DMM Chained Auto-configured Area Refill
...........................................................................
2-54.
DMM Synchronised Auto-configured Area Refill
.....................................................................
2-55.
DMM Cyclic Synchronised Auto-configured Area Refill
.............................................................
2-56.
DMM Section Use-Case 2
..............................................................................................
2-57.
DMM_REVISION Register
..............................................................................................
2-58.
DMM_SYSCONFIG Register
...........................................................................................
2-59.
DMM_LISA_LOCK Register
............................................................................................
2-60.
DMM_LISA_MAP Registers
............................................................................................
2-61.
DMM_TILER_OR Registers
............................................................................................
2-62.
DMM_PAT_CONFIG Register
.........................................................................................
2-63.
DMM_PAT_VIEW Registers
............................................................................................
2-64.
DMM_PAT_VIEW_MAP Registers
....................................................................................
2-65.
DMM_PAT_VIEW_MAP_BASE Register
.............................................................................
2-66.
DMM_PAT_IRQ_EOI Register
.........................................................................................
2-67.
DMM_PAT_IRQSTATUS_RAW Register
.............................................................................
2-68.
DMM_PAT_IRQSTATUS Register
....................................................................................
2-69.
DMM_PAT_IRQENABLE_SET Register
..............................................................................
2-70.
DMM_PAT_IRQENABLE_CLR Register
..............................................................................
2-71.
DMM_PAT_STATUS Registers
........................................................................................
2-72.
DMM_PAT_DESCR Registers
.........................................................................................
2-73.
DMM_PAT_AREA Registers
...........................................................................................
2-74.
DMM_PAT_CTRL Registers
............................................................................................
2-75.
DMM_PAT_DATA Registers
...........................................................................................
2-76.
DMM_PEG_PRIO Registers
............................................................................................
2-77.
DMM_PEG_PRIO_PAT Register
......................................................................................
3-1.
EMAC and MDIO Block Diagram
......................................................................................
3-2.
Ethernet Configuration—GMII Connections
..........................................................................
3-3.
Ethernet Frame Format
.................................................................................................
3-4.
Basic Descriptor Format
................................................................................................
3-5.
Typical Descriptor Linked List
..........................................................................................
3-6.
Transmit Buffer Descriptor Format
.....................................................................................
3-7.
Receive Buffer Descriptor Format
.....................................................................................
3-8.
EMAC Control Module Block Diagram
................................................................................
3-9.
MDIO Module Block Diagram
..........................................................................................
3-10.
EMAC Module Block Diagram
..........................................................................................
3-11.
EMAC Control Module Interrupt Logic Diagram
.....................................................................
3-12.
EMAC Control Module Identification and Version Register (CMIDVER)
.........................................
3-13.
EMAC Control Module Software Reset Register (CMSOFTRESET)
.............................................
3-14.
EMAC Control Module Emulation Control Register (CMEMCONTROL)
.........................................
3-15.
EMAC Control Module Interrupt Control Register (CMINTCTRL)
.................................................
3-16.
EMAC Control Module Receive Threshold Interrupt Enable Register (CMRXTHRESHINTEN)
..............
3-17.
EMAC Control Module Receive Interrupt Enable Register (CMRXINTEN)
......................................
3-18.
EMAC Control Module Transmit Interrupt Enable Register (CMTXINTEN)
......................................
3-19.
EMAC Control Module Miscellaneous Interrupt Enable Register (CMMISCINTEN)
............................
3-20.
EMAC Control Module Receive Threshold Interrupt Status Register (CMRXTHRESHINTSTAT)
............
3-21.
EMAC Control Module Receive Interrupt Status Register (CMRXINTSTAT)
....................................
27
SPRUGX9 – 15 April 2011
List of Figures
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