Tektronix 2440, User Manual

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Theory of Operation— 2440 Service
Sample-and-Hold outputs of both CH 1 an CH2 are gated
in turn to the A/D Converter. The cycle then repeats until
1024 samples from all four sides of both CCDs have
been converted.
NOTE
The samples are docked through each side of the
CCD at a 500 kHz rate, resulting in an output
sampling rate of 2 MHz per channel. Also note that
the 8-to-1 gating of the two channels and their
respective outputs results in a 4 MHz time-
multiplexed (8-to-1) signal to the A/D Converter.
For Short-Pipeline sampling mode, the gating for the
inputs to the Sample-and-Hold circuits is the same as in
FISO mode. However, since only one side of each CCD is
used per channel, only one pair of differential outputs (per
CCD) and the corresponding Gain-Cell amplifier and
Sample-and-Hold circuits transfers valid waveform
samples to the A/D Converter. The Short-Pipeline mode
save-acquisition clocking ensures that only the valid
converted data is saved (see “Short-Pipeline Mode" in
“Acquisition Process and Control”). Observe, however,
that the signal to the A/D Converter is still a 4 M Hz time-
multiplexed signal, but with invalid data half of the time.
Since the invalid data is, in effect, discarded by the Short-
Pipeline Mode save-acquisition clocking, the A/D Converter
continues to operate at a constant 4 M Hz conversion rate
as in FISO mode.
The time-multiplexed signal is applied to the input of the
A/D Converter circuit for digitization. The System Clocks
circuit (diagram 7) provides a 4 M H z clock to the
converter, for a 4 M H z data-conversion rate of the input
signal. The resulting digital output byte is applied in four
8
-bit bytes to the Acquisition Latches (diagram 15).
For Normal and Average Acquisition Modes, data is
clocked into the Acquisition Latches by another 4 M Hz
clock time-shifted from the 4 M Hz clock used by the A/D
Converter. Enabling of the outputs of the Acquisition
Latches is controlled by the CCD D ata clocks in a
sequence that ensures that the data clocked out from the
enabled latch corresponds to the CCD side and Sample-
and-Hold circuit that provided it. The
8
-bit sample bytes
are then saved in Acquisition memory in the same order
they were obtained. This “structured” method for saving
acquisitions keeps the data in the correct tim e sequence
for display.
For Envelope Mode, the Time Base Controller disables
continuous gating of the 4 M Hz clock to the Acquisition
Latches. This action turns over the gating of that clock to
the Envelope M in-M ax Com parators (diagram 15). With
the 4 M Hz clock ungated, the CCD D ata Clocks will
continue to control the enabling of the outputs of the
acquisition latches as described, but the new data bytes
are not continually clocked into the latches. The result is
that only the data bytes clocked in by the Envelope Min-
Max Com parators are sequentially clocked to the
Envelope Data bus in the following manner: CH 1 max,
CH 2 max, CH 1 min, CH 2 min. This is the same order in
which the analog samples are clocked into the A/D
Converter.
The output of the A/D Converter is fed to the Envelope
M in-M ax Com parators (diagram 15). The outputs of the
Acquisition Latches are also fed back to those compara­
tors. Due to the previously described timing action of the
CCD Data Clocks, the newly digitized minimum or max­
imum value from the Peak Detectors (see “Input Signal
Conditioning and Analog Sampling”) is compared to the
last value latched into the Acquisition Latch that
corresponds to the new point. If the newly acquired point
is outside the previous min or max value, the appropriate
Envelope M in-M ax Com parator gates the 4 M Hz clock,
and the new data byte is latched into the corresponding
acquisition latch.
ACQUISITION PROCESSING
AND DISPLAY
Data Transfer to SAVE Memory
Once the 1024 digitized signal bytes per channel are in
Acquisition Mem ory, the Tim e Base Controller ungates the
SAVEACQ clock and switches the the Mem ory Mode Con­
trol circuit to the W aveform
nP.
It also signals the
W aveform via the Display Status Buffer (diagram 2),
that the acquisition is complete. The W aveform
tiP
can
then access the Acquisition Memory.
When the W aveform
nP
reads the acquisition done
(ACQDN) signal from the Time Base Controller, it writes
an address (via the Address Latch) which is decoded by
the Register Address Decoding circuit (diagram 2). The
decoded address signals the Record-End Latch
(diagram
8
) to enable its contents (the last addressed
memory location for the stored acquisition) to the
W aveform
nP
data bus to be read to determ ine the loca­
tion of the last record byte stored. The W aveform
nP
then
uses that location to determine the location of any byte in
Acquisition Memory.
The W aveform
nP
outputs (via its Address Latch)
addresses to the Address Counter for Acquisition Memory.
The Address Counter is held in its load mode by the
W aveform *tP (via the Memory Mode Control circuit), pass­
ing the address through to Acquisition Memory. The
W aveform
nP
enables the Acquisition Memory and
provides the clocks (via the Mem ory Mode Control circuit)
3-12