Tektronix 2440, User Manual

Page: 94 / 531

Theory of Operation— 2440 Service
Depending on the address written to, one of the follow­
ing actions may occur:
Mode control data may be loaded into the internal
mode register.
The internal events and delay counter low-byte or
high-byte of the number of events to be counted or
delay may be loaded.
Various strobes used for internal control of the Trigger
Logic Array may be generated.
Table 3-5 shows the action taken for each address
selected.
Table 3-5
Trigger Logic Array Addresses
(6080h-6087h)
Address Bits
Circuit Operation
A2 A1 AO
Initiated
0 0 0 Restart Acquisition
0 0
1 Force Manual Trigger
0
1 0 Load Mode Control Data
from M 0-M 7
0
1 1 Latch Delay Counter Low-
Byte from M 0-M 7
1
0 0
Latch Delay Counter High-
Byte from M 0-M 7
1 0 1 Load Delay Counter from
Delay Latches
1 1 0 Select Events in FISO,
Delay by Events, or Short
Pipe
1
1 1
Reset All Latches
As previously mentioned, U370 provides final trigger­
mode and source selection, dependent on data written
from the System mP to a control register within U370 at
address 6082h. The mode control data byte loaded from
the M 0-M 7 input bus is built by the System
tiP
and applied
to the M 0-M 7 (mode) inputs from serial-input register U270
(diagram 5) via the GAD0-GAD7 bus lines. The data byte
defines the A Trigger source, B Trigger source, Record
Trigger source, Jitter Trigger source, and whether a single
event or multiple events are needed to produce a trigger.
Bit definition is shown in Figure 3-6.
After the control data byte is loaded and the acquisition
is restarted, Trigger Logic Array U370 waits for EPTHO
(end of pretrigger holdoff) to go HI at pin 28, indicating that
the acquisition system has sampled the “pretrigger” points
and is ready to complete the acquisition. With EPTHO set
HI, the trigger logic begins watching the trigger source (as
defined by the control data byte), waiting for a trigger
event to occur.
Operation of the Trigger Logic Array is very sequential
in the way it functions in the various trigger modes. An
example is illustrated in the sequence of events for
B RUNS AFTER trigger mode.
1. The System
yP
loads the “delay count" and “control
mode” registers, then starts the acquisition (indicated by
setting RSTACQ HI at TP370).
2. The Trigger Logic Array watches for EPTHO at pin
28 to go HI; signaling that the defined number of pre­
trigger points have been sampled.
3. With EPTHO HI, the Trigger Logic Array watches
MTG and MTG (main trigger gate) for an A trigger event to
start the delay counter. When a trigger occurs, JTRIG
(jitter trigger) is generated, starting the jitter-correction cir­
cuits (via the RAM P and RAMP signals).
4. The defined delay count is decremented to zero by
the DELCLK (delay clock) signal on pin 67 from Phase
Clock Array U470. If the mode were A Delayed by
B Events, the B Trigger events would be used to decre­
ment the delay counter.
5. In this example, when the internal Delay count
reaches 0, a RTRIG (record trigger) is generated for
B RUNS AFTER. RTRIG is the “record trigger” point on
the displayed waveform. If the mode were B TRIG AFTER,
the Trigger Logic Array would begin w atching for a B
Trigger to occur on the DTG and DTG input pins (Delay
Trigger Gate).
6. Time Base Controller U670 (diagram 8) counts the
post-trigger samples as they are acquired. When the
required count is reached to complete the acquisition, it
resets EPTHO to LO and further triggers from the Trigger
Logic Array are prevented from being generated.
The Time Base Controller then starts moving digitized
samples to the Acquisition Memory and, when finished,
tells the System
nP
that the acquisition is done. The Sys­
tem
nP
may then restart the whole process again for the
next acquisition by writing appropriate data to the various
trigger registers.
In external clock mode, the differential EXTCK and
l=kTCK (external dock) signals to the Phase Clock circuit
replace the normal master-dock (MCLK) signal and allows
the B trigger events to be used as the events
delay source.
3 -5 2
REV SEP 1988