Tektronix 2440, User Manual

Page: 70 / 531

T h eo ry o f O p e ra tio n - 2 4 4 0 Service
ACQDN (acquisition done) signals on the W D bus where
they may be read. These status bits are used by the reading
pP to determine when to execute the next phase of a display
or acquisition sequence.
Interrupt Latch
The Interrupt Latch (U550) allows the Waveform pP opera­
tions to interrupt the System pP for servicing and, when
servicing is com pleted, allows the System pP to reset the
interrupt.
To write data into the latch, the controlling pP addresses
location 6019h, causing the COMREG line from U540 to
enable U550. Data from the WD bus is written into the latch
on the rising edge of the WWR pulse. The Q output from pin
10 (MDISDN) of the latch is applied to AND-gate U580B
(diagram 1) where it either masks the DISDN (display done)
interrupt from the System pP when it occurs or lets the
interrupt pass. Masking the DISDN interrupt from the System
jji
P permits the Waveform pP to have first access to the
Display System for display updates before the System pP
sees that the Display System is finished with its last task.
The Q output bit on pin 15 is the W PDN (waveform proces­
sor done) interrupt and provides the Waveform pP with a
way of telling the System pP that it is done with its assigned
task and is ready to accept another. The output bit on pin 15
is applied to Display Status Register U542A and is used for
write-readback verification of U550 and U542A during the
self-check and other diagnostic routines.
The other two Q outputs, SVPGO and SVPG1 at pins 2 and 7
respectively, control which of four
8
K pages is selected
when Save RAM U350 is accessed. See “Address Decode”
earlier in this section for more information.
FRONT PANEL PROCESSOR
The Front Panel Processor (diagram 3) monitors the settings
of the pots and switches of the Front Panel (diagram 4) and
the Auxiliary Front Panel (diagram
6
). The Front Panel pP
allows quick system response to changes in front-panel
settings without excessive use of tim e by the System pR The
Front Panel Processor system consists of the microproces­
sor integrated circuit with a built-in RAM, ROM, and A/D
converter (for digitizing the potentiometer wiper voltages);
the handshake logic between the System jjlP and the Front
Panel pP (to synchronize data transfer between processors);
and the data bus interface to provide the actual data trans­
fers between busses.
Front Panel pP
Front Panel pP U700 does the reading of the front-panel
pots and switches. It continuously scans the front-panel
control settings and compares them against the values
stored in its internal RAM. When a change is detected, the
Front Panel pP issues an interrupt to the System pP. The
System pP then handles the interrupt and reads the
changed data from the Front Panel pP to update its con­
trol-setting values. The Front Panel pP also updates the
current value list stored in its RAM for further use.
Front Panel
jul
P
U700 is externally clocked by the 4 MHz
system clock applied to the external clock input (EXTAL).
Initially, the LO state of FPRESET on the INT
2
input (pin 18)
will clear all the internal registers of the Front Panel pR
When FPRESET goes H I, the pP executes the power-up
self-test instructions stored in ROM space within the pP
integrated circuit. When the self test has com pleted, the
Front Panel pP sends the diagnostic result byte to the
System pP and branches to its main program. The main
program routine sets up the data direction for the various
port lines, sets the A N 0-A N 3 (analog inputs 0 -3 ) to their
analog input mode, and receives the eight front-panel
configuration bytes from the System pP that define the
manner in which the various front-panel switches and pots
operate. It then begins scanning the front-panel pots and
switches for their initial settings. After the initial values are
determined and stored, the Front Panel pP sends those
coded values back to the System pP in an 11-byte message
(10
data bytes plus an end-of-message byte) to update the
front-panel information held by the System pP. It then begins
scanning the front-panel controls for changes from the
currently stored front-panel values.
To read front-panel pot settings, the internal A/D converter of
the Front Panel pP performs an
8
-bit, successive-approxima­
tion conversion of the analog levels applied to the ANO and
AN2 inputs by a selected potentiometer. These analog input
signals come from
8
-input analog multiplexers U902 on the
Front Panel (diagram 4) and U600 on the Auxiliary Front
Panel (diagram
6
). A specific pot to be read is selected by
the multiplexer under control of the MUXSELO, MUXSEL1,
MUXSEL2, and MUXINH (multiplexer inhibit) output lines
from the Front Panel pR These select signals, in combina­
tion with the selected A/D (ANO or AN2) input, define the pot
being read.
To read the front-panel switches, the Front Panel pP first sets
one of the front-panel switch-matrix rows LO, using the
MUXSEL0-MUXSEL2 outputs. It then sets its S /L (shift/load)
output on pin 29 LO. The LO does a parallel load of the
switch-closure data into shift registers U904 (diagram 4) and
U700 (diagram
6
). The shift/load line is then set HI (shift
mode), and eight shift clocks (SHCLK) are generated to
move the switch-closure data serially onto the SW OUT
(front-panel switch data out) or the SW OUT A (auxiliary
3-28 REV JUN 1991