Theory of Operation—2440 Service
input (pin 2) causes the output (pin 6) of U281 to move in
the opposite direction. This voltage change is applied to
the base of Q181 (via R145) and to the base of Q 182 (via
series diodes CR193 and CR194 from R145). These
transistors are biased in their linear region and act as
emitter followers for the signals at their bases. Two series
diodes between the bases of the transistors separate the
base voltages by 1.2 volts, so the emitters of both transis
tors are at about the same potential. Negative feedback
from the amplifier output (junction of R194-R196) is via
R280. The resistance ratio of R280 to R172 sets the volt
age gain of the amplifier at - 1 . Capacitor C 281, from the
output of U281 back to the input at R172, provides a fast
feedback path to smooth transition spikes.
Sample Switch U270B, Hold Capacitor C260, and Volt
age Follower U280 form a sample-and-hold circuit. The
output of the High-Current Difference Amplifier at the junc
tion of R194 and R196 is allowed enough time to settle to
its new level before the 250 kHz SAMPLE pulse goes LO.
At that time, the output of the Difference Amplifier is
applied to the input of Voltage Follower U280A, and C260
is charged rapidly to that output voltage level. The
SAMPLE pulse returns HI, and the BX output of the data
selector goes to its high-impedance state to start the hold
time. Voltage Follower U280 has high-impedance FET
inputs; therefore, Hold Capacitor C260 discharges very lit
tle during the hold time.
The output of Voltage Follower U280 is held at the volt
age level across C260; that level causes some value of
current to flow through the series combination of R620
and R162 to the input of Integrator U282 (pin 2, the invert
ing input). The output of Integrator U282 at pin 6 ramps
linearly for the duration of the hold cycle. (Actually, it
ramps for almost the whole cycle, since the charge on
Hold Capacitor C260 reaches the final level slightly before
the sample switch is opened to start the hold time.) The
time constants of the integrating network composed of
R162 and of the series combination of R601 and C l 80 in
parallel with R603 and C470 are such that the output of
Integrator U282 reaches the new point position just as the
next SAMPLE gate to U270B occurs. (A step change of
1 volt at the input causes a ramp of —1/4 V per
ns
(or —1
volt over the 4 ms cycle hold time.)
The feedback of this “ new” point position to U281
through R160 modifies the reference at pin 3 of Difference
Amplifier U281 (new reference is one-half the output volt
age at U282 pin 6). The next voltage from Input Buffer
U170 is applied to the input (pin 2 of U281) of the
Difference Amplifier which now amplifies the difference
between the present point position on screen (represented
by the voltage at pin 3 of U281A) and the new position
(applied to pin 2 of U281A). This difference voltage is sam
pled and stored on Hold Capacitor C260 where it sets a
new current level through R162 and R620 from the output
of Voltage
Follower U280 to the input (pin 2) of
Integrator U282A.
This cycle just described of comparing the old position
to the new one, sampling the difference, and ramping to
the new position continues for each point of a vector
waveform display.
The adjustment associated with Voltage Follower U280
is INT ADJ potentiometer R620. This pot (the integrator
adjustment) is used to compensate for charge current
introduced from analog switch U270B. A corresponding
adjustment is not present in the Horizontal Vector Genera
tor circuit. A VECTOR COM P adjustment is present in
both the Vertical and Horizontal Integrator circuits. The
pots (R276 vertical and R376 horizontal) are used to
adjust for minimum vertical and horizontal offset between
the vector and dot displays.
Mode Select
The Mode Select Switch consists of data selector
U290A (horizontal) and U290B (vertical). The switches
route the various X-Axis and Y-Axis signal sources to the
Horizontal and Vertical Output Amplifiers. The select sig
nals to U290 coming from Miscellaneous Display Register
U540 (diagram 17) allow the System
fiP
to switch to the
various display modes (Envelope, vectors, dots, and
readout). The System
nP
does this by writing control bits
to the I Q and 2Q output of Display Register U540 (AMP1
and AMPO respectively) which are applied to select input
SELb (pin 9) of U290B and to SELA (pin 10) of U290A.
An envelope waveform display is produced by selecting
the XO and Y0 inputs of U290 to be switched to the Out
put Amplifiers. The signal applied to the Horizontal Output
Amplifier for YT displays is the incrementing count from
the Display Counter, and it moves the electron beam hor
izontally across the face of the crt. In the Vertical circuitry,
a sample-and-hold circuit formed by Data Selector U270A
and Hold Capacitor C912 bypasses the Vertical Vector
Generator circuitry. The 250 kHz signal driving the data
selector, derived from the same Clock Divider circuit that
supplies the SAMPLE signal (U410A and B, diagram 17),
is delayed slightly by the rc combination of R607 and
C900. The delay allows the analog signal at the output of
the Vertical DAC to settle before the sample from Input
Buffer Amplifier U170 is taken. The voltage on C912 is
applied to the rc integrator made up of R165 and C l 66 to
produce a min-max envelope with shaded vectors between
the successive dots.
3 -7 4
Summary of Contents for 2440
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