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Theory of Operation— 2440 Service
the opposite edge of the sample clock. The RAMP2 Jitter
Correction Counter produces a count defining the trigger
point relative to the opposite edge of the sample clock.
Since both ramps have a possibility of an error in their
slow-ramp starting times (due to metastable switching of
the SLRAMP1 and SLRAMP2 signals) there will always be
a chance of error present in the trigger-position count. The
count from both ramps is checked, and the value closest
to the nominal midrange count will be used by the System
iiP
when placing the repetitively sampled data points. If
both counts are in error, that acquisition is discarded.
TRIGGER HOLDOFF, JITTER COUNTERS,
AND CALIBRATOR
Circuitry shown in diagram 13 performs a variety of
functions.
The Trigger Holdoff circuits allow a delay to occur
between the occurrence of a triggering event and when
the A/B Trigger Generator is allowed to recognize another
trigger event. Variable Holdoff can help the user prevent
double triggering on aperiodic signals (such as complex
digital words).
The RAMP1 and RAMP2 Jitter Correction Counters
measure the time difference between the asynchronous
trigger event and the actual sampling point of the
waveform data. That information is needed by the System
nP
to place the random samples taken in REPET acquisi
tion mode correctly with respect to data points taken in
the previous acquisitions to fill the waveform record.
The Calibrator circuit generates a square-wave output
having precise amplitude and frequency characteristics.
The CALIBRATOR signal provided at the front-panel con
nector is useful for adjusting probe compensation and veri
fying VOLTS/DIV and SEC/DIV calibration.
The Side Board Address Decoder included in the cir
cuitry is used by the System
nP
to enable the appropriate
register or buffer on the Side board to read the Jitter
Correction
Counters,
select the Holdoff Time,
and
communicate with the Front Panel
fiP.
T rig g er Holdoff
The Trigger Holdoff circuit consists of a trigger-enabled,
constant current source (actually one of three selectable
sources added to a small permanent source) used to
linearly charge a capacitor (one-of-two selectable cap
values). The resulting integrator output is a linear ramp
whose
slope
depends
on
the
current-source
and
integration-capacitor selection. The ramp is applied to the
Holdoff Comparator where it is compared to the user-
definable (front-panel pot) holdoff-reference level. When the
charging ramp crosses that level, the ramp rapidly
discharges (resets) and ends the holdoff condition.
Holdoff S e le ct
The Holdoff Select circuit, under System
nP
control,
determines which of the Holdoff Current Sources and
which of the integration capacitors will be used to produce
the holdoff ramp. Its outputs are set by the microproces
sor by writing data into Holdoff Register U762, residing at
address 620Ch. Output bits HOO through H 0 2 (holdoff
control bits 0-2) enable their corresponding current-source
transistor when HI. Bit HQ3 is used for selection of the
integration capacitor. The FPRESET bit allows the system
processor to reset the Front Panel
nP
(diagram 3).
Buffer U 761, residing at read location 602Ch, allows the
System jaP to check the holdoff circuit setup and to moni
tor the status of the A Trigger (ATG) and trigger holdoff
(ATHO) bits.
Holdoff C urrent Sources
The Holdoff Current Sources provide the constant
currents used to charge the integration capacitors (produc
ing a linear ramp). The circuit consists of four transistor
current sources, three of which may be turned on or off
under control of the Holdoff Select circuit.
The bases of the four current-source transistors, Q 761,
Q771, Q772, and Q773, are held one diode-drop below
+ 5 V by C R772 and R773. This results in precisely + 5 V
being present on the emitter of any conducting current-
source transistor. The amount of current is set by the
value of emitter resistors). Transistor Q 773 will always be
on while the other three current-source transistors can be
turned on or off by the HO control bit via the associated
emitter diodes. A LO at the cathode of one of these diodes
will disable the associated current source by reverse bias
ing the transistor junction; a HI at the cathode of a diode
enables the charging-current source via the associated
emitter resistor.
C harging C ap a cito r S electio n
The Charging Capacitor Selection circuit composed of
Q783, Q782, and associated components, selects the
integrating capacitance. The magnitude of the charging
current from the selected current source, in combination
3 -5 8
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