Table 6-6 (cont)
Maintenance— 2440 Service
2.
Check that STOP1 and STOP2 are present at U841 pin 12 and U842 pin 12 (on the Side board).
These signals are not coincident and should be jittering with respect to one another.
If missing, backtrack to U490 and/or U390 (located on the Main board and shown on diagram
12) to locate the defective component.
3.
While triggering on the START1 pulse, check for gated signal (by STOP1) at U852 pin 1 on the
Side board. Check at U853 pin 1 for gated signal while triggering on the START2 pulse. If either
gated signal is missing, check the gating components to locate the problem.
4.
While triggering on the START1 pulse, check for activity (fast to slow) at the Jitter Counter
(U844 and U852) outputs (pins 14, 13, 11 and 12 on U844; pins 3, 4, 5, 6, 11, 10, 9, and 8 on
U852). Observe that each output pin on the ICs should be switching slower than the preceding
one as the counters count down. Replace the counter if found defective.
5.
Check that the inputs to U750 and U752 are gated to the outputs of U752. The only time they
are the same is if both pin 1 and 19 are low. If a W ORD trigger probe is not available, the follow
ing setup may be used making use of the A and B Trigger Mode to obtain coincident triggering.
HORIZONTAL
A and B SEC/DIV
MODE
VERTICAL
MODE
COUPLING
VOLTS/DIV
POSITION
TRIGGER
A TRIGGER SOURCE
A LEVEL
SLOPE
MODE
B TRIGGER SOURCE
MODE
200 ns
B
CH 1 and CH 2
DC
2 V
Traces to graticule center
EXT1 A*B
500 mV
- (minus)
NORMAL
EXT2
TRIG AFTER; EXT CLK OFF
Now connect the EXT1 to U750 and U752 pin 1 and EXT2 to U750 and U752 pin 19. The input-
output pairs may now be checked, and they should compare at the “T ” of the trigger point.
ANALOG SECTION TROUBLESHOOTING
1.
Connect a probe from CH 1 of the scope under test to the TTLB1 test point on its main board.
Select REPET, set the scope under test to 2 ns/div and obtain a stable trigger.
2.
Set the test scope to 500 jts/div.
With the test scope:
3.
Make sure that the signal at the collector of Q491 and Q390 stabilizes at about 800 mV. This is
the baseline stabilization circuit. The waveforms shown next to the schematic diagrams are useful
to make waveform comparisons.
4.
Check for a fast ramp that corresponds to RAMP and RAMP from U370. This ramp should rise
from the stabilization level to a maximum and start down at the same time that the START1 (or
START2) pulse steps high, and that the STOP1 (or STOP2) pulse steps high when the descending
ramp crosses 0 V. If not, troubleshoot the circuitry to determine the problem. These ramps should
be linear both in rise and fall times.
6-39
Summary of Contents for 2440
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Page 91: ...Theory of Operation 2440 Service 3 49 Figure 3 5 Simplified CCD architecture ...
Page 120: ...Theory of Operation 2440 Service Figure 3 10 DC Restorer 3 78 ...
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Page 136: ...Theory of Operation 2440 Service Figure 3 15 PWM Regulator and Inverter 3 94 ...
Page 138: ...Theory of Operation 2440 Service Figure 3 16 PWM switching waveforms 3 96 ...
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Page 423: ...2440 Service Figure 9 4b 2440 Block diagram part 2 6330 27 BLOCK DIAGRAM PART 2 ...
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