Tektronix 2440, User Manual

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Theory of Operation— 2440 Service
Table 3-6
Phase Clock Array Control Lines (CC3 through CCO)
SEC /D IV Setting
Control Bits
Mode
CC3 CC2 CC1
CCO
EXT CLK 1 1 0
0
100 ns and faster 0 1 0
1 FISO
200 ns
0 1 1 0
FISO
500 ns
1
0 0
1 FISO
1
ms
1
0
1 0 FISO
2 /us
1 0 1
1 FISO
5
ns
1 1 0
1 FISO
10 MS
1 1 1 0
FISO
20
ms
1
1
1
1 FISO
50
ms
0
0
0 1
FISO (Short-Pipe
Clock Source)
100
ms
and slower 0 1 1
1 Short-Pipe
with the present sample count to locate the trigger event
(explained later). When the Time Base Controller has com­
pleted the post-trigger count, it will set SO (slow out) HI,
switching the Phase Clock Array mode from “Fast In" to
“Slow Out” mode. The various phase clocks are now
derived from the 1 MHz 2XPC clock (from the Time Base
Controller) instead of the 500 MHz master clock, and
samples are shifted out of the CCD arrays at the A/D
conversion rate.
Outputs TL0-TL4 (trigger location bits 0 through 4)
define the trigger location within ± 1 /2 of a sample interval
and allow the extra samples taken at the beginning and
end of the CCD sample array contents to be discarded.
Defining and discarding these samples is done because
the trigger event may occur at any of 32 locations within
the four A registers. Outputs TL2-TL4 locate the trigger at
one of the eight sample positions within the A register,
allowing samples before the start of the waveform to be
discarded. Outputs TLO and TL1 define trigger position
within the sample interval to one of the four sides ( L I , L2,
L3 or L4) by sampling the phase of the L clocks when the
trigger occurred.
SHORT-PIPE MODE. A second acquisition mode,
Short-Pipe mode, is used at SEC/DIV settings 100
MS/div
and slower. In Short-Pipe mode, the
<j>A
2 clock that
transfers samples down the input (A) register is disabled;
and instead, the Tl (transfer into B array) clock shifts sam­
ples straight down the first register of the B array to the
output well. Sampling occurs at 2 MHz in Short-Pipe mode
(500 kHz each side of the CCD array) as the various
phase clocks are derived from the 2XPC clock. Trigger
delays are generated at the SDC (slow-delay clock) rate
since Short-Pipe mode connects the DELCLK output to
the SDC input. Since sampling is occurring at a 2 MHz
rate and the SEC/DIV is set so that a sample rate slower
than this is required, some of the samples must be dis­
carded. The discrepancy is resolved by Time Base
Controller by counting and discarding the proper number
of samples between those it allows to be saved. This
allows effective sample rates much lower than the actual
2 MHz rate and, by routing the SDC signal to DELCLK,
allows the trigger delays to be counted in terms of
effective sample events.
In FISO mode, the TTLB1 (TTL-level phase B1) signal
runs at 1/8 of the A-register clock rate and is used by the
Time Base Controller to keep track of how many FISO
samples have been taken. Each TTLB1 clock indicates
that 8 sample intervals have occurred. In Short-Pipe mode,
the TTLB 1 clock runs at the A-register clock rate. By
using the TTLB1 count and the TL0-TL4 data, the Time
Base Controller (U670, diagram 8) can precisely determine
when the acquisition is finished.
TTLC2 is a TTL version of the phase 2 clock for the C
(output) register and runs at all times except during
RESET. This is one of the signals required by the System
Clock Generators for producing correctly timed Output
Sample Clocks to the CCD Output circuitry (diagram 14)
and the RESET clock to the CCD arrays.
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