Tektronix 2440, User Manual

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T h e o ry o f O p e ra tio n - 2 4 4 0 S e rv ic e
W aveform pP O p eratio n —When the Waveform jjP gains
control of the waveform bus, it sequentially moves the 1024
data points for each channel (512 min/max pairs
in
enve­
lope) from the Acquisition Memory (diagram 8) to the Save
Memory (U350). When the Waveform
pP
does a display
update, it selects the required data points needed for each
waveform display requested (according to the mode se­
lected) from Save Memory and moves them to the Display
Memory (diagram 16). At the end of the display update,
DISDN (display done) from the Display Control (diagram 17)
goes
HI
to interrupt the Waveform
jjl
P
(and the System
pP if
the Waveform
pP
is also done and permits the signal to be
gated to the System pP via AND-gate U580B, diagram 1).
This tells the Waveform pP that the current display cycle has
completed and the next update to Display Memory may be
started.
When in ENVELOPE acquisition mode with more than a one
acquisition accumulation to be displayed, the data bytes
stored in Save Memory are not automatically overwritten
with each acquisition. As the data bytes are being trans­
ferred from Acquisition Memory to Save Memory, they are
compared by the Waveform p.R If the new data byte does
not exceed the current maximum or minimum value in Save
Memory location that it is being compared with, that Save
Memory location is not overwritten (until the envelope
acquisition is reset to start a new accumulation).
In AVG acquisition mode, data from the Acquisition Memory
is averaged with the waveform data in the Save Memory, and
the Save Memory is then rewritten with the averaged
waveform data. Waveform adds, multiplies, expansions, and
interpolations are performed by the Waveform pP on the
Save Memory data prior to transfer to the Display Memory
for display.
W aveform pP A ddress Enabling- T h e 2.5 MHz System
Clock signal CLK1 from the Clock Divider U710 (diagram 7)
is inverted by U866E and ORed with the skewed 2.5 MHz
CLK3 signal by OR-gate U264B. The timing of this ORed
signal is such that the output of U264B goes HI when the
address on the input pins of Waveform Address Registers
U562 and U364 is guaranteed to be valid. Inverter U270B
inverts the output from the OR-gate (WVMA—waveform
valid-memory address), and when that output again goes
LO, the rising edge of the inverted WVMA signal on the clock
input of the Waveform Address Registers latches the 16-bit
address from the Waveform pP into the registers.
A ddress Latch- D D U 366, a dual 4-to-1 multiplexer, and
Address Latches U364 and U562 couple a modified version
of the 16-bit address output by the Waveform pP
(DADO-DADF) to the Waveform Processor Address Bus
(WAO-WAF). Addresses latched to the Waveform Processor
Address Bus remain on that bus for the entire Waveform pP
cycle.
Due to its architecture, the Waveform pP outputs different
address blocks than those required to access the various
memories on the Waveform Processor Data Bus (see
Fig. 3-2). U366 selects either address bit DADC or DADB for
output to address WAB of the Waveform Processor Data
Bus, depending on the condition of its three most-significant
address bits, DADC, DADE, and DADF. AND-gate U276B
detects when these bits are all HI and outputs a HI to the “A”
select input of the multiplexer. With the “B” select input held
HI for all Waveform pP accesses by BUSCONNECT, U366
routes DADB to address bit WB via address latch U562.
If any of the three most-significant Waveform pP address
bits are low, DADC is coupled to address bit WB. This action
translates the addresses output by the Waveform pP to those
required on the Waveform Processor Bus.
If BUSCONNECT is LO, the access is a System Processor
access and BUSGRANT is HI. BUSGRANT disables the
Address Latches and the decoding action of U366 does not
affect the address on the Waveform Processor Bus. BUS-
GRANT is inverted via U254B enables the Bus Connect
Address Buffers to connect the System Address Bus to the
Waveform Processor Bus.
Test point TP562 on address line WAA provides a trigger
source for an external test oscilloscope when examining
address waveforms in the Waveform pP “KERNEL” mode. As
the KERNEL mode exercises address lines WAO-WAA, WAA
is used as the trigger point.
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