Table 6-6 (cont)
Maintenance— 2440 Service
In version 1.7 software, an abort will cause the Trigger LEDs to flash, but no coded flashing is done.
The abort codes for version 2 software and possible causes of an abort are shown in the following
table:
CODE
Meaning
Possible Cause
1
Abort code initialized to this value at
power-on.
Bad R O M /RAM . Firmware bug.
2
Unknown code received from Front Panel
>P.
Front Panel
y P
data path to System
y P
bad.
3
Too many bytes received from Front Panel
m
P.
Front Panel
y P
data path to System
y P
bad
or handshake logic bad.
4
Software Interrupt 2 or Software Interrupt 3
instruction executed.3
Bad R O M /RAM . Firmware bug.
5
GPIB terminator value for query response
scrambled.
Bad
R O M /RAM .
Firmware
bug.
(May
require a COLD START.)
6
GPIB event code to be reported is un
known.
Bad
R O M /RAM .
Firmware
bug.
(May
require a COLD START.)
7
GPIB delimiter found
by scanner
has
changed and is invalid.
Bad
R O M /RAM .
Firmware
bug.
(May
require a COLD START.)
aSWI2 and SWI3 are not used in the software instructions. If executed, they were not as valid instructions.
Use the System
y P
Kernel Test to verify the ability of the System
y P
to function.
System
y P
A12U640 (schematic diagram 1) Kernel Test:
1.
With the power off, move jumper J126 from pins 1 and 2 to pins 2 and 3 of P I 26. This disables
the System
y P
Data Bus Driver, and allows the data bus lines to be pulled up and down to a
single-byte instruction. The instruction (CLRB) continually fetches and executes the CLRB instruc
tion to step through the entire 64 K of addresses.
2.
Move jumper J127 (Waveform Processor Bus control) from the NORMAL position (pins 1 and 2
connected) to the BUSTAKE position (pins 2 and 4 connected). This places the Waveform Proces
sor Bus under control of the System
y P .
In the mode, the basic operation of the System
y P
can
be checked, and all the address decoding circuitry can be verified.
3.
Connect CH 1 of a test scope to TP840. Display that signal and use it as a trigger source for the
test scope. This point is the AF address bit (the MSB) of the address bus.
4.
Turn the power on and check that the RESET signal on U844 pin 8 is HI; if not, troubleshoot the
Power Up Reset circuitry (schematic diagram 1) and the Power Up circuitry (schematic
diagram 23).
5.
Adjust the test scope to view the AF signal. It should be a TTL-level square wave with a 50% duty
cycle.
6-9 9
Summary of Contents for 2440
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Page 91: ...Theory of Operation 2440 Service 3 49 Figure 3 5 Simplified CCD architecture ...
Page 120: ...Theory of Operation 2440 Service Figure 3 10 DC Restorer 3 78 ...
Page 130: ...Theory of Operation 2440 Service 3 88 ...
Page 136: ...Theory of Operation 2440 Service Figure 3 15 PWM Regulator and Inverter 3 94 ...
Page 138: ...Theory of Operation 2440 Service Figure 3 16 PWM switching waveforms 3 96 ...
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Page 423: ...2440 Service Figure 9 4b 2440 Block diagram part 2 6330 27 BLOCK DIAGRAM PART 2 ...
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Page 428: ...2440 Service WAVEFORMS FOR DIAGRAM 1 6 2 8 5 3 2 ...
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Page 432: ...2440 Service WAVEFORMS FOR DIAGRAM 2 BUS ISOLATED 6 6 0 3 4 9 ...
Page 433: ...WAVEFORMS FOR DIAGRAM 2 ...
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Page 450: ...2440 Service WAVEFORMS FOR DIAGRAM 8 6603 27 ...
Page 455: ...W A V EFO R M S FOR D IAG RAM 11 WAVEFORMS FOR DIAGRAM 11 6603 29 ...
Page 458: ...WAVEFORMS FOR DIAGRAM 12 ...
Page 463: ...WAVEFORMS FOR DIAGRAM 14 ...
Page 471: ... C N i u i t e x r 4 j u J l i 1 i 6 28 5 44 WAVEFORMS FOR DIAGRAM 18 ...
Page 476: ...WAVEFORMS FOR DIAGRAM 20 ...
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Page 517: ...10 16 R E V J U L 1993 Replaceable Mechanical Parts ...
Page 518: ...2440 Service ...
Page 519: ...FIG 4 L V H V PWR SUPPLY ...
Page 520: ...FIG 5 ACCESSORIES 2440 Service ...
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