Tektronix 2440, User Manual

Page: 66 / 531

Theory of O p e ratio n - 2 4 4 0 Service
W aveform pP R ead/W rite Enabling—Once latched, the
address is removed from the bus and, depending on wheth­
er jaP U470 is supposed to be reading or writing, data will be
read into the processor from data bus buffers U360 and
U560 or written to the WD (waveform data) bus via U360, a
bidirectional data bus buffer. To read data into the processor,
the HI R/W (read-write) signal is applied to NAND-gate
U870C where it is NANDed with CLK1. During the half
period that C LK1 is HI (CLK1 is LO), the gated output from
U870C is the WRD (waveform processor read) in its LO
(asserted) state. The LO is applied to the direction-enabling
input of bidirectional buffer U360 via U542B. This LO en­
ables U360 for a read from the WD (waveform data) bus, and
the addressed
8
-bit word on the W D bus is applied to the
center eight lines of the processor 16-bit address/data bus.
The four least significant bits (LSB) and the four most
significant bits (MSB) of the data applied to the WD bus
come from buffer U560, which is enabled via U250B and
U250A for processor reads. The four LSBs are always LO
(guard bits), while the four MSBs will be set to the same
level as the WD7 bit (sign-extended) of the center eight bits.
This placement of the
8
-bit data in the center of the 16-bit
bus provides a reasonable tradeoff between dynam ic range
(12 bits) and guard bits (4 bits).
To write data out of the Waveform pP to the WD bus, the
WRD level applied to the direction-enabling pin of U360 will
be HI. The center eight bits of the Waveform pP data bus will
then be buffered onto the W D (waveform data) bus by U360
and written to the currently addressed location. During
writes to the WD bus, the HI level of WRD disables buffer
U560, via U250B and U250A, to isolate it from the Waveform
pP address/data bus.
System pP A ccess—When the System p P needs to do an
access in the Waveform pP address space, it checks its
software copy of PCREG to see if the Waveform pP is reset.
If it is not reset, the System pP asserts BUSREQ (bus
request) to the Waveform pP and waits until the Waveform
pP outputs a BUSACK (bus acknowledge) to OR-gate
U332D. The output of U332D is the BUSGRANT signal that,
when HI, disables the Waveform pP data buffers, address
registers, and memory control lines.
When Waveform pP U470 is being held reset (inactive) and
cannot possibly respond to a BUSREQ, the System pP
instead asserts BUSTAKE to OR-gate U332D when it needs
to take control of the Waveform pP address space. The
System pP can also assert BUSTAKE during diagnostics in
the event of a Waveform pP failure to release the bus after a
BUSREQ is given.
With BUSGRA NT asserted HI, the inverted BUSGRANT,
BUSGRANT is output by inverter U254B and enables Bus
Connect Address Buffers U262, U260, and U564. The
enabled buffers connect the System pP address bus and
control signal lines to their counterparts from the Waveform
pR The Bus Connect Data Buffer U552, a bidirectional
device, is then enabled and directed by control signals from
the System pP for data transfers to and from the Waveform
pP data bus.
Decoding circuitry uses the signals WFRAM, MAIN, MAIN2,
and HMMIO; System-Address bits A3, A4, and AF; and
BUSTAKE/BUSGRANT to determine when to enable U552
and connect the System Data Bus to the Waveform Data
Bus. The addresses that produce accesses to the Waveform
RAM (and require U552 to be enabled) are shown as are
noted on the memory map, Figure 3-2. (Also, see “System
Address Decode,” appearing earlier in this section.)
The Bus Connect Data Buffer is enabled when the output of
the dual-input AND-gate U432D steps HI and the output of
U254D steps LO. With BUSGRANT asserted H I, the output
state of U850A depends on the state of its other input which
is controlled by the output of OR-gate U850A. Any HI on
U850A’s inputs drives its output LO. This LO output holds
the output of U432D LO and U552 disabled HI via U254D.
3-24