Tektronix 2440, User Manual

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Theory of Operation— 2440 Service
JITTER CORRECTION RAMPS
The Jitter Correction Ramps located on diagram 12 are
a portion of two dual-ramp timing circuits used to detect
and measure the time difference between a trigger event
and the sample clock. This information is needed when
doing acquisitions at SEC/DIV settings greater that 100 ns
to correctly place the data points obtained on different
trigger events. The Jitter Correction Counters are located
on diagram 13.
Jitter Correction Ram ps
Operation of the RAMP1 and RAMP2 circuits is identi­
cal; therefore, only the RAMP1 Jitter Correction circuit will
be described. Both Jitter Correction Ramps are initiated by
the same trigger event, but they are switched to their
slow-discharge mode on opposite edges of the sample
clock. By switching on opposite edges, the trigger point
has two distinct references which define the trigger point,
allowing the System
fiP
to detect and correct for meta­
stable states of the trigger recognition logic.
The ramp generator consists of a constant current
source used to rapidly charge an integration capacitor
when the trigger event occurs and a second current
source used to discharge the capacitor (more slowly) after
the proper edge of the sample clock occurs. The fast-
charge time is the actual time from the trigger event to the
appropriate sample-clock edge. The time it takes the
slow-discharge mode to discharge C491 gives a numerical
representation (counted) of how high the ramp level
reached when C491 was fast charging; and therefore, the
time of the fast ramp.
Fast charging rate is determined by the constant
current source formed by U590A, Q493, and associated
components. The charging current is nominally 50 mA
through R590, R591, R593 and Q493. The voltage drop
across the resistors balances the + 7 .5 volt reference at
pin 2 of U590A and keeps Q 493 turned on just enough to
maintain the balance at the operational amplifier inputs.
This charge current is switched through either Q491 or
Q492, depending on whether the ramp should be ramping
down slowly or ramping up quickly. When waiting for a
trigger to occur, the SLRMP1 (slow-ramp 1) will be LO,
turning Q491 on. Charging current from Q491, which
would normally charge integration capacitor C491 (and the
50 pF circuit-board capacitor), is shunted to - 5 volts by
Q490, which is turned on by a HI RAMP fast ramp) signal
applied to its base.
RAMP CLAMPING.
The clamping circuit made up of
U590B, CR490, and associated components, holds the
ramp summing-node voltage (collector of Q490) at zero
volts while the circuit is waiting for a trigger to occur (sig­
naled when RAMP and RAMP go to their true states). The
summing-node voltage is applied to U590B on pin 6 where
it is compared to the zero-volt clamp level (ground) on pin
5. When the summing node attempts to go below ground
while Q490 is on, U590B will conduct more to maintain the
balance at the input pins, thereby clamping the summing
node at zero volts via R592 and CR490.
Transistor Q380 and its associated components clamp
the positive peaks of both ramps at + 3 .2 volts via CR491.
This clamping takes place at SEC/DIV settings slower
than 100 ns/div because the SLRM P signal doesn’t occur
soon enough after the RAMP signal starts the ramp to
reverse the ramp slope before the + 3 .2 V level is reached.
RAMP SW ITCHING. When Trigger Logic Array U370
(diagram 11) detects that a trigger event has occurred, it
sets the RAMP and RAMP signals to their active (true)
states. The LO RAMP signal turns Q490 off to allow the
integration capacitor to begin a fast charge, and the
HI RAMP signal turns Q392 on to reverse bias CR490 and
remove the clamp circuit from the summing node.
The charging current now linearily charges C491 and
the circuit board capacitance positive (holding STOP1 LO
through U490) until the proper edge of next sample clock
occurs (see Figure 3-7). This switches the SLRAMP1 and
SLRAMP1 signals to their true states, turning off Q491
and turning Q492 on.
With Q 492 on, the charging current is routed through
R497, producing a HI START1 signal and enabling the
RAMP1 Jitter Correction Counter circuit (diagram 13).
Since Q491 is now off, C491 begins the slow-ramp
discharge through Q495 and R493. When the voltage held
on C491 crosses the switching threshold of U490, STOP1
is switched HI to turn off RAM P I Jitter Correction Counter
at the proper count.
At the time of calibration, the JIT1 GAIN (jitter gain—
ramp 1) value is set to the base of the discharge current
source transistor, Q495, so that the ratio between charg­
ing rate and discharging rate is 1250:1 (approximately
20 mA from the charging current source to approximately
16
m
A discharge current from Q495). The slow discharge
time of C491 allows the RAMP1 Jitter Correction Counter
to convert the peak amplitude of RAMP1 (dependent on
the time that C491 was allowed to fast charge) into a
count relating trigger-event position to the sample-
clock edge.
After the Jitter Counter has been read, the RAMP,
RAMP, SLR AM P I, and SLRAMP1 signals will be reset to
their inactive states. This again clamps the summing-node
voltage at zero volts and reapplies the charging current to
the node in preparation for the next trigger event.
RAMP2.
As mentioned earlier, the RAMP2 Jitter
Correction circuit is running simultaneously, referenced to
3 -5 6