Tektronix 2440, User Manual

Page: 82 / 531

Theory of Operation— 2440 Service
The FISO (fast-in, slow-out, pin 36), ROLL (pin 2), and
ENVL (envelope, pin 39) outputs are set indirectly by Sys­
tem nP writes to the internal control registers at the start
of each acquisition cycle. Control signals are then output
by an internal state machine of the Time Base Controller
to dynamically control the acquisition circuitry in the
required mode and signal acquisition rate (set by FISO).
Writing to these “register” locations also allows the Sys­
tem
nP
to generate several strobes for internal latching
and control functions.
A state machine internal to Time Base Controller U670
runs the acquisition process from start to finish. When all
internal registers are properly loaded, the System nP
writes to location 6022(h), generating a strobe that
switches acquisition control to the Time Base Controller.
This starts the acquisition system, and samples are taken
in the defined mode. For FISO operations, the following
occurs.
A counter internal to U670 begins counting T T
l b
T (TTL
version of B clock— Phase 1) clocks to determine when at
least enough samples have been transferred into the “B”
register of the CCD arrays to fill “pretrigger” requirements.
Samples will then continue to be placed in the B register,
but no output samples will be saved until the record trigger
occurs. (All 1088 locations in the four sides of 8 x 34
B register will fill if a record trigger does not occur before
that many samples have been taken.) Each T T
l b
T clock
represents 32 analog samples (four, 8-sample sides)
transferred into the CCD array B register. When the
proper number of pretrigger samples have been loaded,
U670 will set its EPTHO (end of pretrigger holdoff) line HI.
This signal enables Trigger Logic Array U370 (diagram 11),
and the state machine in Time Base Controller U670
starts watching the SYNTRIG (synchronized trigger) input
(pin 30) from the Phase Clock Array (U470, diagram 11)
for the “record” trigger. In the meantime, the Trigger Logic
Array will be counting delay clocks (DELCLK) to fulfill any
specified delay requirements before a record trigger is per­
mitted to be generated.
When the delay requirements are met, the SYNTRIG is
allowed to occur when a trigger event occurs. The counter
then watches 11 L b i to determine when the proper
number of post-trigger samples have been moved to the
B register to meet the post-trigger requirements. Once
post-trigger requirements are met, it sets SO (slow-out,
pin 38) HI, which stops the sampling process and starts
A/D conversion of the analog samples stored in the CCD
array B register.
Since the trigger event can occur at any one of the 32
analog samples that are taken between each TTLB1B
clock, and since the Time Base Controller only keeps track
of the number of pretrigger and post-trigger samples in
terms of these 34-sample records, there are usually some
samples at the beginning of those in the CCD array
B register that are extra. When the analog samples are
serially moved out of the CCD array for digitization, these
extra samples must be ignored in order to maintain proper
trigger location within the complete record. The CCD
Phase Clock Array (U470) knows where the record trigger
occurred relative to the TTLB1 pulse (1-of-32 position) and
sends this information to U670 on the TL0-TL4 (trigger
location bits 0 through 4) lines. This trigger-location
number is loaded into the counter and, as the samples are
moved out of the CCD array, that number of extra sam­
ples is essentially discarded. Those samples are A/D
converted but will not be stored because U650B is not yet
enabled to gate the SAVEACQ signal used to write the
data into the Acquisition Memory.
Once the extra samples have been counted, the
ACQUIRE output is set HI. In FISO mode, six more sam­
ples are counted out via shift register U750, enabling
U650B. Since the instrument is in FISO mode, the output
of U512C will be HI and the SAVEACQ signal that is used
to save waveform data into the Acquisition Memory (via
U501) is controlled by the output of U835F (SHIFTD200N).
This input to NAND-gate U650B is a delayed version of
the SHIFT (4 MHz) clock. The 200 ns delay provided
ensures that the A/D Converter output byte has settled
before being written to the Acquisition Memory.
When the Time Base Controller is in control of writing
data to the Acquisition Memory, the SAVEACQ clock is
routed through U501 of the Mode Control Logic and
becomes the WE (write enable) clock used to write
waveform data into Acquisition Memory U600. That data
is obtained from the Acquisition Latches (diagram 15) via
buffer U613. The W E signal is also used to increment the
Memory Address Counter (U300, U400, and U401), the
result being that digitized samples from the Acquisition
Latches are saved interleaved in consecutive memory loca­
tions. Each address is latched into the Record-Start
Address Latches (U502 and U601) as the data-write ends,
so that the address of the last-stored sample is always
available. This information is used as a pointer when gen­
erating waveform displays.
As the digitized samples are moved to Acquisition
Memory, an internal counter in Time Base Controller U670
watches the M S 2 3 + M S 2 1 and M S 2 2 + M S 2 4 clocks (pins
6 and 28) to determine when 1024 points (or 512 max/min
pairs in Envelope mode) from each CCD array (CH 1 and
CH 2) have been stored. When 2048 samples have been
saved, the Time Base Controller will set ACQUIRE (pin 24)
LO, disabling memory saves, and it will set its ACQDN
(acquisition done) status line (pin 25) HI. The Waveform juP
(U470, diagram 2) then takes over for transfer of the
acquired waveforms to the Waveform
tiP
Save Memory.
When the Waveform
nP
(U470, diagram 2) reads the HI
ACQDN status via U542 (diagram 2), it reads the address
3 -4 0