Tektronix 2440, User Manual

Page: 83 / 531

Theory of Operation— 2440 Service
of the last-saved point from the Record-End Latch (U502
and U601). Since the Acquisition Memory addresses are
circular (incrementing the Address Counter from its last
address goes back to the first address), it knows the
record begins at the next address. With TB2M EM LO, the
ACQ signal is routed through Mode Logic Switch U501 to
become the W P2M EM signal. The ACQ signal going LO
from the Waveform
n P
via address decoder U570 enables
data buffer U610 to permit the Waveform
/iP
to access the
waveform data stored in the Acquisition Memory (see
“Waveform Processor System” description).
SHORT-PIPE OPERATION. Short-Pipe operation is
similar to FISO in the way mode and setup data is loaded
and the way the internal counter is used to keep track of
various events. The major differences are: Short-Pipe
mode moves input samples directly from the CCD array
“A ” register input, down the first “B ” register channel and
out of the CCD array through the “C ” register. Short-Pipe
mode must also synthesize the sample clock rate.
To synthesize the sample rate for the Short-Pipe mode,
FISO (from U670 pin 36) is set LO by the System ^P,
thereby enabling the CE2B/N (clock enable 2B divided by
N) input to U512C. The CE2B/N clock (along with the
SHIFTD200N clock) then controls saving the waveform
data into the Acquisition Memory. In Short-Pipe mode,
CCD sampling occurs at a continuous 2 M Hz rate, but due
to SEC/DIV setting data written to an internal counter in
U670, the synthesized CE2B/N clock will only allow every
“Nth” point to be saved in Acquisition memory to produce
only 50 data points per division in the display. Samples
between the saved Nth points are ignored. The syn­
thesized CE2B/N clock will only enable U650B long
enough to save either two or four points and is dependent
on the sweep-rate division factor written to the internal
counter. This allows effective sample rates down to 1 sam­
ple every 2
ms
(100 ^s/div) to be achieved. The 2XSDC
(two-times-slow-delay clock, U670— pin 29) runs at half of
this effective sample rate. This 2XSDC clock divided by
two at the Q output of U720B and buffered by U680C to
produce SDC. SDC allows the Trigger Array to count one
delay period per every four sample intervals.
Since CCD array samples are moved directly from the
input to the output via the first B register and since stored
samples may occur at a rate different than the sample
rate, pretrigger and post-trigger counting is done relative
to samples actually stored into the Acquisition Memory.
When enough valid pretrigger points have been saved,
EPTHO enables the Triggers. Data is saved in bursts of
two points (four points in ENVELOPE acquisition mode),
one for CH 1 and one for CH 2, at the synthesized rate.
When the trigger event occurs, U670 counts the proper
number of post-trigger samples. When the post-trigger
count is complete, since A/D converted data already is
stored in Acquisition Memory, ACQDN is set. Waveform
data bytes are moved to the Save Memory by the
Waveform ^P and control is given back to the System UP­
LOAD LATCHES FLIP-FLOP. In Envelope Mode, Load
Latches flip-flop U651A puts out a signal at the beginning
of each envelope sampling interval that is HI for four
acquisition cycles. That HI LOAD LATCHES signal loads
the first eight acquired data points (four min-max pairs)
into the Acquisition Latches to be used for min-max com­
parison to the following waveform samples in that
Envelope sampling interval.
The Set input of U651A is HI during Envelope, the out­
put of the flip-flop is controlled by the M S23 clock and the
CE2B/N clock (on the D input). The CE2B/N clock is a
divided down M S22 clock, with the division factor depend­
ing on the SEC/DIV setting. The division factor determines
how many waveform samples will be compared for new
max and new min data during each envelope sampling
interval. Only the maximum and minimum waveform data
point values that occur during the envelope sampling
interval are transferred to the Acquisition Memory.
For non-envelope acquisitions, ENVL is LO. The Set
input of flip-flop U651A is therefore asserted, and U651A
will be held in the Set state with the Q output (LOAD
LATCHES) held HI. That constant HI signal applied to the
Acquisition Latch Switching circuitry causes each data
point acquired to be loaded into the Acquisition Latches
and transferred into Acquisition Memory.
ROLL LOGIC. In ROLL mode the display is constantly
being updated as new data points are available. A means
is provided to tell the Waveform
n P
when new data points
are available. An interrupt to the Waveform
n P
is gen­
erated by the Roll Logic flip-flop, U651B. When the
ACQUIRE signal from Time Base Controller U670 goes HI,
new waveform data points are acquired. The HI state of
that signal is clocked to the Q output of flip-flop U651B on
the rising edge of the CE2B/N signal; the same signal that
causes the sample data to be saved into the Acquisition
Memory in Short-Pipe mode. The PTAVAIL signal at the
Q output is an interrupt to the Waveform
fiP .
When the
Waveform
n P
services the interrupt request, it sets
PTACK (point acknowledge) LO via U500B and U500C to
reset the flip-flop in preparation for the next new data
points. The saved points are also moved to the Save
Memory and then to the Display Memory for a display
update.
In NORMAL mode, the ROLL signal is LO, and NAND-
gate U500B outputs a continuous logic HI that holds the
Roll Logic flip-flop in the Reset state (with the Q
output LO).
3-41