Tektronix 2440, User Manual

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Theory of Operation— 2440 Service
output source follower amplifiers. The RESET clock
discharges the output wells between output sample inter­
vals so that charge does not accumulate at the input to
the source-followers.
In FISO mode, 8 samples are shifted down the serial
input of A register at a clock period equal to 0.08 times
the SEC/DIV setting. On every eighth clock cycle, the posi­
tive A2 clock pulse is replaced by a single positive Tl pulse
that moves ail the charge packets into a transfer-in regis­
ter at the head of the B register array. The A register is
then empty and ready to accept new serial-in samples.
The B register clocks run at 1/8 the speed of the A
register clock rate so that the A register will be filled prior
to each B register clock. In this way, the B register is filled
with samples that are moved in parallel through the array.
During this Fast-In portion of the input cycle, unneeded
charges that arrive at the output C register due to the way
the input signal is continually sampled (until a trigger
occurs) are emptied from the CCD through the output
diffusions (OD13 and OD24). When the Time Base
Controller determines that the proper number of samples
have been stored in the CCD after the trigger occurs, the
mode changes to Slow-Out. The C register and RESET
clocks then toggle at a constant 500 kHz rate to shift take
samples out of the CCD to be digitized. The B register
clocks pulse once during every eighth C register clock
cycle to shift charge packets into the C register.
The Short Pipe mode of the CCD is in effect at
SEC/DIV settings of 100
ns
and slower. The CCD is
operated at a continuous 500 kHz rate. Samples are
shifted serially through the CCD via one B register channel
only. The Tl clock toggles continuously to move the sam­
ple charge packets from the first A register position into
the active B register channel, shown in Figure 3-5 as the
Short-Pipe Path.
All charge packets exit the CCD through the output
diffusions (OD13 and OD24) which are biased at approxi­
mately 11 volts by operational amplifier U460A.
C lock Drivers
The Clock Driver integrated circuits internal to the
CCD/Clock Driver hybrids develop the two “A ” register
clocks, the two “B” register clocks, the four “L” register
clocks, and the transfer input (Tl) and transfer output (TO)
clocks for the CCD. The high-speed A, L, and Tl drivers
are differential class A drivers through thick-film load resis­
tors on the hybrid. The B Register drivers are slower with
active pull-up and pull-down totem-pole outputs similar to
conventional TTL driver outputs. The TO gate is con­
nected on the hybrid to the B2 gates and driven by the B2
driver output.
The LI and L3 high-speed clocks are accessible at
probe pins 18 and 19 of the hybrid devices. These pins
(PL1 and PL3) are isolated from the actual CCD gates by
internal 875-Q series resistors. Terminate the signals into
50 Q to view them. Using the standard 10 MO probe will
cause the signals to have a displayed rise time of about
30 ns; the actual rise time internally is less than 2 ns.
Bias current for the Channel 1 high-speed drivers is set
by the feedback circuit of U360B and Q375. The drivers
are biased by injecting current into the IS input (pin 37).
Increasing the current makes the LO level of the high­
speed clocks more negative; decreasing the current raises
the LO level. The HI level of the clocks is always within a
few hundred mV of the + 5 V supply to the hybrid. For
controlling the negative clock level, the common-mode
level of the L I and L3 clocks at the PL1 and PL3 outputs
is applied to the input of U360A. This level is compared to
the midpoint between the + 5 V and —5 V supplies.
Operational amplifier U360A drives the base of Q 375 to a
level such that the current injected into IS sets the
common-mode level of PL1 and PL3 equal to the voltage
at pin 3 of U360A (the voltage supply midpoint value).
Since the HI clock levels at PL1 and PL3 are approxi­
mately at the + 5 V supply level, the LO levels of the
clocks then are set to approximately the —5 V supply
level. Bias stability is thereby maintained over
temperature and component variations.
The logic inputs for the A, L, Tl, and B drivers are all
ECL levels from U470, the Phase Clock Gate Array. Resis­
tor array R470 provides proper termination for the ECL
logic inputs to the CH 1 Clock Drivers. Fine adjustment of
clock timing for the L, A, and Tl clocks is necessary to
insure that the CCD transfers charge optimally, and that
samples are taken at the right times in each of the four
sides. The symmetry-delay integrated circuits provide this
adjustability. These circuits sit between the ECL logic
inputs to the hybrid and the clock driver integrated circuit.
They accept the ECL level inputs and produce ECL level
outputs which have several nanoseconds of adjustability of
both the rising and falling edges. R442 through R449 are
the calibration adjustments for the symmetry and delay of
the L, A, and Tl clocks. The dc level, “V IP ,” applied to
U460B’s input by U470, is the internal ECL threshold volt­
age of U470. This threshold is buffered by U460B and
provided as the reference for the ECL inputs to the
symmetry-delay integrated circuits. This provides stable
logic switching times without the need for true differential
ECL logic between U470 and U450.
“C” CLOCK DRIVERS.
These are external clock drivers
consisting of Q450, Q460, and associated components.
They provide the necessary —5 V to + 5 V clock swings
for the CCD C register gates. Each driver is simply an
inverting buffer which accepts TTL inputs from the Phase
Clock Array. During the Fast-In portion of the FISO
acquisition cycle, the outputs of both drivers are held HI by
the Phase Clock Array. During the Slow-Out portion of the
cycle, and at SEC/DIV settings of 1 0 0 /ts and slower, the
C Clock Drivers toggle at a 500 kHz rate with a 50% duty
cycle. When toggling, the C2 output is 180° out-of-phase
with the C l output for normal two-phase clocking.
3 -5 0