Tektronix 2440, User Manual

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Theory of Operation— 2440 Service
RESET DRIVER. This driver consisting of Q 551 is ident-
ical to the C Clock Driver states. It takes the RESET sig­
nal input from U731C in the System Clocks circuitry
(diagram 7). Like the C Clock Drivers, the Reset driver is
driven HI during Fast-in and toggles at other times. The
Reset driver output is held HI for only 200 ns of the 2
clock period.
— 2 V R e g u la to r
A - 2 V supply needed to terminate all of the high­
speed ECL signals on the Main circuit board is formed by
U580B and Q580. The circuit is a simple series-pass regu­
lator with R585 and R586 developing the —2 V reference
for operational amplifier U580B from the - 5 V supply.
Feedback is through R587. Collector load resistors R486,
R487, and R488 limit the power dissipation of Q580 and
protect it from possible short circuits of the - 2 V supply.
TRIGGERS AND PHASE CLOCKS
In this scope, the acquisition system continuously
acquires input samples. When the user-specified number
of “pretrigger” samples have been moved into the CCD
arrays, the trigger system is allowed to recognize trigger
events. Sampling of the signal input to the CCD arrays
continues (with new samples pushing out old samples)
until a trigger occurs. After the trigger, the number of
“post-trigger” samples needed to fill the waveform record
are moved into the CCD arrays and sampling is stopped.
The acquired samples are then moved out of the CCD
arrays, digitized, stored to memory, and displayed. The
acquisition system then begins again to fill the “pretrigger
window" for the next acquisition; and, when that has been
done, the trigger system is enabled to look for the next
trigger event.
The Trigger circuits (diagram 11) detect when the user-
defined triggering conditions are met and then allow the
acquisition to be completed. When the triggering signal lim­
its defined by the user for slope, level, and variable holdoff
are detected by A/B Trigger Generator U150, the resulting
trigger output is applied to Trigger Logic Array U370,
where triggering conditions of delay mode, delay time or
delay events count, and optional trigger sources are taken
into consideration. The Trigger Logic Array outputs several
trigger-recognition and acquisition-control signals that
cause the acquisition system to finish the “post-trigger"
portion of the acquisition.
The Phase Locked Loop and CCD Phase Clock circuits
(diagram 11) control sampling and shifting operations of
the CCD/Clock Driver hybrid. The Phase Locked Loop
synthesizes the 500 MHz sample clock driving the CCD
Phase Clock Array. The CCD Phase Clock Array uses this
“master” clock to generate other CCD clocks in accor­
dance with mode data written to it from the System
n P.
A /B T rig g e r G e n e ra to r
The A/B Trigger Generator circuit, composed of U150
and associated components, provides for selection and
analog-type trigger detection from five input signals for
each of the A and B triggers. These are the CH 1 and
CH 2 vertical inputs, the EXT 1 and EXT 2 trigger inputs,
and the line-trigger input (A trigger only). Two multiplexers
internal to U150 select one of these signals as the trigger
source for A Trigger and one (excluding the LINE signal)
for B Trigger. Source selection depends on the states of
the SR0A, S R I A, and SR2A (source select— A trigger)
lines for the A Trigger and on SR0B, SR1B, and SR2B for
B Trigger. The appropriate select bits are written into
register U140 by the System ^P whenever the operator
makes a triggering condition change using the trigger
source menus.
Control data from the System
tiP
defining trigger mode,
trigger coupling, and trigger slope are clocked serially (one
bit at a time) from the CD (control data) line into two
storage registers internal to U150. Clocking the CCA (con­
trol clock A) line moves the setup data to the A control
register, while clocking CCB moves data to the B control
register. When the control data has been loaded, each
trigger circuit begins comparing its selected input signal to
the user-defined trigger level for that trigger channel.
When the defined triggering criteria are met for either A
or B, the associated trigger outputs (ATG, ATG for
A Trigger; BTG, BTG for B Trigger) will go to their
asserted (true) states. The exception is when the A Trigger
holdoff has not finished (ATHO is still HI). When the holdoff
ends, however, the next trigger event on the selected
A Trigger input will assert the A Trigger output gates.
Each differential trigger gate is inverted and current
buffered by a pair of differential transistors that allow quick
response to the trigger edges by Trigger Logic
Array U370.
T rig g e r L o g ic
The Trigger Logic circuit consists primarily of Trigger
Logic Array U370. The Trigger Logic Array provides final
trigger-source selection; trigger-point delays, delayed
either by a specified amount of time or by a specified
number of events; and ramp-control signals to the Jitter-
Correction circuitry for resolving trigger-point ambiguities.
The Trigger Logic Array also produces the trigger and
external clock signals necessary to control operations of
the CCD Phase Clock circuit.
The three enable inputs to U370, E1B (A3), E2B (WR),
and E3B (ACQSEL), are all set LO whenever writing to
addresses between 6080h and 6087h to enable the
address inputs (A0, A1, and A2). The choice of eight
addresses between 6080h and 6087h provides for different
operating requirements of the Trigger Logic Array.
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