Tektronix 2440, User Manual

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Theory of Operation— 2440 Service
M em ory M od e Control
The Memory Mode Control circuit is made up primarily
of Mode Selector Switch U 501, a quad 2-to-1 multiplexer
that switches control signals between those of Time Base
Controller U670 and those of the Waveform
y P .
Selection
is done by the TB 2M EM signal from AND-gate U731D
pin 11.
The W E (write enable) output from Mode Selector
Switch U501, pin 12, controls both writing into the Acquisi­
tion Memory and incrementing of the Address Counter.
With TB2M EM set LO, the W W R (Waveform
y P
write) sig­
nal gated through OR-gate U512D to the 4A input (pin 13)
of U501 controls writing to the Acquisition Memory. The
S I (output enable) derived from the Waveform
y P
WRD
(Waveform
y P
read signal), controls the output of
Acquisition Memory data. It is asserted LO only when the
Waveform
y P
is trying to read Acquisition Memory
locations.
With TB2M EM HI, the SAVEACQ signal from NAND-
gate U650B, is selected as the W E signal, and the OE is
set HI to disable the Acquisition Memory from outputting
data. Data buffer U613 is enabled by the LO level of the
EOE signal from pin 7 of the Mode Select Switch to con­
nect the Envelope Logic Latch bus to the input bus of the
Acquisition Memory.
When the Waveform
y P
wants to access the Acquisi­
tion Memory, it will set the a Q q line LO to enable its con­
trol signals to the inputs of Mode Logic Switch U501 and
wait for the delayed ACQUIRE signal from U750 (diagram
8) to go LO (indicating that the Time Base Controller is
finished acquiring). When the delayed ACQUIRE goes LO,
the output of AND-gate U731D (TB2M EM ) goes LO and
the Mode Logic Switch select the Waveform
y P
signals to
control the Acquisition Memory. The LO TB 2M EM signal
also sets the Address Counters to their Load state, and
the counter outputs then follow the WAO-WAA (Waveform
y P
address bits 0-A) lines, giving direct access to Acquisi­
tion Memory data locations by the Waveform
y P .
A d dress C ounter
The Address Counter increments the Acquisition
Memory address as each point is saved. Each write into
Acquisition Memory ends with the W E (write enable) signal
going HI, clocking the counter to address the next sequen­
tial Acquisition Memory location.
The TB2M EM signal from AND-gate U731D controls
the mode of the Acquisition Memory Address Counter
(composed of binary counters U300, U400, and U401).
When the TB2M EM signal goes LO, the counters become
“transparent.” This connects the Waveform
y P
address
bus to the address inputs of the Acquisition Memory so
that the Address Counter output follows the WAO-WAA
(Waveform
y P
address bits 0-A) lines. When the TB2M EM
signal is HI, the Time Base Controller is in control of the
Acquisition Memory, and counter will be in its count mode
as the acquired signals are being stored into the Acquisi­
tion Memory.
A cquisition M em ory
Acquisition Memory U600 is a random-access memory
device (RAM) that provides temporary storage of acquired
data points before they are moved into Save Memory.
Analog waveform samples from the CH 1 and CH 2 CCD
arrays are digitized and moved into Acquisition Memory
under control of the Time Base Controller (diagram 8),
alternating CH 1 data with CH 2 data. The Waveform
y P
reads the data out of Acquisition Memory via buffer U610,
unscrambles it, and moves it to proper Save Memory
locations.
MEMORY INPUT BUFFER. Memory Input Buffer U613
applies the time-multiplexed waveform data bytes from the
Acquisition Latches (diagram 15) to the data inputs of the
Acquisition Memory inputs at all times except when the
Waveform
y P
is accessing the Memory. Inverter U620D
inverts the most-significant bit of the sample data so that
range center of the A/D Converter output corresponds to
00 hex (center screen value), thereby creating bipolar data
referenced to center screen.
R ecord-E nd Latch
The Record End Latch composed of U502 and U601
continually latches the address of the last Acquisition
memory location that was written. The latch is clocked on
the rising edge of the W E clock (from the SAVEACQ sig­
nal or the Waveform ^P W W R signal via Mode Logic
Switch U501) and provides the Waveform
y P
with the last
address written (the end of the record for a full acquisition)
by the Time Base Controller or read by the Waveform
y P .
Since the Acquisition Memory addresses are circular, the
start of a FISO record will always be the Record End
address plus one. In Short-Pipe mode, the Waveform
y P
will read those (two for normal, four for envelope) points
immediately preceding (and including) the Record End
address. The latched address (plus the trigger location
data) is placed on the W aveform
y P
data bus by asserting
RDMARO and RDMAR1 (read memory address) lines.
Two-to-one multiplexer U722B applies either trigger-
location bit 4 (TL4) or the Time Base Controller TBTRIG
(time base triggered) status bit to latch U502, depending
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