Tektronix 2440, User Manual

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Theory of Operation— 2440 Service
a line (only the center 40 are displayed) and the next four
LSBs are applied to the Vertical DAC to select 1-of-16
display lines.
Once this rough positioning is done, the Readout State
Machine displays a sequence of dots that make up the
addressed character, each dot being positioned relative to
the rough display position.
Character codes, sequentially read from the Horizontal
RAM, are applied to seven address lines of a character
ROM (U420). These select the block of dot-position data
within the ROM corresponding to that character code. Five
more address bits are generated by an incrementing Dot
Counter (U416B and U416A) and sequentially clock the XY
dot-position data from the selected ROM block. The hor­
izontal and vertical dot-position data is applied to the Hor­
izontal and Vertical DACs and is used to deflect the crt
beam relative to the selected on-screen character position.
The operation of the Readout State Machine is ROM
based; it proceeds through a sequence of states based on
data loaded from a ROM.
Initially, when power is first applied, both the PWRUP
(power up) and DISPLAY signals applied to U450A are LO.
These states cause a LO at the reset input of presettable
counter U231 that resets its output count to zero. The
reset state will remain until the instrument power comes
up (PWRUP goes HI) and the system processor deter­
mines that a display should be produced (it starts the
Display State Machine and DISPLAY goes HI).
With the reset removed, presettable counter U231 is
enabled to either count (up) or do a parallel load from the
four MSBs output from the addressed location within
U232 on the next rising edge of the 5 MHz clock. The
COUNT/LOAD select line from the data selector U230
determines whether counting or loading will occur.
The LOAD/DECIDE bit output from the addressed ROM
location within U232 is applied to the enable input of U230
and determines whether the COUNT/LOAD line is forced
LO (U230 disabled by LOAD/DECIDE being HI) or whether
one of the decision inputs is selected (via select inputs A,
B and C of U230). When the LOAD/DECIDE bit from U232
is LO, it indicates that the state machine is at a decision
point as to whether counter U231 should count or load
(instead of just automatically loading the next state). The
condition tested to make this decision is selected by the
select inputs to U230 and are as follows:
DO— R/O (readout) goes HI when a readout display
should start.
D2— AND gate U233A watches for the 12th character
address (11).
D3— EOCH (end of character) goes LO on the last
character dot and causes the next state to be loaded.
D4— EOL (end of line— X9 bit U440, diagram 16) goes
HI when readout line is over.
D5— AND gate U223B watches for the 64th character
address (63) to indicate that the next character is the
beginning of a new line.
ROM U330, addressed in parallel with U232, outputs
three bits unique to the state selected and is used to clock
the dot counter (U416B and U416A), clock the Display
Counter, and to turn on the Z-Axis for readout dots.
The flow chart in Figure 3-8 illustrates ODeration of the
Readout State Machine.
As the state machine runs, the counter outputs of U231
(the “current-state ”) are first reset to state “ 0 .” The data
output from the 0 4 -0 7 (outputs 4-7) lines of U232 contain
the “next-state" data, 0 1 - 0 3 (outputs 1-3) hold the select
data for the data selector U230, and output OO (output 0)
is the LOAD/DECIDE bit. In addition, the outputs from
U330, used to turn on the Z-Axis if appropriate (RZON),
increment the character ROM dot counter U416B-U416A
(CKDOTCTC), and clock the Display Counter (CLKRAM)
to address the next character, are now at their state 0
condition (all HI).
The COUNT/LOAD signal from U232 determines what
action counter U231 takes when the next 5 MHz clock
occurs. If LO, the data from outputs 0 4 - 0 7 of U232 is
loaded to the counter outputs; if HI, the counter
increments.
The LOAD/DECIDE line, along with the three channel-
select inputs to U230, gives the state machine the ability
to determine when certain events have occurred. When
the LOAD/DECIDE bit from ROM U232 is HI, indicating
that no decisions need be made in the present state, data
selector U230 is disabled and the COUNT/LOAD output to
U231 are forced LO. On the next 5 MHz clock, the “ next-
state" data from U232 (outputs 0 4 -0 7 ) is merely loaded
into counter U231.
If the “ present-state" data output from U232 has the
LOAD/DECIDE bit set LO, indicating that some circuit con­
dition needs to be tested to determine what to do next,
3-7 0