Tektronix 2440, User Manual

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T h eo ry o f O p e ra tio n —2 4 4 0 Service
As indicated by the memory map, addresses from
0000h-7FFFh are overlapping addresses; that is, if they are
originated by the System Processor, they may map to
(access) memory locations or registers connected to either
the System Data Bus or the Waveform Processor Data bus. If
they are originated by the Waveform Processor, they access
the memories indicated on the Waveform Processor Bus.
The following description of the address decoding is for
System Processor addresses and how the System Address
Circuit outputs control signals to the Memory Buffer and to
the address decoding circuit for the Waveform Processor
(diagram 2). For information on how the Waveform Proces­
sor’s address decoding circuitry uses these signals, see
“Waveform Processor Operation” in this section.
A ddresses 800 0 h -F F F h —All addresses from 8000h-FFFFh
have AF set H I. This HI is AF is inverted (via U
866
C) and
routed to U580A. W ith the inverted AF bit holding the input
of AND-gate U580A LO, the output of the gate holds the
Memory Buffer U660 enabled (LO). As shown in the memory
map, all addresses in this range are System ROM accesses
and require System Data Bus connection to the System
Memory Data Bus. Locations 8000h-FFFFh are not used to
address any other memory devices outside System memory
(decoding for the paged System ROM was discussed under
“System ROM” in this section).
A ddresses 0 0 0 0 h -7 F F F h -A II addresses in this range have
the AF bit set LO. With AF LO, the inverted AF signal holds a
HI at one input to the dual-input AND-gate U580A. The
output of this AND-gate (and the enabling of U660) is then
controlled by the output of OR-gate U332A.
When the System Processor wants these address ranges to
map to the Waveform Processor Data Bus (i. e., wants the
System Data Bus and the Waveform Data Bus connected), it
either asserts BUSREQ to the Waveform |j.P to receive
BUSGRANT, or it asserts BUSTAKE to force BUSGRANT.
BUSGRANT at the Input of OR-GATE U250D forces a HI to
the input of AND-gate U862B. If this is not a MAIN or MAIN2
memory access, MAIN and MAIN2 from 1-of-8 Decoder
U
668
are both HI and U862B output is driven HI by the
BUSGRANT. This HI is coupled through U332A and U580A
to disable the U660 Memory Buffer and disconnect the
System Data Bus from System Memory. MAIN and MAIN2
are routed to decoding circuitry and used to connect the
System Data Bus to the Waveform Data Bus (see “System
)iP Access” under “Waveform Processor Operation” in this
section).
If either of the host RAM enables MAIN or MAIN2 are LO, the
1-of-8 decoder U
668
has decoded address lines AC, AD,
and AE to determine that the addresses range from
4000h-4FFFh or from 7000h-7FFFh. In these address
ranges, the LO host RAM enable holds off the BUS-
GRANT-forced HI at the output of U250D from driving the
output of AND-gate U862B HI. If the System Processor is
accessing these locations in Waveform Processor RAM, it
asserts WFRAM HI (Waveform RAM) at the input to OR-gate
U332A. This HI is coupled through U332A and AND-gate
U580 to disable U660 regardless of BUSGRANT, MAIN and
MAIN2. BUSGRANT and WFRAM are routed to decoding
circuitry to connect the System DATA Bus to the Waveform
Data Bus.
If the System Processor is NO T accessing Waveform Pro­
cessor RAM for the 4000h-4FFFh or 7000h-7FFFh address
space, WFRAM is disabled LO. With either MAIN or MAIN2
enabled LO, the output of U862B is driven LO. This LO lets
OR-gate U332A, and then AND-gate U580A, switch LO and
enables Memory Buffer U660 to connect the System Data
Bus to the System Memory Bus. The MAIN and MAIN2
memories are then accessed.
If the System Processor is N O T accessing Waveform Pro­
cessor RAM or a MAIN-section of System RAM, BUSGRANT
and WFRAM are NO T asserted HI and MAIN and MAIN2 are
not asserted LO. In this case, the output of four-input
AND-gate U862A controls the enabling/disabling of the
Memory Buffer. U862A combines with AND-gate U432B to
form a five-input AND-gate function, with output Y 0-Y 3 and
Y5 connected to the five inputs. If the address is in the range
of 0000h-4FFFh or 5000h-5FFFh, 1-of-8 decoder U
668
decodes a LO output to one of the five ANDed inputs. U862A
outputs a LO which is ORed (by U250D) with the disabled
BUSGRANT (LO) to hold off AND-gate U862B. The LO at the
output of U862B is passed through U332A (WPRAM is LO)
and U580A to enable the Memory Buffer and connect the
System Data Bus to the System Memory. The LO output of
U322A, CYSYS, also enables the System RAM for this
Miscellaneous RAM access.
A ddresses 6 0 0 0 h -6 F F F h —Addresses in this range either
access devices on the Waveform Processor bus or directly
access devices on the System Data Bus. If the address is in
this range, U
668
decodes Y
6
, HM M IO LO.
Since Y
6
is LO, all other outputs, including those driving the
five inputs to AND-function U862A/U432B, are HI. With the
five inputs to AND-function U862A/U432B all HI, its output is
HI to U862. With the remaining two decoder outputs U862B,
MAIN and MAIN2, set HI, AND-gate U862B outputs a HI that
holds the Memory Buffer disabled for ALL HMM IO accesses.
HMMIO is inverted via U
866
B and is routed, along with
address bits A3 and A4, to decoding circuitry (Diagram 2) to
determine when the System Data Bus connects to the
Waveform Data Bus for HMMIO accesses.
3-19