Maintenance— 2440 Service
2330
U130
6-62
Table 6-6 (cont)
Ramp Buffer A 11U 130 (schematic diagram 16):
Testing Method:
If run from this level, all four tests are selected in turn, or one may execute any one test by selecting
2331 to 2334.
This test requires the display state machine to be operative. There is no “good’’ way to ensure that it
is functional, and there have been no previous tests to help to find that out. Therefore, if this test fails,
it could be for several reasons other than U 130. If the power-on Self Test starts to run but halts at
test level 3000 or test level 6000 (as indicated by the lighted Trigger LEDs), the problem may be in the
Display S tate Machine circuit (schematic diagram 17) or the DISDN signal path to the System
pP
Inter
rupt circuit. Use the Display Troubleshooting Chart to troubleshoot the Display S tate Machine and
check that the DISDN signal at U 414 pin 5 is correct.
Initialization:
DISCO N = 01100000. Significant bits are b2, b5, b6, and b7 (STO P D IS , enable “Q " bus, not ENV
mode).
MODECON = 00001000. Significant bit is b3 (U 140 lower half).
M IS C = 00100000. Significant bit is b5 (ZA XIS OFF).
The test result = PASS.
The test is to load a pattern into the display counters, U 220 and U 211, with the LDCOUNT strobe
(data loaded to U 222 is fixed). Their outputs are selected by U 221, U 212, U 210 holding U414A in the
reset mode and not PRESTART. Since the STO P D IS line is LO, the display counters are selected as
the source to the Q bus (U 210, U 212, U221). The inputs to U 130 are the bits Q 1..Q 5 where Q 1..Q 3 =
0. and Q4, Q5 are the bO, b l data of pattern. To read back properly, shift the pattern left 3 bits and
use only the lower 5 bits of XDIAG (U 243).
Test 1. 10100101 is loaded and read back via U 243. Test result is set to fail if not a match on bits 0
through 5.
Test 2. 01001011 is loaded and read back via U 243. Test result is set to fail if not a match on bits 0
through 5.
Test 3. 10010110 is loaded and read back via U 243. Test result is set to fail if not a match on bits 0
through 5.
Test 4. 00101101 is loaded and read back via U 243. Test result is set to fail if not a match on bits 0
through 5.
Troubleshooting Procedure:
NOTE
QO through Q3 = 0. Q4 through Q11 map to DO through D7; i.e., Q4
=
d3. By knowing
which test FAILs and the bit pattern one may easily determine the problem bit(s) (look for
the bit column in the failed tests that are the same).
If 2 or 3 tests fail, then there is a bus problem of some sort and they must be exam ined. If all four
tests FAIL, then the problem can be in several locations.
Summary of Contents for 2440
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Page 91: ...Theory of Operation 2440 Service 3 49 Figure 3 5 Simplified CCD architecture ...
Page 120: ...Theory of Operation 2440 Service Figure 3 10 DC Restorer 3 78 ...
Page 130: ...Theory of Operation 2440 Service 3 88 ...
Page 136: ...Theory of Operation 2440 Service Figure 3 15 PWM Regulator and Inverter 3 94 ...
Page 138: ...Theory of Operation 2440 Service Figure 3 16 PWM switching waveforms 3 96 ...
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Page 423: ...2440 Service Figure 9 4b 2440 Block diagram part 2 6330 27 BLOCK DIAGRAM PART 2 ...
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Page 428: ...2440 Service WAVEFORMS FOR DIAGRAM 1 6 2 8 5 3 2 ...
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Page 432: ...2440 Service WAVEFORMS FOR DIAGRAM 2 BUS ISOLATED 6 6 0 3 4 9 ...
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Page 517: ...10 16 R E V J U L 1993 Replaceable Mechanical Parts ...
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