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Theory of Operation—2440 Service
Selection of the CH 1— Side 1 current signal to be
digitized by the A/D Converter is controlled by the
MSlI
(Multiplexer Select-Channel 1— Side 1) line. As shown in
Figure 3-3, only one of the eight MS signals will be LO at
any time. A LO M S 1 1 signal applied to the base of Q773
will turn that transistor off. The other transistors of CH 1
(Q873, Q770 and Q870) and all of the CH 2 transistors
(Q783, Q883, Q780 and Q880) are on to shunt their
associated signal currents to ground. Each of the eight
shunting transistors will be turned off in sequence to allow
its associated signal current to pass to the CCD DATA
node via a series common-base transistor (Q775 for
Channel 1— Side 1). The resulting CCD DATA signal is a
time-multiplexed combination of all eight CCD output chan
nels (four from CH 1 and four from CH 2).
Precise current matching of the signal offsets for the
four sides of Channel 1 is achieved by setting the DAC-
generated CT11 (Center 11), CT12, CT13 and CT14
voltages at self-calibration. Similar offset matching for
CH 2
is
done with
the
C T21,
CT22,
CT23
and
CT24 signals.
S econdary Supplies
The Secondary Supplies circuit, composed of U861A,
U861B, U861C, U861D, and associated components, pro
vides operating voltages used by the CCD Output circuitry.
The voltage level of the A2D REF ( - 0 . 5 V analog-to-digital
reference) is determined by the current through R861 from
operational amplifier U861C and is set by the resistive
divider string formed by R763 and R764 from the
+ 10 VREF supply. The other voltage outputs (+ 8 .5 V and
+ 10 VRA and + 1 0 V R B are set by the various taps on
the resistive voltage divider and buffered by operational
amplifiers.
A/D CONVERTER AND
ACQUISITION LATCHES
The
A/D
Converter
and
Acquisition
Latches
(diagram 15) circuit consists of eight-bit A/D Converter
U560, eight-bit Min-Max Comparator U740 and U732 (for
ENVELOPE acquisitions), Acquisition Latches U631, U632,
U630, and U640, and latch switching circuitry to direct and
latch the acquired data point values.
A /D C onverter
A/D Converter U560 is an 8-bit flash converter that digi
tized the analog samples from the CCD arrays at an
overall conversion rate of 4 MHz.
The A2D REF voltage (— 0.5 V) is amplified and
inverted by U880 to produce the 1.5 V reference voltage
used by the A/D Converter. Noise and ripple are filtered
from the amplified reference voltage by L770, C570, and
C776. The negative side of the reference is tied to ground;
therefore, input voltage for conversion may range from 0 V
to + 1 .5 V. The time-multiplexed CCD Data signal current
develops a voltage across R880 that is offset by the A2D
REF voltage. It is then amplified and inverted by U780 to
produce an input signal to the A/D Converter within the
0 V to + 1 .5 V range needed. The amplified signal is
applied to the analog input of U560 after being filtered by
L780 and C770.
The input sample is converted on the falling edge of
SHIFT, a 4 MHz clock signal. A valid data byte represent
ing the analog input voltage appears on the output of the
A/D Converter approximately 20 ns later. That data byte is
applied to the 8-bit Magnitude Comparator formed by
U740 and U732, with the four LSBs going to U740 and
the four MSBs of the byte going to U732.
E n velop e M in -M ax C o m p arato r
For ENVELOPE Mode acquisitions, glitch-catching at
the slow SEC/DIV settings is done by the Envelope Min-
Max Comparator circuit formed by four-bit comparators
U740 and U732. At SEC/DIV settings slower than 50 #ts,
analog Peak Detectors U440 and U340 provide more
samples than needed to fill the required 50 data points
(25 min-max pairs) per division, so not all are saved.
During each envelope sampling interval (1/50 of the
SEC/DIV setting at 50
ns
and slower), the M in-Max Com
parator compares every Peak Detector min/max value
from A/D Converter U560 to the last-latched maximum or
minimum byte to determine which sample will be saved. If
the new byte value is greater than the latched byte value,
the MAX output of Comparator U732 (pin 5) will go HI; if
less than the latched value, MIN at pin 7 will go HI. If the
A/D output value is equal to the latched value, both con
nected outputs of Magnitude Comparator U732 will remain
LO. The final min byte and max byte obtained from each
channel during an envelope sampling interval are saved to
the
Acquisition
Memory
as
part
of the
envelope
waveform record.
Since the input to the A/D Converter is time multiplexed
between C H I maximum, CH2 maximum, C H I minimum,
and CH2 minimum values from the Peak Detectors, the
latched data applied to the Magnitude Comparator from
the Max/Min Latches must also be time multiplexed to
maintain the correct relationship for making the comparis
ons (CH 1
maximum against CH 1
maximum, CH 1
minimum against CH 1 minimum, etc.). The necessary time
multiplexing
is
done
by
the
Envelope
Latching
Logic circuitry.
3-62
Summary of Contents for 2440
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Page 91: ...Theory of Operation 2440 Service 3 49 Figure 3 5 Simplified CCD architecture ...
Page 120: ...Theory of Operation 2440 Service Figure 3 10 DC Restorer 3 78 ...
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Page 136: ...Theory of Operation 2440 Service Figure 3 15 PWM Regulator and Inverter 3 94 ...
Page 138: ...Theory of Operation 2440 Service Figure 3 16 PWM switching waveforms 3 96 ...
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