Tektronix 2440, User Manual

Page: 87 / 531

Theory of Operation— 2440 Service
between + PICK (pin 12) and — PICK (pin 15) of U420. Any
common-mode signals present are inverted and applied to
a common-mode point between R133 and R235 to cancel
the signals from the differential output. A filter network
composed of LR421 and a built-in circuit board capacitor
reduces trigger noise susceptibility.
The drain voltage for the input FET of the Preamplifier
is provided by the circuit composed of VR420, R512,
R515, and R516. Resistors R516 and R515 are part of the
self-calibration circuitry and are used to match the gain of
the CH1-BAL signal (pin 2) with that of the output of the
attenuator.
C h a n n e l 2 P re a m p lifie r
Operation of Channel 2 Preamplifier U320 is nearly
identical to that of the Channel 1 Preamplifier just
described. The exceptions are that the signal obtained
from the pickoff reverse-termination return (pin 11) is used
to drive the rear-panel CH 2 OUT connector and that the
signal from the positive trigger pickoff (pin 12) is used to
drive the Video Option Back-Porch Clamp circuit (diagram
21). The output of that clamp circuit is an offset signal,
applied to the Channel 2 Preamplifier at pin 3, that is used
to remove ac power-supply hum from the display of a
video signal applied to the Channel 2 input when the Video
option is in use.
The amplified Channel 2 + P R T R signal from U320 pin
11 provides an accurate representation of the Channel 2
signal at the rear-panel CH 2 OUT connector. The + PRTR
pickoff signal is applied to the emitter of Q240B via a volt­
age divider formed by R234, R241, and R240. Transistor
Q240B, configured as a diode, provides thermal compen­
sation for the bias voltage of Q240A and reduces dc level
shifts with varying temperature. Emitter-follower Q240A
provides the drive and impedance matching to the CH 2
OUT connector and removes the diode drop added by
Q240B. Clamp diodes CR140 and CR141 protect Q240A
should a drive signal be accidentally applied to the CH 2
OUT connector.
E x te rn a l T rig g e r P re a m p lifie r
The functions provided by External Trigger Preamplifier
U100 are similar to those provided by the Channel 1 and
Channel 2 Preamplifiers. The single-ended EXT TRIG 1
and EXT TRIG 2 input signals are buffered by U100 and
routed to A/B Trigger Generator U150 (diagram 11) where
they are available for selection as the trigger source for
either the A or B trigger signal.
External trigger signal sensitivities may be set by the
user to allow triggering ranges of either ± 0 .9 volts (EXT
-r- 1) or ± 4 .5 volts (EXT ± 5). Larger applied voltages on
the external trigger inputs will exceed the control ranges of
the Trigger System. The logic levels of control bits applied
to U 100 pin 30 (GA3) and pin 31 (GA4) from Source Select
Control Register U140 (diagram 5) set the gain of the EXT
1 and EXT 2 Preamplifiers respectively.
Dc offsets in the output signal due to any tracking
differences between the + 5 V and the —5 V supply to
U100 are reduced by the Tracking-Regulator circuit com­
posed of U120, Q U O , and associated components. Opera­
tional amplifier U120 and Q U O is configured so that the
output voltage at the emitter of Q U O follows the - 5 V
supply applied to R210. This tracking arrangement
ensures that the supply voltages are of equal magnitude to
minimize dc offsets in the output signals.
PEAK DETECTORS AND
CCD/CLOCK DRIVERS
The Peak Detectors and CCD/Clock Driver arrays
(diagram 10) form what is essentially a very fast analog
shift register. Waveform samples from each Preamplifier
(U320 and U420, diagram 9) are loaded into the shift regis­
ter array at a selected sample rate up to 500 Megasam­
ples per second and clocked out of the array at a slower,
fixed rate for digitization by the A/D Converter (see
diagram 15).
Peak Detectors U340 and U440 are hybrid devices hav­
ing two modes of operation: “track” and “peak detect.”
For NORMAL and AVG (average) acquisition modes, the
Peak Detectors track the input signal and provide signal
gain from the Preamplifiers to the CCD arrays. In the
peak-detect mode used for ENVELOPE acquisitions at
sweep speeds of 500 ns per division and slower, the Peak
Detectors detect and hold the most positive and the most
negative amplitude value of the input signal that occurs
during each sampling interval. The peak values are
amplified as in the NORMAL and AVG modes and applied
to the input registers of the CCD arrays to produce a com­
posite waveform of the most positive and most negative
waveform amplitudes.
CCD/Clock Drivers U350 and U450 are hybrid devices
containing a charge-coupled device (CCD) integrated
circuit, a Clock Driver integrated circuit, and a symmetry-
delay adjustment integrated circuit. The charge-coupled
devices are very fast analog shift registers. Differential sig­
nals applied to the inputs of the C CD ’s from the Peak
Detectors are sequentially clocked into the CCD registers
at the processor-selected sample rate as determined by
the SEC/DIV switch setting. Movement of the analog
samples through the CCD arrays is controlled by the Clock
Driver circuitry of the devices. Shifting the samples out of
the CCD to be digitized is done with the combined clocking
action of the internal Clock Drivers and the clock signals
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