Tektronix 2440, User Manual

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T h eo ry o f O p e ratio n - 2 4 4 0 Service
higher memory location. This address selection schem e is
the “double-fetch” of instruction data mentioned previously
in the Waveform pP description.
Removing jum per P128 disables the Waveform ROMs and
places their outputs into the high-im pedance state. The
pull-up and pull-down resistors within resistor packs R474
and R590 place a “NOP” (no-operation) instruction byte on
the instruction bus. A NOP command causes the Waveform
pP to increment through the first 12 bits of its address range
on the 16-bit DAD bus and through all the addresses of its IA
bus. This “KERNEL” mode allows the Waveform pP address
bus and address decoding to be exercised for troubleshoot­
ing and diagnostic purposes.
A ddress D eco d e
The Address Decode circuit monitors the Waveform pP
address bus to develop the appropriate enabling signals to
the memory or I/O device that is to be accessed.
Block decoding is done by one-of-eight decoder U570,
which uses address lines WAC-WAF to separate the ad­
dresses below 32 K into eight 4 K blocks. Decoder U570 is
enabled when a valid address (WVMA HI) below 32 K
(address bit WAF LO) is placed on the memory address bus
by either the Waveform pP or the System pP. The next three
lower address lines (WAE, WAD, and WAC) determine which
one of the eight outputs of the Decoder will be selected.
Table 3-4 illustrates this address decoding.
A ddresses OOOOh-IFFFh—Accesses in this
8
k Block are
mapped to U350, the Save RAM. U570, a 1-of-8 decoder,
outputs a LO at either Y0 or Y1 for all addresses within this
block and His on Y2-Y7. A LO at either Y0 or Y1 causes
AND-gate U580C (functioning as a negative-logic OR gate)
to output a LO SAVE enable. This LO is inverted twice via
Q244 and Q332 and holds the chip-select input of Save
RAM U350 enabled LO. Since this address block is the only
block that accesses the SAVE memory, when other address
blocks are decoded by U570 (in the descriptions to follow),
Y0 and Y1 are HI and U350 disabled via Q244 and Q332.
NOTE
The chip-select circuit between the SAVE
output of U580C and RAM U350 is identical to
that for the System
p
P RAM (U664, diagram 1).
The circuit determines chip selection during
normal operation and isolates the Save RAM
chip-select input when power is off.
Table 3 -4
W aveform pP A ddress D ecoding
A ddress Bits O utput Signal (Active LO)
WAE WAD
WAC
LO LO LO (Y0 or Y1) AVE from
NAND-gate
LO LO HI U580C to enable the SAVE
memory
LO HI LO (Y2) D IS P -S e le c ts display
memory
LO
HI
HI
(Y3) D A T A -S elects attribute
memory
HI
LO LO
(Y4) A C Q -S e le c ts acquisition
memory
HI
LO
HI (Y5) W PCM DN /C O EFF—
Selects either the command or
the coefficient memory
HI HI LO (Y
6
) W M M IO -E n a b le s
Waveform pP memory-
m apped I/O Decoder U540
HI HI HI (Y7) W P R A M 2-D ecoded to
enable waveform processor
RAM U440
The Save RAM is divided into four
8
K pages with only two
pages used. Since the OOOOh-IFFFh addresses can only
address
8
K of memory, the two bits, SVPGO and SVPG1,
select which
8
K page the 0000h-1 FFFh addresses (an
8
K
address block) map to by controlling address bits AD and
AE of U350. These lines, in turn, are controlled by the two
lower Waveform Data Bus bits WDO and WD1 via the Inter­
rupt Latch U550.
Normally, SVPGO and SVPG1 are always set HI allowing the
8
K address block to always address the same page. How­
ever, when the Vertical mode is ADD or MULT at the same
tim e the Acquire mode is ENVELOPE, additional Save
memory space is required. Therefore, the Waveform pP will
switch those lines LO to select another page as required.
The System pP also switches those lines via the Waveform
Data Bus when running internal diagnostic checks on the
Save RAM.
W riting to or reading from any of the Waveform pP RAM
space is done via bidirectional Bus Buffer U352. When Save
RAM U350 is selected by the SAVE line going LO, U352 is
also enabled via AND-gate U580D. The state of the WWR
(waveform write) control line determines the direction of the
data transfer.
3-26