Theory of Operation—2440 Service
V ertical D isplay RAM
Vertical
Display
RAM
U431
stores the vertical-
deflection data for four 512-point waveforms. Data points
to be displayed are written from the Save Memory into the
RAM by the Waveform
y P
(diagram 2) on the W D bus
(waveform data bus) via bus transceiver U322. The stored
waveform display bytes are read sequentially out of the
Vertical Display RAM in blocks under control of the
Display Counter (diagram 17) and applied to Vertical DAC
U 142 to produce the analog vertical deflection signal of the
displayed waveform.
To write data into the Vertical Display RAM, the
Waveform
y P
puts the data byte to be written onto its WD
bus and sets its WRD (waveform read) bit HI. This HI
enables bus transceiver U322, and the vertical data is
applied to I/O (in/out) pins of the RAM. At the same time,
the DISP signal is address decoded LO (from decoder
U570, diagram 2) for addresses between 8K and 12K, and
the WAB address bit applied to U323B selects the Vertical
RAM U431 via U421A. When the Waveform
y P
generates
its write pulse (WWR), it is transmitted through U422A and
U422D, writing data into the Vertical Display RAM. This
process occurs for each data byte (point) of waveform
information.
To display the stored data points, the System
y P
loads
the starting address of the data block to be displayed into
the Display Counter and selects the Display Counter to
address the Vertical Display RAM (via the Address Multi
plexer). The System
y P
also sets the YON (vertical display
on) bit applied to U421A and U421B LO, selecting the
Vertical Display RAM and enabling its outputs. As the
Display Counter increments, the selected block of data is
sequentially clocked out onto the DY bus (vertical-display
data bus) and applied to Vertical DAC U142 to produce
the vertical deflection signal current to the Vertical Output
Amplifiers.
If the Waveform
y P
needs to read data from the Verti
cal Display RAM, it outputs an address within 8K to 10K
address space of the RAM. This address block is decoded
by U323B to enable both the Vertical Display RAM (via
U421 A) and bus transceiver U322. Since the Waveform
y P
is trying to read data, its W RD (waveform processor read)
line will be set LO. This enables the RAM outputs via
U323C and U421B and causes buffer U322 to direct the
data onto the Waveform
data bus.
Horizontal Display RAM
Operation of Horizontal Display RAM U440 is identical
to that of the Vertical Display RAM just described. The
Horizontal RAM chip select (CSX) is gated through U323D
for addresses between 10K and 12K when DISP is LO.
Data that may be stored in the Horizontal Display RAM
includes two 512-point waveforms and IK
x
8 of readout
information. During a waveform display, the data output
from the Horizontal RAM may be routed to either the Vert
ical DAC or Horizontal DAC, providing for either two more
YT displays or two XY displays.
A ttributes RAM
Attributes RAM U430 contains 4K
X
1 points of data
that tell the Z-Axis system (using the BRIGHTZ signal)
whether or not a data point read from either the Vertical
Display RAM or the Horizontal Display RAM should be
intensified. Operation of the RAM is similar to that just
described for the Vertical and Horizontal RAMs except
that the data path is only one bit wide.
The write enable of the Attribute R A M JW R A ) is gated
by U422C between 12K and 14K w hen DATT is LO from
decoder U570 (diagram 17). W RA going LO enables the
data from bit W D7 of the data bus to be written to the
addressed location. Gate U422A prevents the W W R clock
from being gated to U422C if the Display Counter is
selected (Waveform
y P
not in control of the address bus).
To read attribute data out of the RAM, the Waveform
y P
sets W RD LO. This LO, along with the address-
decoded DATT (attribute data) line, enables buffer U423A
and places the addressed output bit from the DO output of
U430 onto bit W D7 of the data bus.
When displaying data from either (or both) the Vertical
RAM or Horizontal RAM (the addresses applied to all
three RAM chips are the same), the attribute data for each
data point will be applied to the Z-Axis circuit to determine
the intensity of each point. A HI bit from the DO output of
U 430 will intensify the displayed point.
H orizontal D ata Buffers
The Horizontal Data Buffers, U320 and U 321, are used
to route the data from the Horizontal RAM to either the
Horizontal DAC or the Vertical DAC, depending on the
type of display being produced.
For normal waveform displays, vertical deflection data
may come from either the Vertical or the Horizontal
Display RAM. To route data from the Horizontal RAM to
the Vertical DAC, the outputs of the Vertical RAM will be
disabled (OEY), the outputs of the Horizontal RAM will be
enabled (OEX goes LO), and buffer U320 will be enabled
(XTOVERT goes LO). These three signals are all con
trolled by the System /iP by writing bits XON and XTO
VERT HI into Mode Control Register U541 (diagram 17)
3-64
Summary of Contents for 2440
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