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Section 13 Bus State Controller (BSC)

SH7751 Group, SH7751R Group

Page 380 of 1128

R01UH0457EJ0301 Rev. 3.01

Sep 24, 2013

Bits 12 to 10—CAS-Before-RAS Refresh

RAS

Assertion Period (TRAS2–TRAS0):

When the

DRAM interface is set, these bits set the

RAS

assertion period in CAS-before-RAS refreshing.

When the synchronous DRAM interface is set, the bank active command is not issued for a period
set by TPC[2:0] and TRAS[2:0] bits after an auto-refresh command is issued.

Note: For setting values and the period during which no command is issued, see 23.3.3, Bus

Timing.

Bit 12: TRAS2

Bit 11: TRAS1

Bit 10: TRAS0

RAS

/DRAM

Assertion Time

Command Interval after
Synchronous DRAM
Refresh

0 0 0 2 4

+

TRC

(Initial

value)

1

3

5

+

TRC

1 0 4 6

+

TRC

1

5

7

+

TRC

1 0 0 6 8

+

TRC

1

7

9

+

TRC

1 0 8 10

+

TRC

1

9

11

+

TRC

Note: TRC (Bits 29 to 27): RAS precharge interval at end of refresh

Bit 9—Burst Enable (BE):

Specifies whether burst access is performed on DRAM interface. In

synchronous DRAM access, burst access is always performed regardless of the specification of
this bit. The DRAM transfer mode depends on EDOMODE.

BE EDOMODE 8/16/32/64-Bit

Transfer

32-Byte Transfer

0 0

Single

Single

1

Setting

prohibited

Setting prohibited

1 0

Single/fast

page

*

Fast page

1

EDO

EDO

Note:

*

In fast page mode, 32-bit or 64-bit transfer with a 16-bit bus, 64-bit transfer with a 32-bit

bus

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Summary of Contents for SH7751 Group

Page 1: ... Hardware Rev 3 01 Sep 2013 Renesas 32 Bit RISC Microcomputer SuperH RISC engine Family SH7750 Series 32 The revision list summarizes the locations of revisions and additions Details should always be checked by referring to the relevant text ...

Page 2: ...Page ii of liv R01UH0457EJ0301 Rev 3 01 Sep 24 2013 ...

Page 3: ...ange movement power voltage range heat radiation characteristics installation and other product characteristics Renesas Electronics shall have no liability for malfunctions or damages arising out of the use of Renesas Electronics products beyond such specified ranges 7 Although Renesas Electronics endeavors to improve the quality and reliability of its products semiconductor products have specific...

Page 4: ...ined the register settings and the output state of each pin are also undefined Design your system so that it does not malfunction because of processing while it is in this undefined state For those products which have a reset function reset the LSI immediately after the power supply has been turned on 4 Prohibition of Access to Undefined or Reserved Addresses Note Access to undefined or reserved a...

Page 5: ...use this manual basic knowledge of electric circuits logic circuits and microcomputers is required This hardware manual contains revisions related to the addition of R mask functionality Be sure to check the text for the updated content Purpose This manual provides the information of the hardware functions and electrical characteristics of the SH7751 and SH7751R The SH 4 Software Manual contains d...

Page 6: ...ardware Manual This manual SH 4 Software Manual REJ09B0318 0600 User manuals for development tools Name of Document Document No SuperH C C Compiler Assembler Optimizing Linkage Editor User s Manual REJ10B0047 0100H SuperH RISC engine Simulator Debugger User s Manual REJ10B0210 0300 High performance Embedded Workshop User s Manual REJ10J1554 0100 ...

Page 7: ...751RBG240 292 pin BGA 22 2 1 PCI Configuration Register 0 PCICONF0 857 Note amended Note The vendor ID H 1054 specifies Hitachi Ltd but the SH7751 and SH7751R are now products of Renesas Electronics Corp For information on these products contact Renesas Electronics Corp 22 12 5 Notes on Parity Error Detection during Master Access 980 981 Newly added 23 1 Absolute Maximum Ratings Table 23 1 Absolut...

Page 8: ...51RBP240 V HD6417751RBG240 V HD6417751RBA240HV 996 Table title amended Table 23 11 Clock Timing HD6417751RBP200 V HD6417751RBG200 V HD6417751RBA240HV 997 Table title amended and note added Note This is the case when the device in use is an HD6417751RBA240HV running at 200 MHz 23 3 1 Clock and Control Signal Timing Table 23 14 Clock and Control Signal Timing HD6417751RBP240 V HD6417751RBG240 V HD64...

Page 9: ...ming Table 23 19 Control Signal Timing 1012 Table amended and note added HD6417751 RBP240 V HD6417751 RBG240 V HD6417751 RBA240HV HD6417751 RBP200 V HD6417751 RBG200 V HD6417751 RBA240HV 2 HD6417751 RF240 V HD6417751 RF200 V 1 1 1 1 Item Symbol Min Max Min Max Min Max Min Max Unit Figure Notes 1 VDDQ 3 0 to 3 6 V VDD 1 5 V Ta 20 to 75 C 3 CL 30 pF PLL2 on 2 This is the case when the device in use ...

Page 10: ...Hz 4 Ta 40 to 85 C for the HD6417751RBA240HV Table title amended and note added Notes 1 HD6417751RF240 V HD6417751RF200 V 2 Ta 40 to 85 C for the HD6417751RBA240HV Table 23 25 PCIC Signal Timing in PCIREQ PCIGNT Non Port Mode 1 HD6417751RBP240 V HD6417751RBP200 V HD6417751RBG240 V HD6417751RBG200 V HD6417751RBA240HV HD6417751RF240 V HD6417751RF200 V VDDQ 3 0 to 3 6 V VDD 1 5 V Ta 20 to 75 C 2 CL 3...

Page 11: ...40HV 1094 Figure newly added D 2 Handling of Unused Pins Table D 4 Handling of Pins When PCI Is Not Used 1105 Table amended Pin Name I O Handling AD31 AD0 I O Pull up to 3 3 V Appendix H Product Lineup Table H 1 SH7751 SH7751R Product Lineup 1125 Table note amended Notes 1 Contact a Renesas sales office regarding product versions with specifications for a wider temperature range 40 to 85 C The wid...

Page 12: ...Page xii of liv R01UH0457EJ0301 Rev 3 01 Sep 24 2013 All trademarks and registered trademarks are the property of their respective owners ...

Page 13: ... Floating Point Registers 53 2 2 4 Control Registers 55 2 2 5 System Registers 56 2 3 Memory Mapped Registers 58 2 4 Data Format in Registers 59 2 5 Data Formats in Memory 59 2 6 Processor States 60 2 7 Processor Modes 62 Section 3 Memory Management Unit MMU 63 3 1 Overview 63 3 1 1 Features 63 3 1 2 Role of the MMU 63 3 1 3 Register Configuration 66 3 1 4 Caution 66 3 2 Register Descriptions 67 3...

Page 14: ... 6 3 Instruction TLB Protection Violation Exception 89 3 6 4 Data TLB Multiple Hit Exception 90 3 6 5 Data TLB Miss Exception 91 3 6 6 Data TLB Protection Violation Exception 92 3 6 7 Initial Page Write Exception 93 3 7 Memory Mapped TLB Configuration 94 3 7 1 ITLB Address Array 94 3 7 2 ITLB Data Array 1 95 3 7 3 ITLB Data Array 2 96 3 7 4 UTLB Address Array 97 3 7 5 UTLB Data Array 1 98 3 7 6 UT...

Page 15: ...25 4 6 1 IC Address Array 125 4 6 2 IC Data Array 127 4 6 3 OC Address Array 128 4 6 4 OC Data Array 129 4 6 5 Summary of Memory Mapped OC Addresses 130 4 7 Store Queues 131 4 7 1 SQ Configuration 131 4 7 2 SQ Writes 131 4 7 3 Transfer to External Memory 132 4 7 4 Determination of SQ Access Exception 133 4 7 5 SQ Read SH7751R only 133 4 7 6 SQ Usage Notes SH7751 Only 134 Section 5 Exceptions 137 5...

Page 16: ...ating Point Status Control Register FPSCR 179 6 3 3 Floating Point Communication Register FPUL 180 6 4 Rounding 181 6 5 Floating Point Exceptions 181 6 6 Graphics Support Functions 183 6 6 1 Geometric Operation Instructions 183 6 6 2 Pair Single Precision Data Transfer 184 6 7 Usage Notes 185 6 7 1 Rounding Mode and Underflow Flag 185 6 7 2 Setting of Overflow Flag by FIPR or FTRV Instruction 186 ...

Page 17: ...Register 00 CLKSTP00 246 9 2 6 Clock Stop Clear Register 00 CLKSTPCLR00 247 9 3 Sleep Mode 248 9 3 1 Transition to Sleep Mode 248 9 3 2 Exit from Sleep Mode 248 9 4 Deep Sleep Mode 248 9 4 1 Transition to Deep Sleep Mode 248 9 4 2 Exit from Deep Sleep Mode 249 9 5 Pin Sleep Mode 249 9 5 1 Transition to Pin Sleep Mode 249 9 5 2 Exit from Pin Sleep Mode 249 9 6 Standby Mode 249 9 6 1 Transition to S...

Page 18: ...uit 2 Is Off 278 10 5 2 Changing PLL Circuit 1 Starting Stopping When PLL Circuit 2 Is On 278 10 5 3 Changing Bus Clock Division Ratio When PLL Circuit 2 Is On 279 10 5 4 Changing Bus Clock Division Ratio When PLL Circuit 2 Is Off 279 10 5 5 Changing CPU or Peripheral Module Clock Division Ratio 279 10 6 Output Clock Control 280 10 7 Overview of Watchdog Timer 280 10 7 1 Block Diagram 280 10 7 2 R...

Page 19: ... Minute Alarm Register RMINAR 300 11 2 11 Hour Alarm Register RHRAR 301 11 2 12 Day of Week Alarm Register RWKAR 301 11 2 13 Day Alarm Register RDAYAR 302 11 2 14 Month Alarm Register RMONAR 303 11 2 15 RTC Control Register 1 RCR1 303 11 2 16 RTC Control Register 2 RCR2 305 11 2 17 RTC Control Register RCR3 and Year Alarm Register RYRAR SH7751R Only 308 11 3 Operation 309 11 3 1 Time Setting Proce...

Page 20: ...r 333 12 5 4 External Clock Frequency 333 Section 13 Bus State Controller BSC 335 13 1 Overview 335 13 1 1 Features 335 13 1 2 Block Diagram 337 13 1 3 Pin Configuration 338 13 1 4 Register Configuration 340 13 1 5 Overview of Areas 341 13 1 6 PCMCIA Support 344 13 2 Register Descriptions 348 13 2 1 Bus Control Register 1 BCR1 348 13 2 2 Bus Control Register 2 BCR2 357 13 2 3 Bus Control Register ...

Page 21: ...on between Master and Slave 495 13 3 15 Notes on Usage 495 Section 14 Direct Memory Access Controller DMAC 497 14 1 Overview 497 14 1 1 Features 497 14 1 2 Block Diagram SH7751 500 14 1 3 Pin Configuration SH7751 501 14 1 4 Register Configuration SH7751 502 14 2 Register Descriptions 504 14 2 1 DMA Source Address Registers 0 3 SAR0 SAR3 504 14 2 2 DMA Destination Address Registers 0 3 DAR0 DAR3 50...

Page 22: ...nnel Control Registers 0 7 CHCR0 CHCR7 589 14 7 5 DMA Operation Register DMAOR 593 14 8 Operation SH7751R 595 14 8 1 Channel Specification for a Normal DMA Transfer 595 14 8 2 Channel Specification for DDT Mode DMA Transfer 595 14 8 3 Transfer Channel Notification in DDT Mode 596 14 8 4 Clearing Request Queues by DTR Format 597 14 8 5 Interrupt Request Codes 597 14 9 Usage Notes 600 Section 15 Ser...

Page 23: ...ster SCRSR2 675 16 2 2 Receive FIFO Data Register SCFRDR2 675 16 2 3 Transmit Shift Register SCTSR2 676 16 2 4 Transmit FIFO Data Register SCFTDR2 676 16 2 5 Serial Mode Register SCSMR2 677 16 2 6 Serial Control Register SCSCR2 679 16 2 7 Serial Status Register SCFSR2 682 16 2 8 Bit Rate Register SCBRR2 688 16 2 9 FIFO Control Register SCFCR2 689 16 2 10 FIFO Data Count Register SCFDR2 692 16 2 11...

Page 24: ...48 18 1 3 Pin Configuration 755 18 1 4 Register Configuration 758 18 2 Register Descriptions 759 18 2 1 Port Control Register A PCTRA 759 18 2 2 Port Data Register A PDTRA 760 18 2 3 Port Control Register B PCTRB 761 18 2 4 Port Data Register B PDTRB 762 18 2 5 GPIO Interrupt Control Register GPIOIC 763 18 2 6 Serial Port Register SCSPTR1 764 18 2 7 Serial Port Register SCSPTR2 766 Section 19 Inte...

Page 25: ...k Controller UBC 795 20 1 Overview 795 20 1 1 Features 795 20 1 2 Block Diagram 796 20 2 Register Descriptions 798 20 2 1 Access to UBC Registers 798 20 2 2 Break Address Register A BARA 799 20 2 3 Break ASID Register A BASRA 800 20 2 4 Break Address Mask Register A BAMRA 800 20 2 5 Break Bus Cycle Register A BBRA 801 20 2 6 Break Address Register B BARB 803 20 2 7 Break ASID Register B BASRB 803 ...

Page 26: ... Configuration 825 21 1 4 Register Configuration 826 21 2 Register Descriptions 827 21 2 1 Instruction Register SDIR 827 21 2 2 Data Register SDDR 828 21 2 3 Bypass Register SDBPR 828 21 2 4 Interrupt Factor Register SDINT 829 21 2 5 Boundary Scan Register SDBSR 829 21 3 Operation 843 21 3 1 TAP Control 843 21 3 2 H UDI Reset 844 21 3 3 H UDI Interrupt 844 21 3 4 Boundary Scan EXTEST SAMPLE PRELOA...

Page 27: ...CIINTM 895 22 2 22 PCI Address Data Register at Error PCIALR 897 22 2 23 PCI Command Data Register at Error PCICLR 898 22 2 24 PCI Arbiter Interrupt Register PCIAINT 900 22 2 25 PCI Arbiter Interrupt Mask Register PCIAINTM 902 22 2 26 PCI Error Bus Master Data Register PCIBMLR 903 22 2 27 PCI DMA Transfer Arbitration Register PCIDMABT 904 22 2 28 PCI DMA Transfer PCI Address Register 3 0 PCIDPA 3 ...

Page 28: ...ansfers I O Read I O Write 966 22 4 6 Endian Control in Target Transfers Configuration Read Configuration Write 966 22 5 Resetting 968 22 6 Interrupts 969 22 6 1 Interrupts from PCIC to CPU 969 22 6 2 Interrupts from External PCI Devices 970 22 6 3 INTA 971 22 7 Error Detection 971 22 8 PCIC Clock 971 22 9 Power Management 972 22 9 1 Power Management Overview 972 22 9 2 Stopping the Clock 973 22 9...

Page 29: ...me Based on Load Capacitance 1082 Appendix A Address List 1083 Appendix B Package Dimensions 1091 Appendix C Mode Pin Settings 1095 Appendix D Pin Functions 1099 D 1 Pin States 1099 D 2 Handling of Unused Pins 1104 D 3 Note on Pin Processing 1105 Appendix E Synchronous DRAM Address Multiplexing Tables 1107 Appendix F Instruction Prefetching and Its Side Effects 1119 Appendix G Power On and Power O...

Page 30: ...Page xxx of liv R01UH0457EJ0301 Rev 3 01 Sep 24 2013 ...

Page 31: ...ure 3 3 Physical Address Space MMUCR AT 0 71 Figure 3 4 P4 Area 72 Figure 3 5 External Memory Space 74 Figure 3 6 Virtual Address Space MMUCR AT 1 75 Figure 3 7 UTLB Configuration 78 Figure 3 8 Relationship between Page Size and Address Format 79 Figure 3 9 ITLB Configuration 82 Figure 3 10 Flowchart of Memory Access Using UTLB 83 Figure 3 11 Flowchart of Memory Access Using ITLB 84 Figure 3 12 Op...

Page 32: ... Figure 5 2 Instruction Execution and Exception Handling 143 Figure 5 3 Example of General Exception Acceptance Order 145 Section 6 Floating Point Unit Figure 6 1 Format of Single Precision Floating Point Number 173 Figure 6 2 Format of Double Precision Floating Point Number 174 Figure 6 3 Single Precision NaN Bit Pattern 176 Figure 6 4 Floating Point Registers 178 Section 8 Pipelining Figure 8 1 ...

Page 33: ...ure 11 1 Block Diagram of RTC 292 Figure 11 2 Examples of Time Setting Procedures 309 Figure 11 3 Examples of Time Reading Procedures 311 Figure 11 4 Example of Use of Alarm Function 312 Figure 11 5 Example of Crystal Oscillation Circuit Connection 314 Section 12 Timer Unit TMU Figure 12 1 Block Diagram of TMU 316 Figure 12 2 Example of Count Operation Setting Procedure 328 Figure 12 3 TCNT Auto R...

Page 34: ...wn Mode Start EDO Mode RCD 0 AnW 0 422 Figure 13 19 4 DRAM Burst Bus Cycle RAS Down Mode Continuation EDO Mode RCD 0 AnW 0 423 Figure 13 20 CAS Before RAS Refresh Operation 424 Figure 13 21 DRAM CAS Before RAS Refresh Cycle Timing TRAS 0 TRC 1 425 Figure 13 22 DRAM Self Refresh Cycle Timing 426 Figure 13 23 Example of 32 Bit Data Width Synchronous DRAM Connection Area 3 428 Figure 13 24 Basic Timi...

Page 35: ...Write Cycle AnW 0 No External Wait 475 Figure 13 55 MPX Interface Timing 4 Single Write AnW 1 One External Wait Inserted 476 Figure 13 56 MPX Interface Timing 5 Burst Read Cycle AnW 0 No External Wait 477 Figure 13 57 MPX Interface Timing 6 Burst Read Cycle AnW 0 External Wait Control 478 Figure 13 58 MPX Interface Timing 7 Burst Write Cycle AnW 0 No External Wait 479 Figure 13 59 MPX Interface Ti...

Page 36: ...gure 14 14 Dual Address Mode Burst Mode External Bus External Bus DREQ Level Detection DACK Read Cycle 540 Figure 14 15 Dual Address Mode Burst Mode External Bus External Bus DREQ Edge Detection DACK Read Cycle 541 Figure 14 16 Dual Address Mode Cycle Steal Mode On Chip SCI Level Detection External Bus 542 Figure 14 17 Dual Address Mode Cycle Steal Mode External Bus On Chip SCI Level Detection 543...

Page 37: ...Transfer 566 Figure 14 35 Read from Synchronous DRAM Precharge Bank 567 Figure 14 36 Read from Synchronous DRAM Non Precharge Bank Row Miss 567 Figure 14 37 Read from Synchronous DRAM Row Hit 568 Figure 14 38 Write to Synchronous DRAM Precharge Bank 568 Figure 14 39 Write to Synchronous DRAM Non Precharge Bank Row Miss 569 Figure 14 40 Write to Synchronous DRAM Row Hit 569 Figure 14 41 Single Addr...

Page 38: ...mmunication Interface SCI Figure 15 1 Block Diagram of SCI 605 Figure 15 2 SCK Pin 621 Figure 15 3 TxD Pin 622 Figure 15 4 RxD Pin 622 Figure 15 5 Data Format in Asynchronous Communication Example with 8 Bit Data Parity Two Stop Bits 634 Figure 15 6 Relation between Output Clock and Transfer Data Phase Asynchronous Mode 636 Figure 15 7 Sample SCI Initialization Flowchart 637 Figure 15 8 Sample Ser...

Page 39: ...98 Figure 16 6 MD0 SCK2 Pin 699 Figure 16 7 Sample SCIF Initialization Flowchart 705 Figure 16 8 Sample Serial Transmission Flowchart 706 Figure 16 9 Example of Transmit Operation Example with 8 Bit Data Parity One Stop Bit 708 Figure 16 10 Example of Operation Using Modem Control CTS2 708 Figure 16 11 Sample Serial Reception Flowchart 1 709 Figure 16 11 Sample Serial Reception Flowchart 2 710 Fig...

Page 40: ... Interrupt Controller INTC Figure 19 1 Block Diagram of INTC 770 Figure 19 2 Example of IRL Interrupt Connection 773 Figure 19 3 Interrupt Operation Flowchart 788 Section 20 User Break Controller UBC Figure 20 1 Block Diagram of User Break Controller 796 Figure 20 2 User Break Debug Support Function Flowchart 817 Section 21 High performance User Debug Interface H UDI Figure 21 1 Block Diagram of H...

Page 41: ...ata Alignment at Target Configuration Transfer Both Big Endian and Little Endian 967 Figure 22 24 Target Bus Timeout Interrupt Generation Example 1 Example in which the Target Device Asserts STOP at the Sixteenth Clock Cycle after FRAME Was Asserted 978 Figure 22 25 Target Bus Timeout Interrupt Generation Example 2 Example in which the Target Device Takes 8 Clock Cycles to Prepare for the Third Da...

Page 42: ...rtion AnS 1 AnH 1 1026 Figure 23 20 Burst ROM Bus Cycle One Internal Wait One External Wait 1027 Figure 23 21 Synchronous DRAM Auto Precharge Read Bus Cycle Single RCD 1 0 01 CAS Latency 3 TPC 2 0 011 1028 Figure 23 22 Synchronous DRAM Auto Precharge Read Bus Cycle Burst RCD 1 0 01 CAS Latency 3 TPC 2 0 011 1029 Figure 23 23 Synchronous DRAM Normal Read Bus Cycle ACT READ Commands Burst RASD 1 RCD...

Page 43: ...DO Mode RCD 1 0 00 AnW 2 0 000 1048 Figure 23 41 DRAM Burst Bus Cycle RAS Down Mode Continuation EDO Mode RCD 1 0 00 AnW 2 0 000 1049 Figure 23 42 DRAM Burst Bus Cycle Fast Page Mode RCD 1 0 00 AnW 2 0 000 TPC 2 0 001 1050 Figure 23 43 DRAM Burst Bus Cycle Fast Page Mode RCD 1 0 01 AnW 2 0 001 TPC 2 0 001 1051 Figure 23 44 DRAM Burst Bus Cycle Fast Page Mode RCD 1 0 01 AnW 2 0 001 TPC 2 0 001 2 Cy...

Page 44: ...ne External Wait 1065 Figure 23 58 Memory Byte Control SRAM Bus Cycle Basic Read Cycle No Wait Address Setup Hold Time Insertion AnS 0 1 AnH 1 0 01 1066 Figure 23 59 TCLK Input Timing 1072 Figure 23 60 RTC Oscillation Settling Time at Power On 1072 Figure 23 61 SCK Input Clock Timing 1072 Figure 23 62 SCI I O Synchronous Mode Clock Timing 1073 Figure 23 63 I O Port Input Output Timing 1073 Figure ...

Page 45: ...nsions 256 pin BGA HD6417751RBA240HV 1094 Appendix F Instruction Prefetching and Its Side Effects Figure F 1 Instruction Prefetch 1119 Appendix G Power On and Power Off Procedures Figure G 1 Method for Temporarily Selecting Clock Operation Mode 6 1123 Figure G 2 Power On Procedure 1 1124 Figure G 3 Power On Procedure 2 1124 ...

Page 46: ...Page xlvi of liv R01UH0457EJ0301 Rev 3 01 Sep 24 2013 ...

Page 47: ...sters 102 Section 5 Exceptions Table 5 1 Exception Related Registers 137 Table 5 2 Exceptions 140 Table 5 3 Types of Reset 148 Section 6 Floating Point Unit Table 6 1 Floating Point Number Formats and Parameters 174 Table 6 2 Floating Point Ranges 175 Section 7 Instruction Set Table 7 1 Addressing Modes and Effective Addresses 191 Table 7 2 Notation Used in Instruction List 195 Table 7 3 Fixed Poi...

Page 48: ...lock Oscillation Circuits Table 10 1 CPG Pins 272 Table 10 2 CPG Register 272 Table 10 3 1 Clock Operating Modes SH7751 273 Table 10 3 2 Clock Operating Modes SH7751R 273 Table 10 4 FRQCR Settings and Internal Clock Frequencies 274 Table 10 5 WDT Registers 281 Section 11 Realtime Clock RTC Table 11 1 RTC Pins 293 Table 11 2 RTC Registers 293 Table 11 3 Crystal Oscillation Circuit Constants Recomme...

Page 49: ...Registers 503 Table 14 4 Selecting External Request Mode with RS Bits 521 Table 14 5 Selecting On Chip Peripheral Module Request Mode with RS Bits 522 Table 14 6 Supported DMA Transfers 526 Table 14 7 Relationship between DMA Transfer Type Request Mode and Bus Mode 532 Table 14 8 External Request Transfer Sources and Destinations in Normal DMA Mode 533 Table 14 9 External Request Transfer Sources ...

Page 50: ...R2 Settings for SCIF Clock Source Selection 702 Table 16 5 Serial Transfer Formats 703 Table 16 6 SCIF Interrupt Sources 714 Section 17 Smart Card Interface Table 17 1 Smart Card Interface Pins 721 Table 17 2 Smart Card Interface Registers 721 Table 17 3 Smart Card Interface Register Settings 729 Table 17 4 Values of n and Corresponding CKS1 and CKS0 Settings 732 Table 17 5 Examples of Bit Rate B ...

Page 51: ...853 Table 22 5 List of CLASS23 to 16 Base Class Codes CLASS23 to 16 864 Table 22 6 Memory Space Base Address Register BASE0 870 Table 22 7 Memory Space Base Address Register BASE1 872 Table 22 8 Operating Modes 928 Table 22 9 PCI Command Support 929 Table 22 10 Access Size 960 Table 22 11 DMA Transfer Access Size and Endian Conversion Mode 962 Table 22 12 Target Transfer Access Size and Endian Con...

Page 52: ... Table 23 18 Clock and Control Signal Timing HD6417751BP167 V HD6417751F167 V 1006 Table 23 19 Control Signal Timing 1012 Table 23 20 Control Signal Timing 1013 Table 23 21 Bus Timing 1 1016 Table 23 22 Bus Timing 2 1018 Table 23 23 Peripheral Module Signal Timing 1 1067 Table 23 24 Peripheral Module Signal Timing 2 1070 Table 23 25 PCIC Signal Timing in PCIREQ PCIGNT Non Port Mode 1 1076 Table 23...

Page 53: ...mon 1099 Table D 2 Pin States in Reset Power Down State and Bus Released State PCI Enable 1101 Table D 3 Pin States in Reset Power Down State and Bus Released State PCI Disable 1103 Table D 4 Handling of Pins When PCI Is Not Used 1105 Appendix H Product Lineup Table H 1 SH7751 SH7751R Product Lineup 1125 Appendix I Version Registers Table I 1 Register Configuration 1127 ...

Page 54: ...Page liv of liv R01UH0457EJ0301 Rev 3 01 Sep 24 2013 ...

Page 55: ... is upwardly compatible with the SH 1 SH 2 and SH 3 microcomputers The SH7751 SH7751R Group have an instruction cache an operand cache that can be switched between copy back and write through modes a 4 entry full associative instruction TLB table look aside buffer and MMU memory management unit with 64 entry full associative shared TLB The SH7751 SH7751R Group also feature a bus state controller B...

Page 56: ...perH architecture 32 bit internal data bus General register file Sixteen 32 bit general registers and eight 32 bit shadow registers Seven 32 bit control registers Four 32 bit system registers RISC type instruction set upward compatible with SuperH Series Fixed 16 bit instruction length for improved code efficiency Load store architecture Delayed branch instructions Conditional execution C based in...

Page 57: ... or double precision 64 bits 8 2 banks 32 bit CPU FPU floating point communication register FPUL Supports FMAC multiply and accumulate instruction Supports FDIV divide and FSQRT square root instructions Supports FLDI0 FLDI1 load constant 0 1 instructions Instruction execution times Latency FMAC FADD FSUB FMUL 3 cycles single precision 8 cycles double precision Pitch FMAC FADD FSUB FMUL 1 cycle sin...

Page 58: ...1 8 times main clock Power down modes Sleep mode Deep sleep mode Pin sleep mode Standby mode Hardware standby mode Module standby function Single channel watchdog timer Memory management unit MMU 4 Gbyte address space 256 address space identifiers 8 bit ASIDs Single virtual mode and multiple virtual memory mode Supports multiple page sizes 1 Kbyte 4 Kbytes 64 Kbytes 1 Mbyte 4 entry fully associati...

Page 59: ...essed directly by address mapping usable as on chip memory Store queue 32 bytes 2 entries Cache memory SH7751R Instruction cache IC 16 Kbytes 2 way set associative 256 entries way 32 byte block length Cache double mode 16 Kbyte cache Index mode SH7751 compatible mode 8 Kbytes direct mapping Operand cache OC 32 Kbytes 2 way set associative 512 entries way 32 byte block length Cache double mode 32 K...

Page 60: ...nction Bus state controller BSC Supports external memory access 32 16 8 bit external data bus External memory space divided into seven areas each of up to 64 Mbytes with the following parameters settable for each area Bus size 8 16 or 32 bits Number of wait cycles hardware wait function also supported Direct connection of DRAM synchronous DRAM and burst ROM possible by setting space type Supports ...

Page 61: ... external bus 32 bit Timer unit TMU 5 channel auto reload 32 bit timer Input capture function on one channel Selection from 7 counter input clocks in 3 of 5 channels and from 5 counter input clocks on remaining 2 of 5 channels Realtime clock RTC On chip clock and calendar functions Built in 32 kHz crystal oscillation circuit with maximum 1 256 second resolution cycle interrupts Serial communicatio...

Page 62: ... equipped with 64 byte FIFO Selection of built in clock or external PCI dedicated clock Interrupt requests can be sent to CPU Product lineup Abbreviation Voltage Operating Frequency Model No Package SH7751 1 8 V 167 MHz HD6417751BP167 256 pin BGA HD6417751F167 256 pin QFP SH7751R 1 5 V 240 MHz HD6417751RBP240 256 pin BGA HD6417751RBA240H HD6417751RF240 256 pin QFP HD6417751RBG240 292 pin BGA 200 M...

Page 63: ...address 32 bit PCI address data 32 bit SH bus data Peripheral data bus UBC 32 bit data store 32 bit data load CPU I cache O cache ITLB UTLB Cache and TLB controller FPU Legend BSC Bus state controller CPG Clock pulse generator DMAC Direct memory access controller FPU Floating point unit INTC Interrupt controller ITLB Instruction TLB translation lookaside buffer UTLB Unified TLB translation lookasi...

Page 64: ... D31 D30 D29 D28 D27 D26 D25 D24 D23 D22 D21 D20 D19 D18 D17 D16 CAS3 DQM3 CAS2 DQM2 A17 A16 A15 A14 A13 A12 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 TMS TCK TDI CS0 CS1 CS4 CS5 CS6 BS WE0 REG WE1 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 CAS0 DQ...

Page 65: ...29 A19 A12 A17 AD22 AD24 AD27 AD25 AD21 AD18 AD14 PAR AD10 AD4 AD1 AD29 AD28 AD30 AD31 AD20 AD23 AD17 AD19 AD26 A20 A21 A22 A24 AD16 AD12 AD13 AD9 AD6 AD7 AD2 AD5 AD3 AD0 XTAL2 EXTAL2 AD11 AD15 AD8 IDSEL C BE3 C BE1 C BE0 TRDY C BE2 INTA PCIRST PCICLK SERR A25 WE2 ICIORD PCIGNT4 PCIGNT1 REQOUT PCIREQ1 GNTIN PCIGNT2 DEVSEL PERR IRL0 IRL2 IRL1 IRL3 PCILOCK PCIFRAME PCISTOP IRDY PCIREQ4 PCIREQ3 MD10 ...

Page 66: ...E0 D4 D6 D7 D9 D10 D12 C BE1 CAS0 DQM0 CKIO RD CASS FRAME CS3 A3 A6 A9 A14 CAS3 DQM3 D17 D23 D18 D21 D19 D16 D22 D27 A18 A24 A13 CAS2 DQM2 A12 D20 AD19 A0 AD23 AD24 AD22 AD17 CS2 RAS AD13 PAR AD10 AD3 AD0 AD27 AD28 AD30 AD31 AD21 C BE3 AD16 AD18 AD26 A23 A22 PCIFRAME AD12 AD8 D3 AD7 AD5 D0 AD1 AD4 AD2 IRL0 XTAL2 EXTAL2 AD11 AD14 AD9 AD25 AD15 DEVSEL C BE2 PCIRST INTA PCIGNT3 IDSEL VSS SERR WE2 ICI...

Page 67: ...TDI I Data in H UDI 6 CS0 O Chip select 0 CS0 CS0 7 CS1 O Chip select 1 CS1 CS1 8 CS4 O Chip select 4 CS4 CS4 9 CS5 O Chip select 5 CS5 CE1A CS5 10 CS6 O Chip select 6 CS6 CE1B CS6 11 BS O Bus start BS BS BS BS BS 12 WE0 REG O D7 D0 select signal WE0 REG 13 WE1 O D15 D8 select signal WE1 WE1 14 D0 I O Data A0 15 VDDQ Power IO VDD 16 VSSQ Power IO GND 17 VDD Power Internal VDD 18 VSS Power Internal...

Page 68: ...O D7 D0 select signal CAS0 DQM0 37 CAS1 DQM1 O D15 D8 select signal CAS1 DQM1 38 RD WR O Read write RD WR RD WR RD WR RD WR RD WR 39 CKIO O Clock output CKIO CKIO CKIO CKIO 40 Reserved Do not connect 41 VDDQ Power IO VDD 42 VSSQ Power IO GND 43 Reserved Do not connect 44 RD CASS FRAME O Read CAS FRAME OE CAS OE FRAME 45 CKE O Clock output enable CKE 46 RAS O RAS RAS RAS 47 VDD Power Internal VDD 4...

Page 69: ... 64 A11 O Address 65 A12 O Address 66 A13 O Address 67 VDDQ Power IO VDD 68 VSSQ Power IO GND 69 A14 O Address 70 A15 O Address 71 A16 O Address 72 A17 O Address 73 CAS2 DQM2 O D23 D16 select signal CAS2 DQM2 74 CAS3 DQM3 O D31 D24 select signal CAS3 DQM3 75 D16 I O Data A16 76 D17 I O Data A17 77 D18 I O Data A18 78 D19 I O Data A19 79 VDDQ Power IO VDD 80 VSSQ Power IO GND 81 VDD Power Internal ...

Page 70: ...D30 I O Data ACCSIZE1 96 D31 I O Data ACCSIZE2 97 VDD Power Internal VDD 98 VSS Power Internal GND 99 A18 O Address 100 A19 O Address 101 A20 O Address 102 A21 O Address 103 A22 O Address 104 A23 O Address 105 VDDQ Power IO VDD 106 VSSQ Power IO GND 107 A24 O Address 108 A25 O Address 109 WE2 ICIORD O D23 D16 select signal WE2 ICIORD 110 WE3 ICIOWR O D31 D24 select signal WE3 ICIOWR 111 VDD Power ...

Page 71: ... IO GND 121 PCIREQ2 MD9 I Bus request host function mode MD9 122 IDSEL I Configuration device select 123 INTA O Interrupt async 124 PCIRST O Reset output 125 PCICLK I PCI input clock 126 PCIGNT1 REQOUT O Bus grant host function bus request 127 PCIREQ1 GNTIN I Bus request host function bus grant 128 SERR I O System error 129 AD31 I O PCI address data port Port Port Port Port Port 130 AD30 I O PCI a...

Page 72: ...e enable 140 AD23 I O PCI address data port Port Port Port Port Port 141 AD22 I O PCI address data port Port Port Port Port Port 142 AD21 I O PCI address data port Port Port Port Port Port 143 VDDQ Power IO VDD 144 VSSQ Power IO GND 145 VDD Power Internal VDD 146 VSS Power Internal GND 147 AD20 I O PCI address data port Port Port Port Port Port 148 AD19 I O PCI address data port Port Port Port Por...

Page 73: ...4 I O PCI address data port Port Port Port Port Port 166 AD13 I O PCI address data port Port Port Port Port Port 167 AD12 I O PCI address data port Port Port Port Port Port 168 AD11 I O PCI address data port Port Port Port Port Port 169 VDDQ Power IO VDD 170 VSSQ Power IO GND 171 AD10 I O PCI address data port Port Port Port Port Port 172 AD9 I O PCI address data port Port Port Port Port Port 173 ...

Page 74: ...ort Port Port Port Port 183 VDDQ Power I O VDD 184 VSSQ Power I O GND 185 AD1 I O PCI address data port Port Port Port Port Port 186 AD0 I O PCI address data port Port Port Port Port Port 187 IRL0 I Interrupt 0 188 IRL1 I Interrupt 1 189 IRL2 I Interrupt 2 190 IRL3 I Interrupt 3 191 VSSQ Power I O GND 192 VDDQ Power I O VDD 193 XTAL2 O RTC crystal resonator pin 194 EXTAL2 I RTC crystal resonator p...

Page 75: ...r IO GND 209 VDD Power Internal VDD 210 VSS Power Internal GND 211 MD2 RXD2 I Mode SCIF data input MD2 RXD2 RXD2 RXD2 RXD2 RXD2 212 RXD I SCI data input 213 TCLK I O RTC TMU clock 214 MD8 RTS2 I O Mode SCIF data control RTS MD8 RTS2 RTS2 RTS2 RTS2 RTS2 215 SCK I O SCIF clock 216 MD1 TXD2 I O Mode SCIF data output MD1 TXD2 TXD2 TXD2 TXD2 TXD2 217 MD0 SCK2 I O Mode SCIF clock MD0 SCK2 SCK2 SCK2 SCK2...

Page 76: ...A I O Mode PCMCIA CE MD3 CE2A 231 MD4 CE2B I O Mode PCMCIA CE MD4 CE2B 232 MD5 I Mode MD5 233 VDDQ Power IO VDD 234 VSSQ Power IO GND 235 DACK0 O DMAC0 bus acknowledge 236 DACK1 O DMAC1 bus acknowledge 237 DRAK0 O DMAC0 request acknowledge 238 DRAK1 O DMAC1 request acknowledge 239 VDD Power Internal VDD 240 VSS Power Internal GND 241 STATUS0 O Status 242 STATUS1 O Status 243 DREQ0 I Request from D...

Page 77: ... resonator Legend I Input O Output I O Input output Power Power supply Notes Supply power to all power pins However on the SH7751 in hardware standby mode supply power to RTC at the minimum Power must be supplied to VDD PLL1 2 and VSS PLL1 2 regardless of whether or not the on chip PLL circuits are used Power must be supplied to VDD CPG and VSS CPG regardless of whether or not the on chip crystal ...

Page 78: ...select 0 CS0 CS0 7 C2 CS1 O Chip select 1 CS1 CS1 8 C1 CS4 O Chip select 4 CS4 CS4 9 D3 CS5 O Chip select 5 CS5 CE1A CS5 10 D2 CS6 O Chip select 6 CS6 CE1B CS6 11 D1 BS O Bus start BS BS BS BS BS 12 E4 WE0 REG O D7 D0 select signal WE0 REG 13 E3 WE1 O D15 D8 select signal WE1 WE1 14 E2 D0 I O Data A0 15 G2 VDDQ Power IO VDD 16 L4 VSSQ Power IO GND 17 G4 VDD Power Internal VDD 18 F4 VSS Power Inter...

Page 79: ...ect signal CAS0 DQM0 37 M4 CAS1 DQM1 O D15 D8 select signal CAS1 DQM1 38 M3 RD WR O Read write RD WR RD WR RD WR RD WR RD WR 39 M1 CKIO O Clock output CKIO CKIO CKIO CKIO 40 M2 NC Do not connect 41 P3 VDDQ Power IO VDD 42 L1 VSSQ Power IO GND 43 N3 NC Do not connect 44 P1 RD CASS FRAME O Read CAS FRAME OE CAS OE FRAME 45 N2 CKE O Clock output enable CKE 46 N1 RAS O RAS RAS RAS 47 P4 VDD Power Inte...

Page 80: ...ess 65 Y1 A12 O Address 66 Y2 A13 O Address 67 V7 VDDQ Power IO VDD 68 V3 VSSQ Power IO GND 69 W3 A14 O Address 70 Y3 A15 O Address 71 V4 A16 O Address 72 W4 A17 O Address 73 Y4 CAS2 DQM2 O D23 D16 select signal CAS2 DQM2 74 U5 CAS3 DQM3 O D31 D24 select signal CAS3 DQM3 75 V5 D16 I O Data A16 76 W5 D17 I O Data A17 77 Y5 D18 I O Data A18 78 V6 D19 I O Data A19 79 W7 VDDQ Power IO VDD 80 W2 VSSQ P...

Page 81: ...1 96 Y10 D31 I O Data ACCSIZE2 97 U10 VDD Power Internal VDD 98 U11 VSS Power Internal GND 99 V11 A18 O Address 100 Y11 A19 O Address 101 U12 A20 O Address 102 V12 A21 O Address 103 W12 A22 O Address 104 Y12 A23 O Address 105 V14 VDDQ Power IO VDD 106 W11 VSSQ Power IO GND 107 U13 A24 O Address 108 V13 A25 O Address 109 W13 WE2 ICIORD O D23 D16 select signal WE2 ICIORD 110 Y13 WE3 ICIOWR O D31 D24...

Page 82: ... IDSEL I Configuration device select 123 V17 INTA O Interrupt async 124 W17 PCIRST O Reset output 125 Y17 PCICLK I PCI input clock 126 W18 PCIGNT1 REQOUT O Bus grant host function bus request 127 Y18 PCIREQ1 GNTIN I Bus request host function bus grant 128 Y19 SERR I O System error 129 Y20 AD31 I O PCI address data port Port Port Port Port Port 130 W20 AD30 I O PCI address data port Port Port Port ...

Page 83: ...ort Port Port Port Port Port 142 T19 AD21 I O PCI address data port Port Port Port Port Port 143 N19 VDDQ Power IO VDD 144 W19 VSSQ Power IO GND 145 P17 VDD Power Internal VDD 146 R17 VSS Power Internal GND 147 R20 AD20 I O PCI address data port Port Port Port Port Port 148 P20 AD19 I O PCI address data port Port Port Port Port Port 149 P19 AD18 I O PCI address data port Port Port Port Port Port 1...

Page 84: ...AD13 I O PCI address data port Port Port Port Port Port 167 J17 AD12 I O PCI address data port Port Port Port Port Port 168 H20 AD11 I O PCI address data port Port Port Port Port Port 169 G18 VDDQ Power IO VDD 170 K17 VSSQ Power IO GND 171 H19 AD10 I O PCI address data port Port Port Port Port Port 172 G20 AD9 I O PCI address data port Port Port Port Port Port 173 H18 AD8 I O PCI address data port...

Page 85: ...5 D19 AD1 I O PCI address data port Port Port Port Port Port 186 D18 AD0 I O PCI address data port Port Port Port Port Port 187 E17 IRL0 I Interrupt 0 188 C20 IRL1 I Interrupt 1 189 C19 IRL2 I Interrupt 2 190 B20 IRL3 I Interrupt 3 191 B18 NC Do not connect 2 192 D17 VDDQ Power I O VDD 193 A20 XTAL2 O RTC crystal resonator pin 194 A19 EXTAL2 I RTC crystal resonator pin 195 A18 VDD RTC Power RTC VD...

Page 86: ...ND 211 D13 MD2 RXD2 I Mode SCIF data input MD2 RXD2 RXD2 RXD2 RXD2 RXD2 212 C13 RXD I SCI data input 213 B13 TCLK I O RTC TMU clock 214 A13 MD8 RTS2 I O Mode SCIF data control RTS MD8 RTS2 RTS2 RTS2 RTS2 RTS2 215 D12 SCK I O SCIF clock 216 B11 MD1 TXD2 I O Mode SCIF data output MD1 TXD2 TXD2 TXD2 TXD2 TXD2 217 C12 MD0 SCK2 I O Mode SCIF clock MD0 SCK2 SCK2 SCK2 SCK2 SCK2 218 A12 MD7 CTS2 I O Mode ...

Page 87: ... I Mode MD5 233 C11 VDDQ Power IO VDD 234 C17 VSSQ Power IO GND 235 B8 DACK0 O DMAC0 bus acknowledge 236 A8 DACK1 O DMAC1 bus acknowledge 237 B7 DRAK0 O DMAC0 request acknowledge 238 A7 DRAK1 O DMAC1 request acknowledge 239 D7 VDD Power Internal VDD 240 D6 VSS Power Internal GND 241 C6 STATUS0 O Status 242 B6 STATUS1 O Status 243 A6 DREQ0 I Request from DMAC0 244 C5 DREQ1 I Request from DMAC1 245 ...

Page 88: ...I O Input output Power Power supply Notes Supply power to all power pins However on the SH7751 in hardware standby mode supply power to RTC at the minimum Power must be supplied to VDD PLL1 2 and VSS PLL1 2 regardless of whether or not the on chip PLL circuits are used Power must be supplied to VDD CPG and VSS CPG regardless of whether or not the on chip crystal oscillation circuit is used Power m...

Page 89: ...hip select 0 CS0 CS0 7 D1 CS1 O Chip select 1 CS1 CS1 8 D2 CS4 O Chip select 4 CS4 CS4 9 D3 CS5 O Chip select 5 CS5 CE1A CS5 10 E1 CS6 O Chip select 6 CS6 CE1B CS6 11 E2 BS O Bus start BS BS BS BS BS 12 E3 WE0 REG O D7 D0 select signal WE0 REG 13 F1 WE1 O D15 D8 select signal WE1 WE1 14 F2 D0 I O Data A0 15 G3 VDDQ Power IO VDD 16 D4 VSS Power GND 17 G4 VDD Power Internal VDD 18 H4 VSS Power GND 1...

Page 90: ...S0 DQM0 37 M2 CAS1 DQM1 O D15 D8 select signal CAS1 DQM1 38 M3 RD WR O Read write RD WR RD WR RD WR RD WR RD WR 39 N1 CKIO O Clock output CKIO CKIO CKIO CKIO CKIO 40 K4 VDD Power Internal VDD 41 R4 VDDQ Power IO VDD 42 L4 VSS Power IO GND 43 M4 VDDQ Power I O VDD 44 N2 RD CASS FRAME O Read CAS FRAME OE CAS OE FRAME 45 N3 CKE O Clock output enable CKE 46 P1 RAS O RAS RAS RAS 47 P4 VDD Power Interna...

Page 91: ...Y1 A13 O Address 67 V7 VDDQ Power IO VDD 68 U4 VSS Power GND 69 Y2 A14 O Address 70 Y3 A15 O Address 71 W3 A16 O Address 72 Y4 A17 O Address 73 W4 CAS2 DQM2 O D23 D16 select signal CAS2 DQM2 74 V4 CAS3 DQM3 O D31 D24 select signal CAS3 DQM3 75 Y5 D16 I O Data A16 76 W5 D17 I O Data A17 77 V5 D18 I O Data A18 78 Y6 D19 I O Data A19 79 U6 VDDQ Power IO VDD 80 U5 VSS Power GND 81 U7 VDD Power Interna...

Page 92: ... VDD 98 U11 VSS Power GND 99 Y11 A18 O Address 100 W11 A19 O Address 101 V11 A20 O Address 102 Y12 A21 O Address 103 W12 A22 O Address 104 V12 A23 O Address 105 U15 VDDQ Power IO VDD 106 U17 VSS Power GND 107 Y13 A24 O Address 108 W13 A25 O Address 109 V13 WE2 ICIORD O D23 D16 select signal WE2 ICIORD 110 Y14 WE3 ICIOWR O D31 D24 select signal WE3 ICIOWR 111 U14 VDD Power Internal VDD 112 U13 VSS ...

Page 93: ...LK I PCI input clock 126 W18 PCIGNT1 REQOUT O Bus grant host function bus request 127 V18 PCIREQ1 GNTIN I Bus grant host function bus request 128 Y19 SERR I O System error 129 Y20 AD31 I O PCI address data port Port Port Port Port Port 130 W20 AD30 I O PCI address data port Port Port Port Port Port 131 R17 VDDQ Power IO VDD 132 T17 VSS Power GND 133 W19 AD29 I O PCI address data port Port Port Por...

Page 94: ...VDDQ Power I O VDD 145 P17 VDD Power Internal VDD 146 N17 VSS Power GND 147 R19 AD20 I O PCI address data port Port Port Port Port Port 148 R18 AD19 I O PCI address data port Port Port Port Port Port 149 P20 AD18 I O PCI address data port Port Port Port Port Port 150 P19 AD17 I O PCI address data port Port Port Port Port Port 151 N20 AD16 I O PCI address data port Port Port Port Port Port 152 N18 ...

Page 95: ...t Port Port Port 169 F17 VDDQ Power IO VDD 170 K17 VSS Power GND 171 H19 AD10 I O PCI address data port Port Port Port Port Port 172 H18 AD9 I O PCI address data port Port Port Port Port Port 173 G20 AD8 I O PCI address data port Port Port Port Port Port 174 G19 C BE0 I O Command byte enable 175 G17 VDD Power Internal VDD 176 H17 VSS Power GND 177 F20 AD7 I O PCI address data port Port Port Port P...

Page 96: ...0 IRL3 I Interrupt 3 191 B18 VSS RTC Power RTC GND 192 E17 VSS Power GND 193 A20 XTAL2 O RTC crystal resonator pin 194 A19 EXTAL2 I RTC crystal resonator pin 195 A18 VDD RTC Power RTC VDD 196 B19 VDDQ Power IO VDD 197 C18 CA I Hardware standby 198 A17 RESET I Reset RESET 199 B17 TRST I Reset H UDI 200 C17 MRESET I Manual reset 201 A16 NMI I Nonmaskable interrupt 202 B16 BACK BSREQ O Bus acknowledg...

Page 97: ... I O SCIF clock 216 A12 MD1 TXD2 I O Mode SCIF data output MD1 TXD2 TXD2 TXD2 TXD2 TXD2 217 B12 MD0 SCK2 I O Mode SCIF clock MD0 SCK2 SCK2 SCK2 SCK2 SCK2 218 C12 MD7 CTS2 I O Mode SCIF data control RTS MD7 CTS2 CTS2 CTS2 CTS2 CTS2 219 A11 AUDSYNC AUD Sync 220 B11 AUDCK AUD clock 221 D15 VDDQ Power IO VDD 222 D10 VSS Power GND 223 A10 AUDATA0 AUD data 224 B10 AUDATA1 AUD data 225 D11 VDD Power Inte...

Page 98: ...wer I O VDD 241 A6 STATUS0 O Status 242 B6 STATUS1 O Status 243 C6 DREQ0 I Request from DMAC0 244 C5 DREQ1 I Request from DMAC1 245 B5 ASEBRK BRKACK I O Pin break acknowledge H UDI 246 C4 TDO O Data out H UDI 247 C7 VDDQ Power IO VDD 248 D13 VSS Power GND 249 A5 VDD PLL2 Power PLL2 VDD 250 B4 VSS PLL2 Power PLL2 GND 251 A4 VDD PLL1 Power PLL1 VDD 252 C3 VSS PLL1 Power PLL1 GND 253 B3 VDD CPG Power...

Page 99: ...er GND 268 M13 VSS Power GND 269 L13 VSS Power GND 270 K13 VSS Power GND 271 J13 VSS Power GND 272 H13 VSS Power GND 273 H12 VSS Power GND 274 H11 VSS Power GND 275 H10 VSS Power GND 276 H9 VSS Power GND 277 J9 VSS Power GND 278 K9 VSS Power GND 279 L9 VSS Power GND 280 M9 VSS Power GND 281 M10 VSS Power GND 282 M11 VSS Power GND 283 M12 VSS Power GND 284 L12 VSS Power GND 285 K12 VSS Power GND 28...

Page 100: ...1 2 and VSS PLL1 2 regardless of whether or not the on chip PLL circuits are used Power must be supplied to VDD CPG and VSS CPG regardless of whether or not the on chip crystal oscillation circuit is used Power must be supplied to VDD RTC and VSS RTC regardless of whether or not the on chip RTC is used For the handling of the PCI bus pins in PCI disabled mode see table D 4 in appendix D I O attrib...

Page 101: ...ion 2 Programming Model 2 1 Data Formats The data formats handled by the SH 4 are shown in figure 2 1 Byte 8 bits Word 16 bits Longword 32 bits Single precision floating point 32 bits Double precision floating point 64 bits 0 7 0 15 0 31 0 31 30 22 fraction exp s 0 63 62 51 exp s fraction Figure 2 1 Data Formats ...

Page 102: ... bank 0 general registers R0_BANK0 to R7_BANK0 are accessed by the LDC STC instructions When the RB bit is 0 that is when bank 0 is selected the 16 registers comprising bank 0 general registers R0_BANK0 to R7_BANK0 and non banked general registers R8 to R15 can be accessed as general registers R0 to R15 In this case the eight registers comprising bank 1 general registers R0_BANK1 to R7_BANK1 are a...

Page 103: ...12 14 register pairs or register matrix XMTRX Register values after a reset are shown in table 2 1 Table 2 1 Initial Register Values Type Registers Initial Value General registers R0_BANK0 R7_BANK0 R0_BANK1 R7_BANK1 R8 R15 Undefined SR MD bit 1 RB bit 1 BL bit 1 FD bit 0 IMASK 1111 H F reserved bits 0 others undefined GBR SSR SPC SGR DBR Undefined Control registers VBR H 00000000 MACH MACL PR FPUL...

Page 104: ...1 3 R3_BANK1 3 R4_BANK1 3 R5_BANK1 3 R6_BANK1 3 R7_BANK1 3 R8 R9 R10 R11 R12 R13 R14 R15 R0_BANK0 1 4 R1_BANK0 4 R2_BANK0 4 R3_BANK0 4 R4_BANK0 4 R5_BANK0 4 R6_BANK0 4 R7_BANK0 4 c Register configuration in privileged mode RB 0 GBR MACH MACL VBR PR SR SSR PC SPC SGR DBR SGR DBR Notes 1 The R0 register is used as the index register in indexed register indirect addressing mode and indexed GBR indire...

Page 105: ... However only 16 of these can be accessed as general registers R0 R15 in one processor mode The SH 4 has two processor modes user mode and privileged mode in which R0 R7 are assigned as shown below R0_BANK0 R7_BANK0 In user mode SR MD 0 R0 R7 are always assigned to R0_BANK0 R7_BANK0 In privileged mode SR MD 1 R0 R7 are assigned to R0_BANK0 R7_BANK0 only when SR RB 0 R0_BANK1 R7_BANK1 In user mode ...

Page 106: ...2_BANK1 R3_BANK1 R4_BANK1 R5_BANK1 R6_BANK1 R7_BANK1 R0 R1 R2 R3 R4 R5 R6 R7 R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R8 R9 R10 R11 R12 R13 R14 R15 R8 R9 R10 R11 R12 R13 R14 R15 SR MD 1 SR RB 1 Figure 2 3 General Registers Programming Note As the user s R0 R7 are assigned to R0_BANK0 R7_BANK0 and after an exception or interrupt R0 R7 are assigned to R0_BANK1 R7_BANK1 it is not necessa...

Page 107: ...FPR7_BANK1 FPR8_BANK1 FPR9_BANK1 FPR10_BANK1 FPR11_BANK1 FPR12_BANK1 FPR13_BANK1 FPR14_BANK1 FPR15_BANK1 Single precision floating point registers FRi 16 registers When FPSCR FR 0 FR0 FR15 are assigned to FPR0_BANK0 FPR15_BANK0 When FPSCR FR 1 FR0 FR15 are assigned to FPR0_BANK1 FPR15_BANK1 Double precision floating point registers or single precision floating point register pairs DRi 8 registers ...

Page 108: ...13_BANK0 FPR14_BANK0 FPR15_BANK0 XF0 XF1 XF2 XF3 XF4 XF5 XF6 XF7 XF8 XF9 XF10 XF11 XF12 XF13 XF14 XF15 FR0 FR1 FR2 FR3 FR4 FR5 FR6 FR7 FR8 FR9 FR10 FR11 FR12 FR13 FR14 FR15 DR0 DR2 DR4 DR6 DR8 DR10 DR12 DR14 FV0 FV4 FV8 FV12 XD0 XMTRX XD2 XD4 XD6 XD8 XD10 XD12 XD14 FPR0_BANK1 FPR1_BANK1 FPR2_BANK1 FPR3_BANK1 FPR4_BANK1 FPR5_BANK1 FPR6_BANK1 FPR7_BANK1 FPR8_BANK1 FPR9_BANK1 FPR10_BANK1 FPR11_BANK1 ...

Page 109: ...ANK0 are accessed as general registers R0 R7 R0_BANK1 R7_BANK1 can be accessed using LDC STC instructions RB 1 R0_BANK1 R7_BANK1 are accessed as general registers R0 R7 R0_BANK0 R7_BANK0 can be accessed using LDC STC instructions BL Exception interrupt block bit set to 1 by a reset exception or interrupt BL 1 Interrupt requests are masked If a general exception other than a user break occurs while...

Page 110: ... section 5 Exceptions Saved general register 15 SGR 32 bits privilege protection initial value undefined The contents of R15 are saved to SGR in the event of an exception or interrupt Debug base register DBR 32 bits privilege protection initial value undefined When the user break debug function is enabled BRCR UBDE 1 DBR is referenced as the user break handler branch destination address instead of...

Page 111: ...egister pair 64 bits PR Precision mode PR 0 Floating point instructions are executed as single precision operations PR 1 Floating point instructions are executed as double precision operations the result of instructions for which double precision is not supported is undefined Do not set SZ and PR to 1 simultaneously this setting is reserved SZ PR 11 Reserved FPU operation instruction is undefined ...

Page 112: ...used for double precision floating point data load or store operations In little endian mode two 32 bit data size moves must be executed with SZ 0 to load or store a double precision floating point data 2 3 Memory Mapped Registers Appendix A shows the control registers mapped to memory The control registers are double mapped to the following two memory areas All registers have two addresses H 1C00...

Page 113: ...t word or 32 bit longword form A memory operand less than 32 bits in length is sign extended before being loaded into a register A word operand must be accessed starting from a word boundary even address of a 2 byte unit address 2n and a longword operand starting from a longword boundary even address of a 4 byte unit address 4n An address error will result if this rule is not observed A byte opera...

Page 114: ...pin goes low The CPU enters the manual reset state if the RESET pin is high and the MRESET pin is low For more information on resets see section 5 Exceptions In the power on reset state the internal state of the CPU and the on chip peripheral module registers are initialized In the manual reset state the internal state of the CPU and registers of on chip peripheral modules other than the bus state...

Page 115: ...re three modes in the power down state sleep mode deep sleep mode and standby mode For details see section 9 Power Down Modes Bus Released State In this state the CPU has released the bus to a device that requested it Transitions between the states are shown in figure 2 6 RESET 0 RESET 1 MRESET 1 RESET 1 Power on reset state Manual reset state Program execution state Bus released state Exception h...

Page 116: ...e and privileged mode The processor mode is determined by the processor mode bit MD in the status register SR User mode is selected when the MD bit is cleared to 0 and privileged mode when the MD bit is set to 1 When the reset state or exception state is entered the MD bit is set to 1 There are certain registers and bits which can only be accessed in privileged mode ...

Page 117: ... physical memory it becomes necessary to divide the process into smaller parts and map the parts requiring execution onto physical memory on an ad hoc basis 1 Having this mapping onto physical memory executed consciously by the process itself imposes a heavy burden on the process The virtual memory system was devised as a means of handling all physical memory mapping to reduce this burden 2 With a...

Page 118: ...ient For this reason a buffer for address translation the translation lookaside buffer TLB is provided in hardware and frequently used address translation information is placed here The TLB can be described as a cache for address translation information However unlike a cache if address translation fails that is if an exception occurs switching of the address translation information is normally pe...

Page 119: ... Rev 3 01 Page 65 of 1128 Sep 24 2013 2 Process 1 Process 1 Physical memory Process 1 Process 2 Process 3 Virtual memory Process 1 Process 1 Process 2 Process 3 MMU MMU 4 3 1 Physical memory Physical memory Physical memory Physical memory Virtual memory Figure 3 1 Role of the MMU ...

Page 120: ...sistance register PTEA R W Undefined H FF00 0034 H 1F00 0034 32 Translation table base register TTB R W Undefined H FF00 0008 H 1F00 0008 32 TLB exception address register TEA R W Undefined H FF00 000C H 1F00 000C 32 MMU control register MMUCR R W H 0000 0000 H FF00 0010 H 1F00 0010 32 Notes 1 The initial value is the value after a power on reset or manual reset 2 P4 address is the address when us...

Page 121: ...PN PPN ASID 1 PTEH 31 30 29 28 10 9 8 7 6 5 4 3 2 1 0 V SZ PR SZ C D SH WT 2 PTEL 31 4 3 2 0 TC SA 3 PTEA 31 0 0 TTB 4 TTB 31 Virtual address at which MMU exception or address error occurred 5 TEA 31 26 24 23 18 17 16 15 10 9 8 7 6 5 4 3 2 1 0 LRUI URC SQMD SV TI AT 6 MMUCR Note indicates a reserved bit the write value must be 0 and a read will return 0 URB 25 Figure 3 2 MMU Related Registers ...

Page 122: ...ion The contents of this register are not changed unless a software directive is issued 3 Page table entry assistance register PTEA Longword access to PTEA can be performed from H FF00 0034 in the P4 area and H 1F00 0034 in area 7 PTEA is used to store assistance bits for PCMCIA access to the UTLB by means of the LDTLB instruction When performing PCMCIA access with the MMU off access is always per...

Page 123: ...by software The LRUI bits and URC bits may also be updated by hardware LRUI LRU bits that indicate the ITLB entry for which replacement is to be performed The LRU least recently used method is used to decide the ITLB entry to be replaced in the event of an ITLB miss The entry to be purged from the ITLB can be confirmed using the LRUI bits LRUI is updated by means of the algorithm shown below A das...

Page 124: ...n to URC by software which results in the condition URC URB incrementing is first performed in excess of URB until URC H 3F URC is not incremented by an LDTLB instruction SQMD Store queue mode bit Specifies the right of access to the store queues 0 User privileged access possible 1 Privileged access possible address error exception in case of user access SV Bit that switches between single virtual...

Page 125: ...a to the P4 area can be accessed In user mode a 2 Gbyte space in the U0 area can be accessed Accessing the P1 to P4 areas except the store queue area in user mode will cause an address error Area 0 Area 1 Area 2 Area 3 Area 4 Area 5 Area 6 Area 7 External memory space Address error Address error Store queue area User mode Privileged mode P1 area Cacheable P0 area Cacheable P2 area Non cacheable P3...

Page 126: ...pace is a reserved area a reserved area also appears in these areas P2 Area The P2 area cannot be accessed using the cache In the P2 area zeroizing the upper 3 bits of an address gives the corresponding external memory space address However since area 7 in the external memory space is a reserved area a reserved area also appears in this area P4 Area The P4 area is mapped onto SH 4 on chip I O chan...

Page 127: ...ction 3 7 1 ITLB Address Array The area from H F300 0000 to H F3FF FFFF is used for direct access to instruction TLB data arrays 1 and 2 For details see sections 3 7 2 ITLB Data Array 1 and 3 7 3 ITLB Data Array 2 The area from H F400 0000 to H F4FF FFFF is used for direct access to the operand cache address array For details see section 4 5 3 OC Address Array The area from H F500 0000 to H F5FF F...

Page 128: ...ce is divided into eight areas as shown in figure 3 5 Areas 0 to 6 relate to memory such as SRAM synchronous DRAM DRAM and PCMCIA Area 7 is a reserved area For details see section 13 Bus State Controller BSC H 0000 0000 H 0400 0000 H 0800 0000 H 0C00 0000 H 1000 0000 H 1400 0000 H 1800 0000 H 1C00 0000 H 1FFF FFFF Area 0 Area 1 Area 2 Area 3 Area 4 Area 5 Area 6 Area 7 reserved area Figure 3 5 Ext...

Page 129: ...t are equivalent to the P4 area control register area in the physical address space Virtual address space is illustrated in figure 3 6 Area 0 Area 1 Area 2 Area 3 Area 4 Area 5 Area 6 Area 7 External memory space 256 256 U0 area Cacheable Address translation possible Address error Address error Store queue area P0 area Cacheable Address translation possible User mode Privileged mode P1 area Cachea...

Page 130: ...be accessed from the U0 area in user mode In this case the C bit for the corresponding page must be cleared to 0 P1 P2 P4 Areas Address translation using the TLB cannot be performed for the P1 P2 or P4 area except for the store queue area Accesses to these areas are the same as for physical address space The store queue area can be mapped onto any external memory space by the MMU However operation...

Page 131: ...ddress space on an exclusive basis and the physical address corresponding to a particular virtual address is uniquely determined In the multiple virtual memory system a number of processes run while sharing the virtual address space and a particular virtual address may be translated into different physical addresses depending on the process The only difference between the single virtual memory and...

Page 132: ... its use for the following two purposes 1 To translate a virtual address to a physical address in a data access 2 As a table of address translation information to be recorded in the instruction TLB in the event of an ITLB miss Information in the address translation table located in external memory is cached into the UTLB The address translation table contains virtual page numbers and address space...

Page 133: ... Physical address PPN Offset PPN Offset PPN Offset PPN Offset Figure 3 8 Relationship between Page Size and Address Format VPN Virtual page number For 1 Kbyte page upper 22 bits of virtual address For 4 Kbyte page upper 20 bits of virtual address For 64 Kbyte page upper 16 bits of virtual address For 1 Mbyte page upper 12 bits of virtual address ASID Address space identifier Indicates the process ...

Page 134: ... a manual reset PPN Physical page number Upper 22 bits of the physical address With a 1 Kbyte page PPN bits 28 10 are valid With a 4 Kbyte page PPN bits 28 12 are valid With a 64 Kbyte page PPN bits 28 16 are valid With a 1 Mbyte page PPN bits 28 20 are valid The synonym problem must be taken into account when setting the PPN see section 3 5 5 Avoiding Synonym Problems PR Protection key data 2 bit...

Page 135: ...mode 0 Copy back mode 1 Write through mode When performing PCMCIA space mapping in the cache enabled state either set this bit to 1 or clear the C bit to 0 SA Space attribute bits Valid only when the page is mapped onto PCMCIA connected to area 5 or 6 000 Undefined 001 Variable size I O space base size according to IOIS16 signal 010 8 bit I O space 011 16 bit I O space 100 8 bit common memory spac...

Page 136: ... type entries The address translation information is almost the same as that in the UTLB but with the following differences 1 D and WT bits are not supported 2 There is only one PR bit corresponding to the upper of the PR bits in the UTLB PPN 28 10 PPN 28 10 PPN 28 10 PPN 28 10 SZ 1 0 SZ 1 0 SZ 1 0 SZ 1 0 SH SH SH SH C C C C PR PR PR PR ASID 7 0 ASID 7 0 ASID 7 0 ASID 7 0 VPN 31 10 VPN 31 10 VPN 3...

Page 137: ... exception Data TLB protection violation exception Data TLB miss exception Initial page write exception Data TLB protection violation exception Cache access in copy back mode Data access to virtual address VA On chip I O access R W R W VA is in P4 area VA is in P2 area VA is in P1 area VA is in P0 U0 or P3 area Yes No 1 0 Yes Yes No No Yes Yes Yes No No 1 Privileged 1 0 0 PR 0 User D R W W W W R R...

Page 138: ... TLB multiple hit exception Instruction TLB miss exception Instruction access to virtual address VA VA is in P4 area VA is in P2 area VA is in P1 area VA is in P0 U0 or P3 area Yes No 1 0 Yes Yes No No Yes Yes No Non cacheable C 1 and CCR ICE 1 No PR Instruction TLB protection violation exception Match Record in ITLB Access prohibited 0 1 No Yes Yes No Hardware ITLB miss handling 0 User 1 Privileg...

Page 139: ...R LRUI 3 5 2 MMU Software Management Software processing for the MMU consists of the following 1 Setting of MMU related registers Some registers are also partially updated by hardware automatically 2 Recording deletion and reading of TLB entries There are two methods of recording UTLB entries by using the LDTLB instruction or by writing directly to the memory mapped UTLB ITLB entries can only be r...

Page 140: ...0 VPN 31 10 V Entry 63 D WT 31 29 28 9 8 7 6 5 4 3 2 1 0 V SZ PR SZ C D SHWT PTEL Write UTLB 31 10 9 8 7 0 ASID PTEH 31 26 25 24 23 18 17 16 15 10 9 8 7 3 2 1 0 LRUI URB URC SV SQMD TI AT MMUCR VPN 10 PPN 31 4 3 2 0 SA TC PTEA Entry specification Figure 3 12 Operation of LDTLB Instruction 3 5 4 Hardware ITLB Miss Handling In an instruction access the SH 4 searches the ITLB If it cannot find the ne...

Page 141: ... 10 of the virtual address Consequently the following restrictions apply to the recording of address translation information in UTLB entries 1 When address translation information whereby a number of 1 Kbyte page UTLB entries are translated into the same physical address is recorded in the UTLB ensure that the VPN 13 10 values are the same 2 When address translation information whereby a number of...

Page 142: ...sult When an instruction TLB multiple hit exception occurs a reset is executed and cache coherency is not guaranteed Hardware Processing In the event of an instruction TLB multiple hit exception hardware carries out the following processing 1 Sets the virtual address at which the exception occurred in TEA 2 Sets exception code H 140 in EXPEVT 3 Branches to the reset handling routine H A000 0000 So...

Page 143: ...responsible for searching the external memory page table and assigning the necessary page table entry Software should carry out the following processing in order to find and assign the necessary page table entry 1 Write to PTEL the values of the PPN PR SZ C D SH V and WT bits in the page table entry recorded in the external memory address translation table If necessary the values of the SA and TC ...

Page 144: ...ained by adding offset H 0000 0100 to the contents of VBR and starts the instruction TLB protection violation exception handling routine Software Processing Instruction TLB Protection Violation Exception Handling Routine Resolve the instruction TLB protection violation execute the exception handling return instruction RTE terminate the exception handling routine and return control to the normal fl...

Page 145: ...ed in SPC If the exception occurred at a delay slot sets the PC value indicating the address of the delayed branch instruction in SPC 5 Sets the SR contents at the time of the exception in SSR and sets the R15 contents at the time in SGR 6 Sets the MD bit in SR to 1 and switches to privileged mode 7 Sets the BL bit in SR to 1 and masks subsequent exception requests 8 Sets the RB bit in SR to 1 9 B...

Page 146: ... which the exception occurred in PTEH 2 Sets the virtual address at which the exception occurred in TEA 3 Sets exception code H 0A0 in the case of a read or H 0C0 in the case of a write in EXPEVT OCBP OCBWB read OCBI MOVCA L write 4 Sets the PC value indicating the address of the instruction at which the exception occurred in SPC If the exception occurred at a delay slot sets the PC value indicati...

Page 147: ...R contents at the time of the exception in SSR The R15 contents at this time are saved in SGR 6 Sets the MD bit in SR to 1 and switches to privileged mode 7 Sets the BL bit in SR to 1 and masks subsequent exception requests 8 Sets the RB bit in SR to 1 9 Branches to the address obtained by adding offset H 0000 0100 to the contents of VBR and starts the initial page write exception handling routine...

Page 148: ... the address array side and the data array side Only longword access is possible Instruction fetches cannot be performed in these areas For reserved bits a write value of 0 should be specified their read value is undefined 3 7 1 ITLB Address Array The ITLB address array is allocated to addresses H F200 0000 to H F2FF FFFF in the P4 area An address array access requires a 32 bit address field speci...

Page 149: ...pecification when writing Information for selecting the entry to be accessed is specified in the address field and PPN V SZ PR C and SH to be written to the data array are specified in the data field In the address field bits 31 23 have the value H F30 indicating ITLB data array 1 and the entry is selected by bits 9 8 In the data field PPN is indicated by bits 28 10 V by bit 8 SZ by bits 7 and 4 P...

Page 150: ...32 bit address field specification when reading or writing and a 32 bit data field specification when writing Information for selecting the entry to be accessed is specified in the address field and SA and TC to be written to data array 2 are specified in the data field In the address field bits 31 23 have the value H F38 indicating ITLB data array 2 and the entry is selected by bits 9 8 In the da...

Page 151: ... field In the address field bits 31 24 have the value H F6 indicating the UTLB address array and the entry is selected by bits 13 8 The address array bit 7 association bit A bit specifies whether or not address comparison is performed when writing to the UTLB address array In the data field VPN is indicated by bits 31 10 D by bit 9 V by bit 8 and ASID by bits 7 0 The following three kinds of opera...

Page 152: ...tch in both the UTLB and ITLB the UTLB information is also written to the ITLB Address field Data field Legend VPN V E D Virtual page number Validity bit Entry Dirty bit ASID A Address space identifier Association bit Reserved bits 0 write value undefined read value 31 0 V D 10 9 8 7 30 2928 A 8 7 ASID VPN 31 23 2 1 0 1 1 1 1 0 1 1 0 E 24 14 13 Figure 3 16 Memory Mapped UTLB Address Array 3 7 5 UT...

Page 153: ... 5 PR C PPN 31 23 0 1 1 1 1 0 1 1 1 0 E 24 8 7 14 13 D SZ SH WT Figure 3 17 Memory Mapped UTLB Data Array 1 3 7 6 UTLB Data Array 2 UTLB data array 2 is allocated to addresses H F780 0000 to H F7FF FFFF in the P4 area A data array access requires a 32 bit address field specification when reading or writing and a 32 bit data field specification when writing Information for selecting the entry to be...

Page 154: ...sponding to the entry set in the address field Address field 31 23 0 1 1 1 1 0 1 1 1 1 E Data field 31 4 0 TC 24 8 13 7 3 2 14 SA Legend TC E Timing control bit Entry SA Space attribute bits Reserved bits 0 write value undefined read value Figure 3 18 Memory Mapped UTLB Data Array 2 3 8 Usage Notes 1 Address Space Identifier ASID in Single Virtual Memory Mode Refer to the note in 3 3 7 Address Spa...

Page 155: ...s can also be used as on chip RAM When the EMODE bit in the CCR register is cleared to 0 in the SH7751R both the IC and OC are set to SH7751 compatible mode When the EMODE bit in the CCR register is set to 1 the cache characteristics are as shown in table 4 2 After a power on reset or manual reset the initial value of the EMODE bit is 0 This LSI supports two 32 byte store queues SQs for performing...

Page 156: ... write Write back Prefetch instruction PREF instruction Access right MMU off according to MMUCR SQMD MMU on according to individual page PR 4 1 2 Register Configuration Table 4 4 shows the cache control registers Table 4 4 Cache Control Registers Name Abbreviation R W Initial Value 1 P4 Address 2 Area 7 Address 2 Access Size Cache control register CCR R W H 0000 0000 H FF00 001C H 1F00 001C 32 Que...

Page 157: ...ntrol Registers CCR 1 Cache Control Register CCR CCR contains the following bits EMODE Cache double mode SH7751R only Reserved bit in SH7751 IIX IC index enable ICI IC invalidation ICE IC enable OIX OC index enable ORA OC RAM enable OCI OC invalidation CB Copy back enable WT Write through enable OCE OC enable CCR can be accessed by longword size access from H FF00001C in the P4 area and H 1F00001C...

Page 158: ...try selection ICI IC invalidation bit When 1 is written to this bit the V bits of all IC entries are cleared to 0 This bit always returns 0 when read ICE IC enable bit Indicates whether or not the IC is to be used When address translation is performed the IC cannot be used unless the C bit in the page management information is also 1 0 IC not used 1 IC used OIX OC index enable bit 2 0 Effective ad...

Page 159: ...e used unless the C bit in the page management information is also 1 0 OC not used 1 OC used 2 Queue Address Control Register 0 QACR0 QACR0 can be accessed by longword size access from H FF000038 in the P4 area and H 1F000038 in area 7 QACR0 specifies the area onto which store queue 0 SQ0 is mapped when the MMU is off 3 Queue Address Control Register 1 QACR1 QACR1 can be accessed by longword size ...

Page 160: ...rand cache in the SH7751R 31 26 25 5 4 3 2 1 LW0 32 bits LW1 32 bits LW2 32 bits LW3 32 bits LW4 32 bits LW5 32 bits LW6 32 bits LW7 32 bits MMU RAM area determination ORA OIX 13 12 11 5 511 19 bits 1 bit 1 bit Tag U V Address array Data array Entry selection Longword LW selection Effective address 3 9 22 19 0 Write data Read data Hit signal Compare 13 1211 10 9 0 Figure 4 2 Configuration of Opera...

Page 161: ...ntry selection Longword LW selection Effective address 3 9 22 19 0 Write data Read data Hit signal Compare way 0 Compare way 1 13 12 10 0 Figure 4 3 Configuration of Operand Cache SH7751R Tag Stores the upper 19 bits of the 29 bit external address of the data line to be cached The tag is not initialized by a power on or manual reset V bit validity bit Indicates that valid data is stored in the cac...

Page 162: ...tered among the two ways There is one LRU bit in each entry and it is controlled by hardware The LRU Last Recently Used algorithm that selects the most recently accessed way is used for way selection The LRU bit is initialized to 0 by a power on reset but is not initialized by a manual reset The LRU bit cannot be read from or written to by software 4 3 2 Read Operation When the OC is enabled CCR O...

Page 163: ... the cache the read data is returned to the CPU While the remaining one cache line of data is being read the CPU can execute the next processing When reading of one line of data is completed the tag corresponding to the effective address is recorded in the cache 1 is written to the V bit and 0 to the U bit The data in the write back buffer is then written back to external memory 4 3 3 Write Operat...

Page 164: ...ed the tag corresponding to the effective address is recorded in the cache and 1 is written to the V bit and U bit 3d Cache miss write through A write of the specified access size is performed to the external memory corresponding to the effective address In this case a write to cache is not performed 3e Cache miss copy back with write back The tag and data field of the cache line indexed by effect...

Page 165: ...g for completion of the write to external memory Physical address bits 28 0 LW1 LW0 Figure 4 5 Configuration of Write Through Buffer 4 3 6 RAM Mode Setting CCR ORA to 1 enables 8 Kbytes of the operand cache to be used as RAM The operand cache entries used as RAM are the 8 Kbytes of entries 128 to 255 and 384 to 511 In SH7751 compatible mode in the SH7751R the 8 Kbytes of operand cache entries 256 ...

Page 166: ...FFF 4 KB Corresponds to RAM area 1 H 7DFF F000 to H 7DFF FFFF 4 KB Corresponds to RAM area 1 H 7E00 0000 to H 7E00 0FFF 4 KB Corresponds to RAM area 2 H 7E00 1000 to H 7E00 1FFF 4 KB Corresponds to RAM area 2 H 7FFF F000 to H 7FFF FFFF 4 KB Corresponds to RAM area 2 As the distinction between RAM areas 1 and 2 is indicated by address bit 25 the area from H 7DFF F000 to H 7E00 0FFF should be used t...

Page 167: ...ssured by software In this LSI the following four new instructions are supported for cache operations Details of these instructions are given in the Programming Manual Invalidate instruction OCBI Rn Cache invalidation no write back Purge instruction OCBP Rn Cache invalidation with write back Write back instruction OCBWB Rn Cache write back Allocate instruction MOVCA L R0 Rn Cache allocation 4 3 9 ...

Page 168: ...iggered by a debugging tool swapping an instruction a break occurring when a TRAPA instruction or undefined instruction code H FFFD is swapped for an instruction Condition 4 A store instruction MOV FMOV AND B OR B XOR B MOVCA L STC L or STS L that accesses internal RAM H 7C000000 to H 7FFFFFFF exists within four words after the instruction associated with the exception or interrupt described in co...

Page 169: ...s within four instructions after an instruction causing an interrupt to be accepted MOV L H 7C002000 R1 R1 is an address mapped to internal RAM MOV L H 12345678 R0 An interrupt is accepted after this instruction NOP 1st word NOP 2nd word NOP 3rd word MOV L R0 R1 Store instruction accessing internal RAM Example 3 A debugging tool generates a break to swap an instruction Original Instruction String ...

Page 170: ...ak with no instruction swapping will not cause the problem Workaround 2 Ensure that there are no instructions that generate an interrupt or exception within four instructions after an instruction that accesses internal RAM For example the internal RAM area can be used as a data table that is accessed only by load instructions with writes to the internal RAM area only being performed when the table...

Page 171: ...nfiguration of the instruction cache in the SH7751R LW0 32 bits LW1 32 bits LW2 32 bits LW3 32 bits LW4 32 bits LW5 32 bits LW6 32 bits LW7 32 bits 255 19 bits 1 bit Tag V Address array Longword LW selection Data array 0 Read data Hit signal Compare 31 26 25 5 4 3 2 1 MMU IIX 12 11 5 Entry selection Effective address 8 3 22 19 13 1211 10 9 0 Figure 4 6 Configuration of Instruction Cache SH7751 ...

Page 172: ...ngword LW selection Effective address 3 8 22 19 0 Read data Hit signal Compare way 0 Compare way 1 13 12 11 10 0 Figure 4 7 Configuration of Instruction Cache SH7751R Tag Stores the upper 19 bits of the 29 bit external address of the data line to be cached The tag is not initialized by a power on or manual reset V bit validity bit Indicates that valid data is stored in the cache line When this bit...

Page 173: ...cacheable area the instruction cache operates as follows 1 The tag and V bit are read from the cache line indexed by effective address bits 12 5 2 The tag is compared with bits 28 10 of the address resulting from effective address translation by the MMU If the tag matches and the V bit is 1 3a If the tag matches and the V bit is 0 3b If the tag does not match and the V bit is 0 3b If the tag does ...

Page 174: ...s can be used on both the IC address array and data array and the OC address array and data array and the access size is always longword Instruction fetches cannot be performed in these areas For reserved bits a write value of 0 should be specified and read values are undefined 4 5 1 IC Address Array The IC address array is allocated to addresses H F000 0000 to H F0FF FFFF in the P4 area An addres...

Page 175: ...the tag specified in the data field If the MMU is enabled at this time comparison is performed after the virtual address specified by data field bits 31 10 has been translated to a physical address using the ITLB If the addresses match and the V bit is 1 the V bit specified in the data field is written into the IC entry In other cases no operation is performed This operation is used to invalidate ...

Page 176: ...cification in the entry As only longword access is used 0 should be specified for address field bits 1 0 The data field is used for the longword data specification The following two kinds of operation can be used on the IC data array 1 IC data array read Longword data is read into the data field from the data specified by the longword specification bits in the address field in the IC entry corresp...

Page 177: ...ad The tag U bit and V bit are read into the data field from the OC entry corresponding to the entry set in the address field In a read associative operation is not performed regardless of whether the association bit specified in the address field is 1 or 0 2 OC address array write non associative The tag U bit and V bit specified in the data field are written to the OC entry corresponding to the ...

Page 178: ...o be written is specified in the data field In the address field bits 31 24 have the value H F5 indicating the OC data array and the entry is specified by bits 13 5 CCR OIX and CCR ORA have no effect on this entry specification Address field bits 4 2 are used for the longword data specification in the entry As only longword access is used 0 should be specified for address field bits 1 0 The data f...

Page 179: ...a in physical memory space Only data accesses can be used on both the IC address array and data array and the OC address array and data array and the access size is always longword Instruction fetches cannot be performed in these areas For reserved bits a write value of 0 should be specified and read values are undefined Note that the memory mapped cache configuration in SH7751 compatible mode of ...

Page 180: ... to 0 3 IC address array write associative When a write is performed with the A bit in the address field set to 1 each way s tag stored in the entry specified in the address field is compared with the tag specified in the data field The way number set in bit 13 is ignored If the MMU is enabled at this time comparison is performed after the virtual address specified by data field bits 31 10 has bee...

Page 181: ... data specification in the entry As only longword access is used 0 should be specified for address field bits 1 0 The data field is used for the longword data specification The following two kinds of operation can be used on the IC data array 1 IC data array read Longword data is read into the data field from the data specified by the longword specification bits in the address field in the IC entr...

Page 182: ...he case of a write in which association is performed The following three kinds of operation can be used on the OC address array 1 OC address array read The tag U bit and V bit are read into the data field from the OC entry corresponding to the way and entry set in the address field In a read associative operation is not performed regardless of whether the association bit specified in the address f...

Page 183: ...ea A data array access requires a 32 bit address field specification when reading or writing and a 32 bit data field specification The way and entry to be accessed are specified in the address field and the longword data to be written is specified in the data field In the address field bits 31 24 have the value H F5 indicating the OC data array the way is specified by bit 14 and the entry is speci...

Page 184: ... array side Address field 31 23 5 4 2 1 0 1 1 1 1 0 1 0 1 Entry L Data field 31 0 Longword data 24 13 14 Legend L Longword specification bits Reserved bits 0 write value undefined read value 15 Way Figure 4 15 Memory Mapped OC Data Array 4 6 5 Summary of Memory Mapped OC Addresses The memory mapped OC addresses in cache double mode in the SH7751R are summarized below using data area access as an e...

Page 185: ...ode determined by the CCR CB and CCR WT bits and if address translation is performed the WT bit in the page management information When the memory allocation cache function is used to write to the OC address array and an entry is generated when both the V and U bits are set to 1 4 7 1 SQ Configuration There are two 32 byte store queues SQ0 and SQ1 as shown in figure 4 16 These two store queues can...

Page 186: ...fer destination external address in PPN The ASID V SZ SH PR and D bits have the same meaning as for normal address translation but the C and WT bits have no meaning with regard to this page Since burst transfer is prohibited for PCMCIA areas the SA and TC bits also have no meaning When a prefetch instruction is issued for the SQ area address translation is performed and external address bits 28 10...

Page 187: ...U is on Operation is in accordance with the address translation information recorded in the UTLB and MMUCR SQMD Write type exception judgment is performed for writes to the SQs and read type for transfer from the SQs to external memory PREF instruction and a TLB miss exception protection violation exception or initial page write exception is generated However if SQ access is enabled in privileged ...

Page 188: ... the exception handling routine the execution order of the PREF instruction and SQ store instruction is reversed so that erroneous data may be transferred to external memory 2 When SQ data is transferred to external memory in an exception handling routine If store queue contents are transferred to external memory within an exception handling routine erroneous data may be transferred to external me...

Page 189: ...tion 5 Both A and B below must be satisfied in order to prevent this bug A When a store queue store instruction is executed after a PREF instruction for transfer from that same store queue SQ0 SQ1 to external memory 1 and 2 below must be satisfied 1 Insert three NOP instructions 1 between the two instructions 2 Do not place a PREF instruction for transfer from a store queue to external memory in t...

Page 190: ...Section 4 Caches SH7751 Group SH7751R Group Page 136 of 1128 R01UH0457EJ0301 Rev 3 01 Sep 24 2013 ...

Page 191: ... given the generic name of exception handling SH 4 exception handling is of three kinds for resets general exceptions and interrupts 5 1 2 Register Configuration The registers used in exception handling are shown in table 5 1 Table 5 1 Exception Related Registers Name Abbrevia tion R W Initial Value P4 Address 2 Area 7 Address 2 Access Size TRAPA exception register TRA R W Undefined H FF00 0020 H ...

Page 192: ... P4 address H FF00 0028 and contains a 14 bit exception code The exception code set in INTEVT is that for an interrupt request The exception code is set automatically by hardware when an exception is accepted INTEVT can also be modified by software 3 The TRAPA exception register TRA resides at P4 address H FF00 0020 and contains 8 bit immediate data imm for the TRAPA instruction TRA is set automat...

Page 193: ... the meaning of the individual SR bits 1 The PC SR and R15 contents are saved in SPC SSR and SGR 2 The block bit BL in SR is set to 1 3 The mode bit MD in SR is set to 1 4 The register bank bit RB in SR is set to 1 5 In a reset the FPU disable bit FD in SR is cleared to 0 6 The exception code is written to bits 11 0 of the exception event register EXPEVT or to bits 13 0 of the interrupt event regi...

Page 194: ...or 2 1 VBR H 100 H 0E0 Instruction TLB miss exception 2 2 VBR H 400 H 040 Instruction TLB protection violation exception 2 3 VBR H 100 H 0A0 General illegal instruction exception 2 4 VBR H 100 H 180 Slot illegal instruction exception 2 4 VBR H 100 H 1A0 General FPU disable exception 2 4 VBR H 100 H 800 Slot FPU disable exception 2 4 VBR H 100 H 820 Data address error read 2 5 VBR H 100 H 0E0 Data ...

Page 195: ... 200 1 H 220 2 H 240 3 H 260 4 H 280 5 H 2A0 6 H 2C0 7 H 2E0 8 H 300 9 H 320 A H 340 B H 360 C H 380 D H 3A0 External interrupts IRL3 IRL0 E 4 2 VBR H 600 H 3C0 TMU0 TUNI0 H 400 TMU1 TUNI1 H 420 TUNI2 H 440 TMU2 TICPI2 H 460 TMU3 TUNI3 H B00 TMU4 TUNI4 H B80 ATI H 480 PRI H 4A0 RTC CUI H 4C0 SCI ERI H 4E0 RXI H 500 TXI H 520 TEI H 540 WDT ITI H 560 RCMI H 580 Interrupt Completion type Peripheral m...

Page 196: ...rupt Completion type Peripheral module interrupt module source PCIDMA3 4 2 VBR H 600 H A20 Priority Priority is first assigned by priority level then by priority order within each level the lowest number represents the highest priority Exception transition destination Control passes to H A000 0000 in a reset and to VBR offset in other cases Exception code Stored in EXPEVT for a reset or general ex...

Page 197: ...egisters may be set automatically by hardware depending on the exception For details see section 5 6 Description of Exceptions Also see section 5 6 4 Priority Order with Multiple Exceptions for exception handling during execution of a delayed branch instruction and a delay slot instruction and in the case of instructions in which two data accesses are performed Execute next instruction Is highest ...

Page 198: ...on general FPU disable exception slot FPU disable exception and unconditional trap exception are detected in the process of instruction decoding and do not occur simultaneously in the instruction pipeline These exceptions therefore all have the same priority General exceptions are detected in the order of instruction execution However exception handling is performed in the order of instruction flo...

Page 199: ...B miss instruction n Program order 1 Instruction n 2 General illegal instruction exception IF ID EX MA WB IF ID EX MA WB TLB miss instruction access 2 3 4 Legend IF Instruction fetch ID Instruction decode EX Instruction execution MA Memory access WB Write back Instruction n 3 TLB miss instruction n Re execution of instruction n General illegal instruction exception instruction n 1 Re execution of ...

Page 200: ... to 0 by software If a nonmaskable interrupt NMI occurs it can be held pending or accepted according to the setting made by software Thus normally SPC and SSR are saved and then the BL bit in SR is cleared to 0 to enable multiple exception state acceptance 5 5 4 Return from Exception Handling The RTE instruction is used to return from exception handling When the RTE instruction is executed the SPC...

Page 201: ...e MD RB and BL bits are set to 1 the FD bit is cleared to 0 and the interrupt mask bits IMASK are set to B 1111 CPU and on chip peripheral module initialization is performed For details see the register descriptions in the relevant sections For some CPU functions the TRST pin and RESET pin must be driven low It is therefore essential to execute a power on reset and drive the TRST pin low when powe...

Page 202: ...nch is made to PC H A000 0000 In the initialization processing the VBR register is set to H 0000 0000 and in SR the MD RB and BL bits are set to 1 the FD bit is cleared to 0 and the interrupt mask bits IMASK are set to B 1111 CPU and on chip peripheral module initialization is performed For details see the register descriptions in the relevant sections Manual_reset EXPEVT H 00000020 VBR H 00000000...

Page 203: ...d a branch is made to PC H A000 0000 In the initialization processing the VBR register is set to H 0000 0000 and in SR the MD RB and BL bits are set to 1 the FD bit is cleared to 0 and the interrupt mask bits IMASK are set to B 1111 CPU and on chip peripheral module initialization is performed For details see the register descriptions in the relevant sections H UDI_reset EXPEVT H 00000000 VBR H 00...

Page 204: ...H 140 is set in EXPEVT initialization of VBR and SR is performed and a branch is made to PC H A000 0000 In the initialization processing the VBR register is set to H 0000 0000 and in SR the MD RB and BL bits are set to 1 the FD bit is cleared to 0 and the interrupt mask bits IMASK are set to B 1111 CPU and on chip peripheral module initialization is performed in the same way as in a manual reset F...

Page 205: ...0 is set in EXPEVT initialization of VBR and SR is performed and a branch is made to PC H A000 0000 In the initialization processing the VBR register is set to H 0000 0000 and in SR the MD RB and BL bits are set to 1 the FD bit is cleared to 0 and the interrupt mask bits IMASK are set to B 1111 CPU and on chip peripheral module initialization is performed in the same way as in a manual reset For d...

Page 206: ...EH indicates the ASID when this exception occurred The PC and SR contents for the instruction at which this exception occurred are saved in SPC and SSR The R15 contents at this time are saved in SGR Exception code H 040 for a read access or H 060 for a write access is set in EXPEVT The BL MD and RB bits are set to 1 in SR and a branch is made to PC VBR H 0400 To speed up TLB miss processing the of...

Page 207: ...set in PTEH 31 10 ASID in PTEH indicates the ASID when this exception occurred The PC and SR contents for the instruction at which this exception occurred are saved in SPC and SSR The R15 contents at this time are saved in SGR Exception code H 040 is set in EXPEVT The BL MD and RB bits are set to 1 in SR and a branch is made to PC VBR H 0400 To speed up TLB miss processing the offset is separate f...

Page 208: ...esponding virtual page number 22 bits is set in PTEH 31 10 ASID in PTEH indicates the ASID when this exception occurred The PC and SR contents for the instruction at which this exception occurred are saved in SPC and SSR The R15 contents at this time are saved in SGR Exception code H 080 is set in EXPEVT The BL MD and RB bits are set to 1 in SR and a branch is made to PC VBR H 0100 Initial_write_e...

Page 209: ...on operations The virtual address 32 bits at which this exception occurred is set in TEA and the corresponding virtual page number 22 bits is set in PTEH 31 10 ASID in PTEH indicates the ASID when this exception occurred The PC and SR contents for the instruction at which this exception occurred are saved in SPC and SSR The R15 contents at this time are saved in SGR Exception code H 0A0 for a read...

Page 210: ...ress 32 bits at which this exception occurred is set in TEA and the corresponding virtual page number 22 bits is set in PTEH 31 10 ASID in PTEH indicates the ASID when this exception occurred The PC and SR contents for the instruction at which this exception occurred are saved in SPC and SSR The R15 contents at this time are saved in SGR Exception code H 0A0 is set in EXPEVT The BL MD and RB bits ...

Page 211: ...which this exception occurred is set in TEA and the corresponding virtual page number 22 bits is set in PTEH 31 10 ASID in PTEH indicates the ASID when this exception occurred The PC and SR contents for the instruction at which this exception occurred are saved in SPC and SSR The R15 contents at this time are saved in SGR Exception code H 0E0 for a read access or H 100 for a write access is set in...

Page 212: ...e corresponding virtual page number 22 bits is set in PTEH 31 10 ASID in PTEH indicates the ASID when this exception occurred The PC and SR contents for the instruction at which this exception occurred are saved in the SPC and SSR The R15 contents at this time are saved in SGR Exception code H 0E0 is set in EXPEVT The BL MD and RB bits are set to 1 in SR and a branch is made to PC VBR H 0100 For d...

Page 213: ...for the instruction following the TRAPA instruction are saved in SPC The value of SR and R15 when the TRAPA instruction is executed are saved in SSR and SGR The 8 bit immediate value in the TRAPA instruction is multiplied by 4 and the result is set in TRA 9 0 Exception code H 160 is set in EXPEVT The BL MD and RB bits are set to 1 in SR and a branch is made to PC VBR H 0100 TRAPA_exception SPC PC ...

Page 214: ...ions LDC STC RTE LDTLB SLEEP but excluding LDC STC instructions that access GBR Transition address VBR H 0000 0100 Transition operations The PC and SR contents for the instruction at which this exception occurred are saved in SPC and SSR The R15 contents at this time are saved in SGR Exception code H 180 is set in EXPEVT The BL MD and RB bits are set to 1 in SR and a branch is made to PC VBR H 010...

Page 215: ...in a delay slot Privileged instructions LDC STC RTE LDTLB SLEEP but excluding LDC STC instructions that access GBR Decoding of a PC relative MOV instruction or MOVA instruction in a delay slot Transition address VBR H 0000 0100 Transition operations The PC contents for the preceding delayed branch instruction are saved in SPC The SR and R15 contents when this exception occurred are saved in SSR an...

Page 216: ...on occurred are saved in SPC and SSR The R15 contents at this time are saved in SGR Exception code H 800 is set in EXPEVT The BL MD and RB bits are set to 1 in SR and a branch is made to PC VBR H 0100 Note FPU instructions are instructions in which the first 4 bits of the instruction code are H F but excluding undefined instruction H FFFD and the LDS STS LDS L and STS L instructions corresponding ...

Page 217: ...BR H 0000 0100 Transition operations The PC contents for the preceding delayed branch instruction are saved in SPC The SR and R15 contents when this exception occurred are saved in SSR and SGR Exception code H 820 is set in EXPEVT The BL MD and RB bits are set to 1 in SR and a branch is made to PC VBR H 0100 Slot_fpu_disable_exception SPC PC 2 SSR SR SGR R15 EXPEVT H 00000820 SR MD 1 SR RB 1 SR BL...

Page 218: ...are set in SPC In the case of a pre execution break the PC contents for the instruction at which the breakpoint is set are set in SPC The SR and R15 contents when the break occurred are saved in SSR and SGR Exception code H 1E0 is set in EXPEVT The BL MD and RB bits are set to 1 in SR and a branch is made to PC VBR H 0100 It is also possible to branch to PC DBR For details of PC etc when a data br...

Page 219: ...ss VBR H 0000 0100 Transition operations The PC and SR contents for the instruction at which this exception occurred are saved in SPC and SSR The R15 contents at this time are saved in SGR Exception code H 120 is set in EXPEVT The BL MD and RB bits are set to 1 in SR and a branch is made to PC VBR H 0100 FPU_exception SPC PC SSR SR SGR R15 EXPEVT H 00000120 SR MD 1 SR RB 1 SR BL 1 PC VBR H 0000010...

Page 220: ...ts at this time are saved in SGR Exception code H 1C0 is set in INTEVT The BL MD and RB bits are set to 1 in SR and a branch is made to PC VBR H 0600 When the BL bit in SR is 0 this interrupt is not masked by the interrupt mask bits in SR and is accepted at the highest priority level When the BL bit in SR is 1 a software setting can specify whether this interrupt is to be masked or accepted For de...

Page 221: ... which the interrupt is accepted are set in SPC The SR and R15 contents at the time of acceptance are set in SSR and SGR The code corresponding to the IRL 3 0 level is set in INTEVT See table 19 4 for the corresponding codes The BL MD and RB bits are set to 1 in SR and a branch is made to VBR H 0600 The acceptance level is not set in the interrupt mask bits in SR When the BL bit in SR is 1 the int...

Page 222: ...immediately after the instruction at which the interrupt is accepted are set in SPC The SR and R15 contents at the time of acceptance are set in SSR and SGR The code corresponding to the interrupt source is set in INTEVT The BL MD and RB bits are set to 1 in SR and a branch is made to VBR H 0600 The module interrupt levels should be set as values between B 0000 and B 1111 in the interrupt priority...

Page 223: ...e write exception in second data transfer 2 Indivisible delayed branch instruction and delay slot instruction As a delayed branch instruction and its associated delay slot instruction are indivisible they are treated as a single instruction Consequently the priority order for exceptions that occur in these instructions differs from the usual priority order The priority order shown below is for the...

Page 224: ...d SSR registers is undefined b Interrupt If an ordinary interrupt occurs the interrupt request is held pending and is accepted after the BL bit in SR has been cleared to 0 by software If a nonmaskable interrupt NMI occurs it can be held pending or accepted according to the setting made by software In the sleep or standby state however an interrupt is accepted even if the BL bit in SR is set to 1 3...

Page 225: ...andling routine Do not locate a BT BF BT S BF S BRA or BSR instruction at address VBR H 100 VBR H 400 or VBR H 600 When the UBDE bit in the BRCR register is set to 1 and the user break debug support function is used do not locate a BT BF BT S BF S BRA or BSR instruction at the address indicated by the DBR register Note See section 20 4 User Break Debug Support Function ...

Page 226: ...Section 5 Exceptions SH7751 Group SH7751R Group Page 172 of 1128 R01UH0457EJ0301 Rev 3 01 Sep 24 2013 ...

Page 227: ... exception sources FPU Error Invalid Operation Divide By Zero Overflow Underflow and Inexact Comprehensive instructions Single precision double precision graphics support system control When the FD bit in SR is set to 1 the FPU cannot be used and an attempt to execute an FPU instruction will cause an FPU disable exception 6 2 Data Formats 6 2 1 Floating Point Format A floating point number consist...

Page 228: ... shows bias Emin and Emax values Table 6 1 Floating Point Number Formats and Parameters Parameter Single Precision Double Precision Total bit width 32 bits 64 bits Sign bit 1 bit 1 bit Exponent field 8 bits 11 bits Fraction field 23 bits 52 bits Precision 24 bits 53 bits Bias 127 1023 Emax 127 1023 Emin 126 1022 Floating point number value v is determined as follows If E Emax 1 and f 0 v is a non ...

Page 229: ...ve zero H 00000000 H 00000000 00000000 Negative zero H 80000000 H 80000000 00000000 Negative denormalized number H 80000001 to H 807FFFFF H 80000000 00000001 to H 800FFFFF FFFFFFFF Negative normalized number H 80800000 to H FF7FFFFF H 80100000 00000000 to H FFEFFFFF FFFFFFFF Negative infinity H FF800000 H FFF00000 00000000 Quiet non number H FF800001 to H FFBFFFFF H FFF00000 00000001 to H FFF7FFFF...

Page 230: ...the EN V bit in the FPSCR register An exception will not be generated in this case The qNAN values generated by the FPU as operation results are as follows Single precision qNaN H 7FBFFFFF Double precision qNaN H 7FF7FFFF FFFFFFFF See the individual instruction descriptions for details of floating point operations when a non number NaN is input 6 2 3 Denormalized Numbers For a denormalized number ...

Page 231: ...PR0_BANK1 FPR15_BANK1 3 Double precision floating point registers DRi 8 registers A DR register comprises two FR registers DR0 FR0 FR1 DR2 FR2 FR3 DR4 FR4 FR5 DR6 FR6 FR7 DR8 FR8 FR9 DR10 FR10 FR11 DR12 FR12 FR13 DR14 FR14 FR15 4 Single precision floating point vector registers FVi 4 registers An FV register comprises four FR registers FV0 FR0 FR1 FR2 FR3 FV4 FR4 FR5 FR6 FR7 FV8 FR8 FR9 FR10 FR11 ...

Page 232: ...F4 XF5 XF6 XF7 XF8 XF9 XF10 XF11 XF12 XF13 XF14 XF15 FR0 FR1 FR2 FR3 FR4 FR5 FR6 FR7 FR8 FR9 FR10 FR11 FR12 FR13 FR14 FR15 DR0 DR2 DR4 DR6 DR8 DR10 DR12 DR14 FV0 FV4 FV8 FV12 XD0 XMTRX XD2 XD4 XD6 XD8 XD10 XD12 XD14 FPR0_BANK1 FPR1_BANK1 FPR2_BANK1 FPR3_BANK1 FPR4_BANK1 FPR5_BANK1 FPR6_BANK1 FPR7_BANK1 FPR8_BANK1 FPR9_BANK1 FPR10_BANK1 FPR11_BANK1 FPR12_BANK1 FPR13_BANK1 FPR14_BANK1 FPR15_BANK1 XF...

Page 233: ...NK0 are assigned to XF0 XF15 FPR0_BANK1 FPR15_BANK1 are assigned to FR0 FR15 SZ Transfer size mode SZ 0 The data size of the FMOV instruction is 32 bits SZ 1 The data size of the FMOV instruction is a 32 bit register pair 64 bits PR Precision mode PR 0 Floating point instructions are executed as single precision operations PR 1 Floating point instructions are executed as double precision operation...

Page 234: ... the FPU exception cause field and FPU exception flag field are set to 1 The FPU exception flag field holds the status of the exception generated after the field was last cleared RM Rounding mode RM 00 Round to Nearest RM 01 Round to Zero RM 10 Reserved RM 11 Reserved Bits 22 to 31 Reserved These bits are always read as 0 and should only be written with 0 6 3 3 Floating Point Communication Registe...

Page 235: ...2Emax 2 2 P or more the result will be infinity with the same sign as the unrounded value The values of Emax and P respectively are 127 and 24 for single precision and 1023 and 53 for double precision Round to Zero The digits below the round bit of the unrounded value are discarded If the unrounded value is larger than the maximum expressible absolute value the value will be the maximum expressibl...

Page 236: ... U FPSCR EN U 1 and instruction with possibility of operation result underflow Inexact exception I FPSCR EN I 1 and instruction with possibility of inexact operation result For information on possibilities which differ depending on the individual instruction see section 9 Instruction Descriptions in the SH 4 Software Manual All exception events that originate in the FPU are assigned as the same ex...

Page 237: ...duced in the result of the computation Maximum error MAX individual multiplication result 2 MIN number of multiplier significant digits 1 number of multiplicand significant digits 1 MAX result value 2 23 2 149 The number of significant digits is 24 for a normalized number and 23 for a denormalized number number of leading zeros in the fractional part In future version of SuperH RISC engine Family ...

Page 238: ...to check all data types in the registers beforehand when executing an FTRV instruction If the V bit is set in the FPU exception enable field FPU exception handling will be executed FRCHG This instruction modifies banked registers For example when the FTRV instruction is executed matrix elements must be set in an array in the background bank However to create the actual elements of a translation ma...

Page 239: ... mode is used and infinite precision operation result x is i or ii single precision or iii or iv double precision there are cases where the result after rounding is a normalized number but an underflow results In such cases where the result after rounding is a normalized number but an underflow results the FPU does not set the underflow flag to 1 In these cases the operation result the value writt...

Page 240: ... enable generation of inexact exceptions so that the exception handling routine can be used to check whether or not an underflow has occurred 6 7 2 Setting of Overflow Flag by FIPR or FTRV Instruction When the maximum error produced by the FIPR or FTRV instruction exceeds the maximum value expressible as a normalized number H 7F7FFFFF the overflow flag may be set even through the operation result ...

Page 241: ...conditions listed below the inexact bits FPSCR Flag I and FPSCR Cause I may not be set even through the operation result is inexact Condition 1 The operation instruction is a double precision FADD instruction or a double precision FSUB instruction Condition 2 The difference between the DRn and DRm exponents is between 43 and 50 Condition 3 At least one of bits 31 to 24 of the mantissa portion of w...

Page 242: ...equent rounding mechanism Strictly speaking it consists of the following a The infinite precision operation result b The closest expressible value less than a c The closest expressible value greater than a d The operation result when a is rounded correctly e The operation result when a is rounded by the FPU The rounding error when rounding is performed correctly in Round to Nearest mode is 0 d a 1...

Page 243: ...ture The SH 4 features a load store architecture in which operations are basically executed using registers Except for bit manipulation operations such as logical AND that are executed directly in memory operands in an operation that requires memory access are loaded into registers and the operation is executed between the registers Delayed Branches Except for the two branch instructions BF and BT...

Page 244: ... the MD bit is used before modification and in data access the MD bit is accessed after modification The other bits S T M Q FD BL and RB after modification are used for delay slot instruction execution The STC and STC L SR instructions access all SR bits after modification Constant Values An 8 bit constant value can be specified by the instruction code and an immediate value 16 bit and 32 bit cons...

Page 245: ...t Rn Effective address is register Rn Operand is register Rn contents Register indirect Rn Effective address is register Rn contents Rn Rn Rn EA EA effective address Register indirect with post increment Rn Effective address is register Rn contents A constant is added to Rn after instruction execution 1 for a byte operand 2 for a word operand 4 for a longword operand 8 for a quadword operand Rn Rn...

Page 246: ...isp 1 2 4 1 2 4 disp zero extended Byte Rn disp EA Word Rn disp 2 EA Longword Rn disp 4 EA Indexed register indirect R0 Rn Effective address is sum of register Rn and R0 contents Rn R0 Rn R0 Rn R0 EA GBR indirect with displacement disp 8 GBR Effective address is register GBR contents with 8 bit displacement disp added After disp is zero extended it is multiplied by 1 byte 2 word or 4 longword acco...

Page 247: ... After disp is zero extended it is multiplied by 2 word or 4 longword according to the operand size With a longword operand the lower 2 bits of PC are masked PC H FFFFFFFC PC 4 disp 2 or PC H FFFFFFFC 4 disp 4 4 2 4 disp zero extended With longword operand Word PC 4 disp 2 EA Longword PC H FFFFFFFC 4 disp 4 EA PC relative disp 8 Effective address is PC 4 with 8 bit displacement disp added after be...

Page 248: ...ata imm of TST AND OR or XOR instruction is zero extended imm 8 8 bit immediate data imm of MOV ADD or CMP EQ instruction is sign extended imm 8 8 bit immediate data imm of TRAPA instruction is zero extended and multiplied by 4 Note For the addressing modes below that use a displacement disp the assembler descriptions in this manual show the value before scaling 1 2 or 4 is performed according to ...

Page 249: ...ndividual bits Logical exclusive OR of individual bits Logical NOT of individual bits n n n bit shift Instruction code MSB LSB mmmm Register number Rm FRm nnnn Register number Rn FRn 0000 R0 FR0 0001 R1 FR1 1111 R15 FR15 mmm Register number DRm XDm Rm_BANK nnn Register number DRm XDm Rn_BANK 000 DR0 XD0 R0_BANK 001 DR2 XD2 R1_BANK 111 DR14 XD14 R7_BANK mm Register number FVm nn Register number FVn...

Page 250: ... Rn Rn 1 Rn Rm Rn 0010nnnnmmmm0100 MOV W Rm Rn Rn 2 Rn Rm Rn 0010nnnnmmmm0101 MOV L Rm Rn Rn 4 Rn Rm Rn 0010nnnnmmmm0110 MOV B Rm Rn Rm sign extension Rn Rm 1 Rm 0110nnnnmmmm0100 MOV W Rm Rn Rm sign extension Rn Rm 2 Rm 0110nnnnmmmm0101 MOV L Rm Rn Rm Rn Rm 4 Rm 0110nnnnmmmm0110 MOV B R0 disp Rn R0 disp Rn 10000000nnnndddd MOV W R0 disp Rn R0 disp 2 Rn 10000001nnnndddd MOV L Rm disp Rn Rm disp 4 R...

Page 251: ...disp GBR R0 disp 4 GBR 11000010dddddddd MOV B disp GBR R0 disp GBR sign extension R0 11000100dddddddd MOV W disp GBR R0 disp 2 GBR sign extension R0 11000101dddddddd MOV L disp GBR R0 disp 4 GBR R0 11000110dddddddd MOVA disp PC R0 disp 4 PC H FFFFFFFC 4 R0 11000111dddddddd MOVT Rn T Rn 0000nnnn00101001 SWAP B Rm Rn Rm swap lower 2 bytes Rn 0110nnnnmmmm1000 SWAP W Rm Rn Rm swap upper lower words Rn...

Page 252: ...011nnnnmmmm0011 Comparison result CMP HI Rm Rn When Rn Rm unsigned 1 T Otherwise 0 T 0011nnnnmmmm0110 Comparison result CMP GT Rm Rn When Rn Rm signed 1 T Otherwise 0 T 0011nnnnmmmm0111 Comparison result CMP PZ Rn When Rn 0 1 T Otherwise 0 T 0100nnnn00010001 Comparison result CMP PL Rn When Rn 0 1 T Otherwise 0 T 0100nnnn00010101 Comparison result CMP STR Rm Rn When any bytes are equal 1 T Otherwi...

Page 253: ...n Rm MAC MAC Rn 4 Rn Rm 4 Rm 32 32 64 64 bits 0000nnnnmmmm1111 MAC W Rm Rn Signed Rn Rm MAC MAC Rn 2 Rn Rm 2 Rm 16 16 64 64 bits 0100nnnnmmmm1111 MUL L Rm Rn Rn Rm MACL 32 32 32 bits 0000nnnnmmmm0111 MULS W Rm Rn Signed Rn Rm MACL 16 16 32 bits 0010nnnnmmmm1111 MULU W Rm Rn Unsigned Rn Rm MACL 16 16 32 bits 0010nnnnmmmm1110 NEG Rm Rn 0 Rm Rn 0110nnnnmmmm1011 NEGC Rm Rn 0 Rm T Rn borrow T 0110nnnnm...

Page 254: ... Rm Rn 0010nnnnmmmm1011 OR imm R0 R0 imm R0 11001011iiiiiiii OR B imm R0 GBR R0 GBR imm R0 GBR 11001111iiiiiiii TAS B Rn When Rn 0 1 T Otherwise 0 T In both cases 1 MSB of Rn 0100nnnn00011011 Test result TST Rm Rn Rn Rm when result 0 1 T Otherwise 0 T 0010nnnnmmmm1000 Test result TST imm R0 R0 imm when result 0 1 T Otherwise 0 T 11001000iiiiiiii Test result TST B imm R0 GBR R0 GBR imm when result ...

Page 255: ...Rn T 0100nnnn00100101 LSB SHAD Rm Rn When Rn 0 Rn Rm Rn When Rn 0 Rn Rm MSB Rn 0100nnnnmmmm1100 SHAL Rn T Rn 0 0100nnnn00100000 MSB SHAR Rn MSB Rn T 0100nnnn00100001 LSB SHLD Rm Rn When Rn 0 Rn Rm Rn When Rn 0 Rn Rm 0 Rn 0100nnnnmmmm1101 SHLL Rn T Rn 0 0100nnnn00000000 MSB SHLR Rn 0 Rn T 0100nnnn00000001 LSB SHLL2 Rn Rn 2 Rn 0100nnnn00001000 SHLR2 Rn Rn 2 Rn 0100nnnn00001001 SHLL8 Rn Rn 8 Rn 0100n...

Page 256: ...p 10001111dddddddd BT label When T 1 disp 2 PC 4 PC When T 0 nop 10001001dddddddd BT S label Delayed branch when T 1 disp 2 PC 4 PC When T 0 nop 10001101dddddddd BRA label Delayed branch disp 2 PC 4 PC 1010dddddddddddd BRAF Rn Rn PC 4 PC 0000nnnn00100011 BSR label Delayed branch PC 4 PR disp 2 PC 4 PC 1011dddddddddddd BSRF Rn Delayed branch PC 4 PR Rn PC 4 PC 0000nnnn00000011 JMP Rn Delayed branch...

Page 257: ...0010111 LDC L Rm VBR Rm VBR Rm 4 Rm 0100mmmm00100111 Privileged LDC L Rm SSR Rm SSR Rm 4 Rm 0100mmmm00110111 Privileged LDC L Rm SPC Rm SPC Rm 4 Rm 0100mmmm01000111 Privileged LDC L Rm DBR Rm DBR Rm 4 Rm 0100mmmm11110110 Privileged LDC L Rm Rn_BANK Rm Rn_BANK Rm 4 Rm 0100mmmm1nnn0111 Privileged LDS Rm MACH Rm MACH 0100mmmm00001010 LDS Rm MACL Rm MACL 0100mmmm00011010 LDS Rm PR Rm PR 0100mmmm001010...

Page 258: ... STC Rm_BANK Rn Rm_BANK Rn m 0 to 7 0000nnnn1mmm0010 Privileged STC L SR Rn Rn 4 Rn SR Rn 0100nnnn00000011 Privileged STC L GBR Rn Rn 4 Rn GBR Rn 0100nnnn00010011 STC L VBR Rn Rn 4 Rn VBR Rn 0100nnnn00100011 Privileged STC L SSR Rn Rn 4 Rn SSR Rn 0100nnnn00110011 Privileged STC L SPC Rn Rn 4 Rn SPC Rn 0100nnnn01000011 Privileged STC L SGR Rn Rn 4 Rn SGR Rn 0100nnnn00110010 Privileged STC L DBR Rn ...

Page 259: ... Rm DRn R0 Rm DRn 1111nnn0mmmm0110 FMOV Rm DRn Rm DRn Rm 8 Rm 1111nnn0mmmm1001 FMOV DRm Rn DRm Rn 1111nnnnmmm01010 FMOV DRm Rn Rn 8 Rn DRm Rn 1111nnnnmmm01011 FMOV DRm R0 Rn DRm R0 Rn 1111nnnnmmm00111 FLDS FRm FPUL FRm FPUL 1111mmmm00011101 FSTS FPUL FRn FPUL FRn 1111nnnn00001101 FABS FRn FRn H 7FFF FFFF FRn 1111nnnn01011101 FADD FRm FRn FRn FRm FRn 1111nnnnmmmm0000 FCMP EQ FRm FRn When FRn FRm 1 ...

Page 260: ...11101 FCNVSD FPUL DRn float_to_ double FPUL DRn 1111nnn010101101 FLOAT FPUL DRn float FPUL DRn 1111nnn000101101 FMUL DRm DRn DRn DRm DRn 1111nnn0mmm00010 FNEG DRn DRn H 8000 0000 0000 0000 DRn 1111nnn001001101 FSQRT DRn DRn DRn 1111nnn001101101 FSUB DRm DRn DRn DRm DRn 1111nnn0mmm00001 FTRC DRm FPUL long DRm FPUL 1111mmm000111101 Table 7 11 Floating Point Control Instructions Instruction Operation...

Page 261: ...X FVn FVn 1111nn0111111101 FRCHG FPSCR FR FPSCR FR 1111101111111101 FSCHG FPSCR SZ FPSCR SZ 1111001111111101 7 4 Usage Notes 7 4 1 Notes on TRAPA Instruction SLEEP Instruction and Undefined Instruction H FFFD Incorrect data may be written to the cache when a TRAPA instruction or undefined instruction code H FFFD is executed The ITLB hit judgment may be incorrect when a TRAPA instruction or undefin...

Page 262: ...ccur a The MMU is enabled MMUCR AT 1 b A TRAPA instruction or undefined instruction code H FFFD in a TLB conversion area U0 P0 or P3 area is executed c The four words of data following the TRAPA instruction or undefined instruction code H FFFD mentioned in b contain code that can be interpreted as an instruction to access read or write an address H F0000000 to H F7FFFFFF mapped to the internal cac...

Page 263: ...em use either of workarounds a or b below a Include a NOP instruction in the eight words of data following each TRAPA instruction SLEEP instruction or undefined instruction code H FFFD b Include an OR R0 R0 instruction in the five words of data following each TRAPA instruction SLEEP instruction or undefined instruction code H FFFD This workaround also applies to cases where the eight words of data...

Page 264: ...Section 7 Instruction Set SH7751 Group SH7751R Group Page 210 of 1128 R01UH0457EJ0301 Rev 3 01 Sep 24 2013 ...

Page 265: ...allel The execution cycles depend on the implementation of a processor Definitions in this section may not be applicable to SH 4 Core models other than this LSI 8 1 Pipelines Figure 8 1 shows the basic pipelines Normally a pipeline consists of five or six stages instruction fetch I decode and register read D execution EX SX F0 F1 F2 F3 data access NA MA and write back S FS An instruction is execut...

Page 266: ...ction fetch Instruction decode Issue Register read Non memory data access Write back I D SX Operation NA S 4 Special Load Store Pipeline Instruction fetch Instruction decode Issue Register read Memory data access Write back I D SX Address calculation MA S 5 Floating Point Pipeline Instruction fetch Instruction decode Issue Register read Computation 2 Computation 3 Write back I D F1 Computation 1 F...

Page 267: ... store 1 issue cycle MOV BWL FMOV LDS L to FPUL LDTLB PREF STS L from FPUL FPSCR I D EX MA S 3 GBR based load store 1 issue cycle MOV BWL d GBR I D SX MA S 4 JMP RTS BRAF 2 issue cycles I D EX NA S D EX NA S 5 TST B 3 issue cycles I D SX MA S D SX NA S D SX NA S 6 AND B OR B XOR B 4 issue cycles I D SX MA S D SX NA S D SX NA S D SX MA S 7 TAS B 5 issue cycles I D EX MA S D EX MA S D EX NA S D EX N...

Page 268: ... MA 13 TRAPA 7 issue cycles I D EX NA S D EX NA S D EX NA S D EX NA S D EX NA S D EX NA S D EX NA S 14 LDC to DBR Rp_BANK SSR SPC VBR BSR 1 issue cycle I D EX NA S SX SX 15 LDC to GBR 3 issue cycles I D EX NA S D D SX SX 16 LDC to SR 4 issue cycles I D EX NA S D D D SX SX SX I D EX MA S 17 LDC L to DBR Rp_BANK SSR SPC VBR 1 issue cycle SX SX 18 LDC L to GBR 3 issue cycles I D EX MA S D D SX SX Fig...

Page 269: ... SSR SPC VBR 2 issue cycles I D SX NA S D SX MA S 23 STC L from SGR 3 issue cycles I D SX NA S D SX NA S D SX MA S 24 LDS to PR JSR BSRF 2 issue cycles I D EX NA S D SX SX 25 LDS L to PR 2 issue cycles I D EX MA S D SX SX 26 STS from PR 2 issue cycles I D SX NA S D SX NA S 27 STS L from PR 2 issue cycles I D SX NA S D SX MA S 28 CLRMAC LDS to MACH L 1 issue cycle I D EX NA S F1 F1 F2 FS 29 LDS L t...

Page 270: ... 35 MAC W MAC L 2 issue cycles I D EX MA S CPU D EX MA S f1 FPU f1 f1 f1 F2 FS 36 Single precision floating point computation 1 issue cycle FCMP EQ FCMP GT FADD FLOAT FMAC FMUL FSUB FTRC FRCHG FSCHG I D F1 F2 FS 37 Single precision FDIV SQRT 1 issue cycle I D F1 F2 FS F3 F1 F2 FS 38 Double precision floating point computation 1 1 issue cycle FCNVDS FCNVSD FLOAT FTRC I D F1 F2 FS d F1 F2 FS 39 Doub...

Page 271: ...RT 1 issue cycle FDIV FSQRT F1 F2 d F1 F2 FS F1 F2 FS 42 FIPR 1 issue cycle I D F0 F1 F2 FS 43 FTRV 1 issue cycle F1 F2 FS D F0 I F1 F2 FS d F0 F1 F2 FS d F0 F1 F2 FS d F0 Notes Locks D stage Register read only Locks but no operation is executed Can overlap another f1 but not another F1 d D f1 Cannot overlap a stage of the same kind except when two instructions are executed in parallel Figure 8 2 ...

Page 272: ...T Group CLRT CMP HI Rm Rn MOV Rm Rn CMP EQ imm R0 CMP HS Rm Rn NOP CMP EQ Rm Rn CMP PL Rn SETT CMP GE Rm Rn CMP PZ Rn TST imm R0 CMP GT Rm Rn CMP STR Rm Rn TST Rm Rn 2 EX Group ADD imm Rn MOVT Rn SHLL2 Rn ADD Rm Rn NEG Rm Rn SHLL8 Rn ADDC Rm Rn NEGC Rm Rn SHLR Rn ADDV Rm Rn NOT Rm Rn SHLR16 Rn AND imm R0 OR imm R0 SHLR2 Rn AND Rm Rn OR Rm Rn SHLR8 Rn DIV0S Rm Rn ROTCL Rn SUB Rm Rn DIV0U ROTCR Rn S...

Page 273: ...FMOV Rm DRn LDS Rm FPUL MOV W disp Rm R0 FMOV Rm XDn MOV B disp GBR R0 MOV W R0 Rm Rn FMOV Rm DRn MOV B disp Rm R0 MOV W Rm Rn FMOV Rm XDn MOV B R0 Rm Rn MOV W Rm Rn FMOV DRm R0 Rn MOV B Rm Rn MOV W R0 disp GBR FMOV DRm Rn MOV B Rm Rn MOV W R0 disp Rn FMOV DRm Rn MOV B R0 disp GBR MOV W Rm R0 Rn FMOV DRm DRn MOV B R0 disp Rn MOV W Rm Rn FMOV DRm XDn MOV B Rm R0 Rn MOV W Rm Rn FMOV FRm FRn MOV B Rm...

Page 274: ...Group FADD DRm DRn FIPR FVm FVn FSQRT DRn FADD FRm FRn FLOAT FPUL DRn FSQRT FRn FCMP EQ FRm FRn FLOAT FPUL FRn FSUB DRm DRn FCMP GT FRm FRn FMAC FR0 FRm FRn FSUB FRm FRn FCNVDS DRm FPUL FMUL DRm DRn FTRC DRm FPUL FCNVSD FPUL DRn FMUL FRm FRn FTRC FRm FPUL FDIV DRm DRn FRCHG FTRV XMTRX FVn FDIV FRm FRn FSCHG ...

Page 275: ...TC L SPC Rn FCMP GT DRm DRn LDS L Rm PR STC L SR Rn JMP Rn LDTLB STC L SSR Rn JSR Rn MAC L Rm Rn STC L VBR Rn LDC Rm DBR MAC W Rm Rn STS FPSCR Rn LDC Rm GBR MUL L Rm Rn STS MACH Rn LDC Rm Rp_BANK MULS W Rm Rn STS MACL Rn LDC Rm SPC MULU W Rm Rn STS PR Rn LDC Rm SR OR B imm R0 GBR STS L FPSCR Rn LDC Rm SSR RTE STS L FPUL Rn LDC Rm VBR RTS STS L MACH Rn LDC L Rm DBR SETS STS L MACL Rn LDC L Rm GBR S...

Page 276: ...heral units The frequency ratios of the three clocks are determined with the frequency control register FRQCR In this section machine cycles are based on the I clock unless otherwise specified For details of FRQCR see section 10 Clock Oscillation Circuits Instruction execution cycles are summarized in table 8 3 Penalty cycles due to a pipeline stall or freeze are not considered in this table Issue...

Page 277: ...ow dependency write after read as in the following cases FTRV is the preceding instruction 5 cycles A double precision FADD FSUB or FMUL is the preceding instruction 2 cycles In the case of flow dependency latency may be exceptionally increased or decreased depending on the combination of sequential instructions figure 8 3 e When a floating point computation is followed by a floating point registe...

Page 278: ...he interfering instructions For example when a load instruction and an ADD instruction that references the loaded value are consecutive the 2 cycle stall of the ADD is eliminated by inserting three instructions without dependency Software performance can be improved by such instruction scheduling Other causes of a stall are as follows Instruction TLB miss Instruction access to external memory inst...

Page 279: ...tall BT L_skip ADD 1 R0 L_skip i D E A S 4 stall cycles EX group SHAD and EX group ADD cannot be executed in parallel Therefore SHAD is issued first and the following ADD is recombined with the next instruction EX group ADD and LS group MOV L can be executed in parallel Overlapping of stages in the 2nd instruction is possible AND B and MOV are fetched simultaneously but MOV is stalled due to resou...

Page 280: ...R4 FLOAT FPUL DR0 FMOV S FR0 R15 FR3 write FR2 write I D F1 F2 FS d F1 F2 FS I D EX MA S 3 cycle latency for upper lower FR FR1 write FR0 write FLDI1 FR3 FIPR FV0 FV4 FMOV R1 XD14 FTRV XMTRX FV0 I D EX NA S I D d F0 F1 F2 FS Zero cycle latency 3 cycle increase 3 stall cycles I D EX MA S I D d F0 F1 F2 FS d F0 F1 FS F2 d F0 F2 F1 FS d F1 F0 F2 FS 2 cycle latency 1 cycle increase 3 stall cycles The ...

Page 281: ...dency D F1 F2 FS I I D F1 F2 FS F1 F2 FS 11 cycle latency 10 stall cycles latency 11 1 The registers are written back in program order D F1 F2 FS I d F1 F2 FS d F1 F2 FS d F1 F2 FS d F1 F2 FS F1 F2 FS EX NA S I D 7 cycle latency for lower FR 8 cycle latency for upper FR 6 stall cycles longest latency 8 2 FR2 write FR3 write D F1 F2 FS I d F1 F2 FS d F1 F2 FS d F1 F0 F0 F0 F0 F2 FS g Anti flow depe...

Page 282: ...I 3 stall cycles STC GBR R2 FADD DR0 DR2 I D F1 F2 FS d F1 F2 FS d F1 F2 FS d F1 F2 FS d F1 F2 FS F1 F2 FS EX MA S f1 EX MA S D f1 f1 F2 FS f1 F2 FS I D 5 stall cycles MAC W R1 R2 I D EX MA S f1 f1 f1 F2 FS f1 F2 FS I f1 D EX MA S f1 D EX MA S f1 F2 FS f1 F2 FS F1 F2 FS d F1 F2 FS d F1 F2 FS d F1 F2 FS d F1 F2 FS F1 I D 3 stall cycles 1 stall cycle 2 stall cycles MAC W R1 R2 MAC W R1 R2 FADD DR4 D...

Page 283: ...9 MOV L disp PC Rn LS 1 2 2 10 MOV B Rm Rn LS 1 2 2 11 MOV W Rm Rn LS 1 2 2 12 MOV L Rm Rn LS 1 2 2 13 MOV B Rm Rn LS 1 1 2 2 14 MOV W Rm Rn LS 1 1 2 2 15 MOV L Rm Rn LS 1 1 2 2 16 MOV B disp Rm R0 LS 1 2 2 17 MOV W disp Rm R0 LS 1 2 2 18 MOV L disp Rm Rn LS 1 2 2 19 MOV B R0 Rm Rn LS 1 2 2 20 MOV W R0 Rm Rn LS 1 2 2 21 MOV L R0 Rm Rn LS 1 2 2 22 MOV B disp GBR R0 LS 1 2 3 23 MOV W disp GBR R0 LS ...

Page 284: ... 40 MOVCA L R0 Rn LS 1 3 7 12 MA 4 3 7 41 MOVT Rn EX 1 1 1 42 OCBI Rn LS 1 1 2 10 MA 4 1 2 43 OCBP Rn LS 1 1 5 11 MA 4 1 5 44 OCBWB Rn LS 1 1 5 11 MA 4 1 5 45 PREF Rn LS 1 1 2 46 SWAP B Rm Rn EX 1 1 1 47 SWAP W Rm Rn EX 1 1 1 Data transfer instructions 48 XTRCT Rm Rn EX 1 1 1 49 ADD Rm Rn EX 1 1 1 50 ADD imm Rn EX 1 1 1 51 ADDC Rm Rn EX 1 1 1 52 ADDV Rm Rn EX 1 1 1 53 CMP EQ imm R0 MT 1 1 1 54 CMP...

Page 285: ...5 F1 4 2 70 MUL L Rm Rn CO 2 4 4 34 F1 4 2 71 MULS W Rm Rn CO 2 4 4 34 F1 4 2 72 MULU W Rm Rn CO 2 4 4 34 F1 4 2 73 NEG Rm Rn EX 1 1 1 74 NEGC Rm Rn EX 1 1 1 75 SUB Rm Rn EX 1 1 1 76 SUBC Rm Rn EX 1 1 1 Fixed point arithmetic instructions 77 SUBV Rm Rn EX 1 1 1 78 AND Rm Rn EX 1 1 1 79 AND imm R0 EX 1 1 1 80 AND B imm R0 GBR CO 4 4 6 81 NOT Rm Rn EX 1 1 1 82 OR Rm Rn EX 1 1 1 83 OR imm R0 EX 1 1 1...

Page 286: ...1 1 1 98 SHAR Rn EX 1 1 1 99 SHLD Rm Rn EX 1 1 1 100 SHLL Rn EX 1 1 1 101 SHLL2 Rn EX 1 1 1 102 SHLL8 Rn EX 1 1 1 103 SHLL16 Rn EX 1 1 1 104 SHLR Rn EX 1 1 1 105 SHLR2 Rn EX 1 1 1 106 SHLR8 Rn EX 1 1 1 Shift instructions 107 SHLR16 Rn EX 1 1 1 108 BF disp BR 1 2 or 1 1 109 BF S disp BR 1 2 or 1 1 110 BT disp BR 1 2 or 1 1 111 BT S disp BR 1 2 or 1 1 112 BRA disp BR 1 2 1 113 BRAF Rn CO 2 3 4 114 B...

Page 287: ...Rp_BANK CO 1 3 14 SX 3 2 132 LDC Rm SR CO 4 4 16 SX 3 2 133 LDC Rm SSR CO 1 3 14 SX 3 2 134 LDC Rm SPC CO 1 3 14 SX 3 2 135 LDC Rm VBR CO 1 3 14 SX 3 2 136 LDC L Rm DBR CO 1 1 3 17 SX 3 2 137 LDC L Rm GBR CO 3 3 3 18 SX 3 2 138 LDC L Rm Rp_BANK CO 1 1 3 17 SX 3 2 139 LDC L Rm SR CO 4 4 4 19 SX 3 2 140 LDC L Rm SSR CO 1 1 3 17 SX 3 2 141 LDC L Rm SPC CO 1 1 3 17 SX 3 2 142 LDC L Rm VBR CO 1 1 3 17 ...

Page 288: ...p_BANK Rn CO 2 2 2 22 161 STC L SR Rn CO 2 2 2 22 162 STC L SSR Rn CO 2 2 2 22 163 STC L SPC Rn CO 2 2 2 22 164 STC L VBR Rn CO 2 2 2 22 165 STS MACH Rn CO 1 3 30 166 STS MACL Rn CO 1 3 30 167 STS PR Rn CO 2 2 26 168 STS L MACH Rn CO 1 1 1 31 169 STS L MACL Rn CO 1 1 1 31 System control instructions 170 STS L PR Rn CO 2 2 2 27 171 FLDI0 FRn LS 1 0 1 172 FLDI1 FRn LS 1 0 1 173 FMOV FRm FRn LS 1 0 1...

Page 289: ...1 11 12 37 F3 2 9 F1 10 1 192 FSUB FRm FRn FE 1 3 4 36 193 FTRC FRm FPUL FE 1 3 4 36 194 FMOV DRm DRn LS 1 0 1 195 FMOV Rm DRn LS 1 2 2 196 FMOV Rm DRn LS 1 1 2 2 197 FMOV R0 Rm DRn LS 1 2 2 198 FMOV DRm Rn LS 1 1 2 199 FMOV DRm Rn LS 1 1 1 2 Single precision floating point instructions 200 FMOV DRm R0 Rn LS 1 1 2 201 FABS DRn LS 1 0 1 202 FADD DRm DRn FE 1 7 8 9 39 F1 2 6 203 FCMP EQ DRm DRn CO 2...

Page 290: ...TS L FPUL Rn CO 1 1 1 2 FPU system control instructions 221 STS L FPSCR Rn CO 1 1 1 2 222 FMOV DRm XDn LS 1 0 1 223 FMOV XDm DRn LS 1 0 1 224 FMOV XDm XDn LS 1 0 1 225 FMOV Rm XDn LS 1 2 2 226 FMOV Rm XDn LS 1 1 2 2 227 FMOV R0 Rm XDn LS 1 2 2 228 FMOV XDm Rn LS 1 1 2 229 FMOV XDm Rm LS 1 1 1 2 230 FMOV XDm R0 Rn LS 1 1 2 231 FIPR FVm FVn FE 1 4 5 42 F1 3 1 232 FRCHG FE 1 1 4 36 233 FSCHG FE 1 1 4...

Page 291: ...ation is decreased by 1 cycle 2 When the preceding instruction loads the shift amount of the following SHAD SHLD the latency of the load is increased by 1 cycle 3 When an LS group instruction with a latency of less than 3 cycles is followed by a double precision floating point instruction FIPR or FTRV the latency of the first instruction is increased to 3 cycles Example In the case of FMOV FR4 FR0...

Page 292: ...s access etc occurs may include an increased number of cycles in addition to the number of memory access cycles set by the bus state controller BSC etc For example the occurrence of the following may result in idle cycles as observed from the external bus 1 Transfer of data from the logical address bus to the physical address bus 2 Transfer of data between buses using different operation clocks Th...

Page 293: ...halted enabling power consumption to be reduced 9 1 1 Types of Power Down Modes The following power down modes and functions are provided Sleep mode Deep sleep mode Standby mode Hardware standby mode Module standby function TMU RTC SCI SCIF DMAC SQ and UBC Table 9 1 shows the conditions for entering these modes from the program execution state the status of the CPU and peripheral modules in each m...

Page 294: ...truction executed while STBY bit is 0 in STBCR and DSLP bit is 1 in STBCR2 Operating Halted registers held Held Operating DMA halted Held Self refresh ing Interrupt Reset Standby SLEEP instruction executed while STBY bit is 1 in STBCR Halted Halted registers held Held Halted Held Self refresh ing Interrupt Reset Hard ware standby Setting CA pin to low level Halted Halted Unde fined Halted High imp...

Page 295: ...000 H FE0A0000 H 1E0A0000 32 Clock stop clear register CLKSTPCLR00 W H 00000000 H FE0A0008 H 1E0A0008 32 9 1 3 Pin Configuration Table 9 3 shows the pins used for power down mode control Table 9 3 Power Down Mode Pins Pin Name Abbreviation I O Function Processor status 1 Processor status 0 STATUS1 STATUS0 Output Indicate the processor s operating status STATUS1 STATUS0 HH Reset HL Sleep mode LH St...

Page 296: ... Bit 6 Peripheral Module Pin High Impedance Control PHZ Controls the state of peripheral module related pins in standby mode When the PHZ bit is set to 1 peripheral module related pins go to the high impedance state in standby mode For the relevant pins see section 9 2 2 Peripheral Module Pin High Impedance Control Bit 6 PHZ Description 0 Peripheral module related pins are in normal state Initial ...

Page 297: ...hip peripheral modules The clock supply to the SCIF is stopped when the MSTP3 bit is set to 1 Bit 3 MSTP3 Description 0 SCIF operates Initial value 1 SCIF clock supply is stopped Bit 2 Module Stop 2 MSTP2 Specifies stopping of the clock supply to the timer unit channel 0 to 2 TMU among the on chip peripheral modules The clock supply to the TMU is stopped when the MSTP2 bit is set to 1 Bit 2 MSTP2 ...

Page 298: ... to 1 peripheral module related pins go to the high impedance state in standby mode Relevant Pins SCI related pins SCK MD0 SCK2 TXD MD1 TXD2 MD7 CTS2 MD8 RTS2 DMA related pins DACK0 DRAK0 DACK1 DRAK1 Other Information The setting in this register is invalid when the above pins are used as port output pins For details of pin states see Appendix D Pin Functions 9 2 3 Peripheral Module Pin Pull Up Co...

Page 299: ... to deep sleep mode on execution of SLEEP instruction Note When the STBY bit in the STBCR register is 0 Bit 6 STATUS Pin High Impedance Control STHZ This bit selects whether the STATUS0 and 1 pins are set to high impedance when in hardware standby mode Bit 6 STHZ Description 0 Sets STATUS0 1 pins to high impedance when in hardware standby mode Initial value 1 Drives STATUS0 1 pins to LH when in ha...

Page 300: ...l modules The clock supply is restarted by writing 1 to the corresponding bit in the CLKSTPCLR00 register Writing 0 to CLKSTP00 will not change the bit value CLKSTP00 is initialized to H 00000000 by a reset It is not initialized in standby mode Bit 31 30 29 11 10 9 8 Initial value 0 0 0 0 0 0 0 R W R R R R R R R Bit 7 6 5 4 3 2 1 0 CSTP2 CSTP1 CSTP0 Initial value 0 0 0 0 0 0 0 0 R W R R R R R R W ...

Page 301: ...nd TMU channel 3 and 4 interrupts Initial value 1 INTC does not detect PCIC and TMU channel 3 and 4 interrupts 9 2 6 Clock Stop Clear Register 00 CLKSTPCLR00 Clock stop clear register 00 CLKSTPCLR00 is a 32 bit write only register that is used to clear corresponding bits in the CLKSTP00 register Bit 31 30 29 11 10 9 8 Initial value 0 0 0 0 0 0 0 R W W W W W W W W Bit 7 6 5 4 3 2 1 0 Initial value ...

Page 302: ...upt When an NMI IRL or on chip peripheral module interrupt is generated sleep mode is exited and interrupt exception handling is executed The code corresponding to the interrupt source is set in the INTEVT register Exit by Reset Sleep mode is exited by means of a power on or manual reset via the RESET pin or a power on or manual reset executed when the watchdog timer overflows 9 4 Deep Sleep Mode ...

Page 303: ... refreshed use this function when the DSLP bit of STBCR2 is set to 0 9 5 2 Exit from Pin Sleep Mode Setting the SLEEP pin level high causes this LSI to return to the normal state The pin sleep mode is also canceled when the conditions specified in section 9 3 2 Exit From Sleep Mode are satisfied In a power on reset the SLEEP pin should be fixed high 9 6 Standby Mode 9 6 1 Transition to Standby Mod...

Page 304: ...d stop the WDT Set the initial value for the up count in the WDT timer counter WTCNT and set the clock to be used for the up count in bits CKS2 CKS0 in the WTCSR register 2 Set the STBY bit in the STBCR register to 1 then execute a SLEEP instruction 3 When standby mode is entered and the chip s internal clock stops a low level signal is output at the STATUS1 pin and a high level signal at the STAT...

Page 305: ...the transition procedure described above 2 When standby mode is entered and the chip s internal clock stops a low level signal is output at the STATUS1 pin and a high level signal at the STATUS0 pin 3 The input clock is stopped or its frequency changed after the STATUS1 pin goes low and the STATUS0 pin high 4 When the frequency is changed input an NMI or IRL interrupt after the change When the clo...

Page 306: ...TP1 0 RTC operates 1 Clock supplied to RTC is stopped 2 MSTP0 0 SCI operates 1 Clock supplied to SCI is stopped Notes 1 The register initialized is the same as in standby mode but initialization is not performed if the RTC clock is not in use see section 12 Timer Unit TMU 2 The counter operates when the START bit in RCR2 is 1 see section 11 Realtime Clock RTC 3 For details see section 20 6 User Br...

Page 307: ...the STHZ bit of STBCR2 See section D Pin Functions for details of output pin states Operation when a low level is input to the CA pin when in the standby mode depends on the CPG status as follows 1 In standby mode The clock remains stopped and a transition is made to the hardware standby state Interrupts and manual resets are disabled but the output pins remain in the same state as in standby mode...

Page 308: ...PLL1 and VDD PLL2 power supply pins in addition to the RTC power supply pin in hardware standby mode 9 9 STATUS Pin Change Timing The STATUS1 and STATUS0 pin change timing is shown below The meaning of the STATUS pin settings is as follows Reset HH STATUS1 high STATUS0 high Sleep HL STATUS1 high STATUS0 low Standby LH STATUS1 low STATUS0 high Normal LL STATUS1 low STATUS0 low The meaning of the cl...

Page 309: ... Bcyc 0 30 Bcyc PLL stabilization time Figure 9 1 STATUS Output in Power On Reset Manual Reset CKIO High RESET MRESET STATUS Normal Reset Normal 0 30 Bcyc 0 Bcyc Note In a manual reset STATUS HH reset is set and an internal reset started after waiting until the end of the currently executing bus cycle Must be asserted for tRESW or longer Figure 9 2 STATUS Output in Manual Reset ...

Page 310: ...terrupt request WDT overflow Figure 9 3 STATUS Output in Standby Interrupt Sequence Standby Power On Reset Reset CKIO RESET 1 STATUS Normal Reset Normal 0 10 Bcyc Standby Oscillation stops 2 0 30 Bcyc Notes 1 When standby mode is exited by means of a power on reset a WDT count is not performed Hold RESET low for the PLL oscillation stabilization time 2 Undefined Figure 9 4 STATUS Output in Standby...

Page 311: ...0 20 Bcyc 0 30 Bcyc Note When standby mode is exited by means of a manual reset a WDT count is not performed Hold MRESET low for the PLL oscillation stabilization time Reset Oscillation stops Figure 9 5 STATUS Output in Standby Manual Reset Sequence 9 9 3 In Exit from Sleep Mode Sleep Interrupt CKIO STATUS Normal Sleep Normal Interrupt request Figure 9 6 STATUS Output in Sleep Interrupt Sequence ...

Page 312: ...1 Sep 24 2013 Sleep Power On Reset Reset CKIO STATUS Normal Reset Sleep Normal 0 10 Bcyc 0 30 Bcyc RESET 1 2 Notes 1 When sleep mode is exited by means of a power on reset hold RESET low for the oscillation stabilization time 2 Undefined Figure 9 7 STATUS Output in Sleep Power On Reset Sequence ...

Page 313: ...es R01UH0457EJ0301 Rev 3 01 Page 259 of 1128 Sep 24 2013 Sleep Manual Reset Reset RESET STATUS Normal Reset MRESET Sleep Normal CKIO High 0 30 Bcyc 0 30 Bcyc Note Hold MRESET low until STATUS reset Figure 9 8 STATUS Output in Sleep Manual Reset Sequence ...

Page 314: ...leep Normal Interrupt request Figure 9 9 STATUS Output in Deep Sleep Interrupt Sequence Deep Sleep Power On Reset Reset CKIO STATUS Normal Sleep Reset Normal 0 10 Bcyc 0 30 Bcyc RESET 1 2 Notes 1 When deep sleep mode is exited by means of a power on reset hold RESET low for the oscillation stabilization time 2 Undefined Figure 9 10 STATUS Output in Deep Sleep Power On Reset Sequence ...

Page 315: ...UH0457EJ0301 Rev 3 01 Page 261 of 1128 Sep 24 2013 Deep Sleep Manual Reset Reset RESET STATUS Normal Sleep Reset MRESET Normal CKIO High 0 30 Bcyc 0 30 Bcyc Note Hold MRESET low until STATUS reset Figure 9 11 STATUS Output in Deep Sleep Manual Reset Sequence ...

Page 316: ...e standby mode The CA pin level must be kept low while in hardware standby mode After setting the RESET pin level low the clock starts when the CA pin level is switched to high CKIO CA STATUS Reset 0 10 Bcyc 0 10 Bcyc Standby 2 RESET Waiting for end of bus cycle Undefined Notes 1 Same at sleep and reset 2 High impedance when STBCR2 STHZ 0 Normal 1 Figure 9 12 Hardware Standby Mode Timing When CA L...

Page 317: ...A STATUS Standby 0 10 Bcyc Normal RESET Standby WDT count WDT overflow Interrupt request Note High impedance when STBCR2 STHZ 0 Figure 9 13 Hardware Standby Mode Timing When CA Low in WDT Operation VDDQ VDD RESET CA Min 0s Min 0s Max 50 μs Note VDDQ VDD CPG VDD min Figure 9 14 Timing When Power Other than VDD RTC Is Off ...

Page 318: ...mption may exceed the maximum value for sleep mode or standby mode during the period until one or more of the arithmetic operation or floating point operation instructions listed below is executed 1 Arithmetic operation instructions MAC W MAC L 2 Floating point operation instructions When FPSCR PR 0 FADD FSUB FMUL FMAC FLOAT FTRC FDIV FSQRT FIPR FTRV When FPSCR PR 1 FADD FSUB FMUL FLOAT FTRC FDIV ...

Page 319: ...Page 265 of 1128 Sep 24 2013 Example To reduce the effect on FPSCR arrange the following two instructions starting at H A0000000 Address Instruction String H A0000000 FLDI1 FR0 H A0000002 FADD FR0 FR0 FLDI1 FR0 loads 1 into FR0 so the cause and flag bits of FPSCR are not set to 1 ...

Page 320: ...Section 9 Power Down Modes SH7751 Group SH7751R Group Page 266 of 1128 R01UH0457EJ0301 Rev 3 01 Sep 24 2013 ...

Page 321: ...FPU caches and TLB the peripheral module clock Pck used by the peripheral modules and the bus clock Bck used by the external bus interface Six clock modes Any of six clock operating modes can be selected with different combinations of CPU clock bus clock and peripheral module clock division ratios after a power on reset Frequency change function PLL phase locked loop circuits and a frequency divid...

Page 322: ... watchdog timer mode and interval timer mode Internal reset generation in watchdog timer mode An internal reset is executed on counter overflow Power on reset or manual reset can be selected Interrupt generation in interval timer mode An interval timer interrupt is generated on counter overflow Selection of eight counter input clocks Any of eight clocks can be selected scaled from the 1 clock of f...

Page 323: ... STBCR Standby control register STBCR2 Standby control register 2 Oscillator circuit PLL circuit 1 Frequency divider 2 Crystal oscillation circuit Frequency divider 1 PLL circuit 2 CPU clock Ick cycle Icyc Peripheral module clock Pck cycle Pcyc Bus clock Bck cycle Bcyc CPG control unit Clock frequency control circuit Standby control circuit Bus interface Internal bus XTAL EXTAL MD8 CKIO MD2 MD1 MD...

Page 324: ...egister 2 Oscillator circuit PLL circuit 1 Frequency divider 2 Crystal oscillation circuit CPU clock Ick cycle Icyc Peripheral module clock Pck cycle Pcyc Bus clock Bck cycle Bcyc CPG control unit Clock frequency control circuit Standby control circuit Bus interface Internal bus XTAL EXTAL MD8 CKIO MD2 MD1 MD0 FRQCR STBCR2 1 1 2 1 3 1 4 1 6 1 8 6 12 PLL circuit 2 1 STBCR Figure 10 1 2 Block Diagra...

Page 325: ...eform duty to 50 by halving the input clock frequency when clock input from the EXTAL pin is supplied internally without using PLL circuit 1 Frequency Divider 2 Frequency divider 2 generates the CPU clock Ick bus clock Bck and peripheral module clock Pck The division ratio is set in the frequency control register Clock Frequency Control Circuit The clock frequency control circuit controls the cloc...

Page 326: ...resonator When MD8 0 external clock is input from EXTAL When MD8 1 crystal resonator is connected directly to EXTAL and XTAL Clock output pin CKIO Output Used as external clock output pin Level can also be fixed CKIO enable pin CKE Output 0 when CKIO output clock is unstable and in case of synchronous DRAM self refreshing Note Set to 1 in a power on reset For details of synchronous DRAM self refre...

Page 327: ...3 0 1 1 Off On On 6 2 1 H 0E13 4 1 0 0 On On On 3 3 2 3 4 H 0E0A 5 1 Off On On 6 3 3 2 H 0E0A 6 1 0 Off Off Off 1 1 2 1 2 H 0808 Notes 1 The clock operating mode is the only factor to determine whether to turn the 1 2 frequency divider on or off 2 For the frequency range of the input clock see the EXTAL clock input frequency fEX and CKIO clock output fOP in section 23 3 1 Clock and Control Signal ...

Page 328: ...es Frequency Division Ratio of Frequency Divider 2 FRQCR Lower 9 Bits CPU Clock Bus Clock Peripheral Module Clock H 000 1 2 H 002 1 4 H 004 1 1 8 H 008 1 2 H 00A 1 4 H 00C 1 2 1 8 H 011 1 3 H 013 1 3 1 6 H 01A 1 4 H 01C 1 4 1 8 H 023 1 6 1 6 H 02C 1 1 8 1 8 H 048 1 2 H 04A 1 4 H 04C 1 2 1 8 H 05A 1 4 H 05C 1 4 1 8 H 063 1 6 1 6 H 06C 1 2 1 8 1 8 H 091 1 3 H 093 1 3 1 6 H 0A3 1 3 1 6 1 6 H 0DA 1 4 ...

Page 329: ...mode Bit 15 14 13 12 11 10 9 8 CKOEN PLL1EN PLL2EN IFC2 Initial value 0 0 0 0 1 1 1 R W R W R W R W R R W R W R W R W Bit 7 6 5 4 3 2 1 0 IFC1 IFC0 BFC2 BFC1 BFC0 PFC2 PFC1 PFC0 Initial value R W R W R W R W R W R W R W R W R W Bits 15 to 12 Reserved These bits are always read as 0 and should only be written with 0 Bit 11 Clock Output Enable CKOEN Specifies whether a clock is output from the CKIO ...

Page 330: ...LL Circuit 2 Enable PLL2EN Specifies whether PLL circuit 2 is on or off Bit 9 PLL2EN Description 0 PLL circuit 2 is not used 1 PLL circuit 2 is used Initial value Bits 8 to 6 CPU Clock Frequency Division Ratio IFC These bits specify the CPU clock frequency division ratio with respect to the input clock 1 2 frequency divider or PLL circuit 1 output frequency Bit 8 IFC2 Bit 7 IFC1 Bit 6 IFC0 Descrip...

Page 331: ...requency Bit 5 BFC2 Bit 4 BFC1 Bit 3 BFC0 Description 0 0 0 1 1 1 2 1 0 1 3 1 1 4 1 0 0 1 6 1 1 8 Other than the above Setting prohibited Do not set Bits 2 to 0 Peripheral Module Clock Frequency Division Ratio PFC These bits specify the peripheral module clock frequency division ratio with respect to the input clock 1 2 frequency divider or PLL circuit 1 output frequency Bit 2 PFC2 Bit 1 PFC1 Bit ...

Page 332: ...atio WTCNT counter Initial counter value 2 Set the PLL1EN bit to 1 3 Internal processor operation stops temporarily and the WDT starts counting up The internal clock stops and an unstable clock is output to the CKIO pin 4 After the WDT count overflows clock supply begins within the chip and the processor resumes operation The WDT stops after overflowing 10 5 2 Changing PLL Circuit 1 Starting Stopp...

Page 333: ...and an unstable clock is output to the CKIO pin 4 After the WDT count overflows clock supply begins within the chip and the processor resumes operation The WDT stops after overflowing 10 5 4 Changing Bus Clock Division Ratio When PLL Circuit 2 Is Off If PLL circuit 2 is off when the bus clock frequency division ratio is changed a WDT count is not performed 1 Set the BFC2 BFC0 bits to the desired v...

Page 334: ...to the high impedance state it is pulled up 10 7 Overview of Watchdog Timer 10 7 1 Block Diagram Figure 10 2 shows a block diagram of the WDT Standby release Internal reset request Interrupt request Standby control Reset control Interrupt control WTCSR WTCNT Bus interface Clock selection Overflow Frequency divider Clock selector Clock WDT Legend WTCSR Watchdog timer control status register WTCNT W...

Page 335: ...word size access when writing Perform the write with the upper byte set to H 5A or H A5 respectively Byte and longword size writes cannot be used Use byte access when reading 10 8 WDT Register Descriptions 10 8 1 Watchdog Timer Counter WTCNT The watchdog timer counter WTCNT is an 8 bit readable writable counter that counts up on the selected clock When WTCNT overflows a reset is generated in watch...

Page 336: ... byte size access Bit 7 6 5 4 3 2 1 0 TME WT IT RSTS WOVF IOVF CKS2 CKS1 CKS0 Initial value 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W Bit 7 Timer Enable TME Specifies starting and stopping of timer operation Clear this bit to 0 when using the WDT in standby mode or to change a clock frequency Bit 7 TME Description 0 Up count stopped WTCNT value retained Initial value 1 Up count started B...

Page 337: ...erval timer mode Bits 2 to 0 Clock Select 2 to 0 CKS2 CKS0 These bits select the clock used for the WTCNT count from eight clocks obtained by dividing the frequency divider 2 input clock The overflow periods shown in the following table are for use of a 33 MHz input clock with frequency divider 1 off and PLL circuit 1 on 6 Note When PLL1 is switched on or off the clock following the switch is used...

Page 338: ... a word transfer instruction They cannot be written to with a byte or longword transfer instruction When writing to WTCNT perform the transfer with the upper byte set to H 5A and the lower byte containing the write data When writing to WTCSR perform the transfer with the upper byte set to H A5 and the lower byte containing the write data This transfer procedure writes the lower byte data to WTCNT ...

Page 339: ... 5 When the WDT count overflows the CPG starts clock supply and the processor resumes operation The WOVF flag in the WTCSR register is not set at this time 6 The counter stops at a value of H 00 H 01 The value at which the counter stops depends on the clock ratio 10 9 2 Frequency Changing Procedure The WDT is used in a frequency change using the PLL It is not used when the frequency is changed sim...

Page 340: ...o the counter periodically so that it does not overflow 4 When the counter overflows the WDT sets the WOVF flag in the WTCSR register to 1 and generates a reset of the type specified by the RSTS bit The counter then continues counting 10 9 4 Using Interval Timer Mode When the WDT is operating in interval timer mode an interval timer interrupt is generated each time the counter overflows This enabl...

Page 341: ...rfering with correct oscillation ensure that no other signal lines cross the signal lines for these pins EXTAL XTAL SH7751 SH7751R CL1 CL2 R Avoid crossing signal lines Recommended values CL1 CL2 0 33 pF R 0 Ω Note The values for CL1 CL2 and the damping resistance should be determined after consultation with the crystal resonator manufacturer Figure 10 4 Points for Attention when Using Crystal Res...

Page 342: ... VDD and VSS lines at the board power supply source and insert resistors RCB and RB and decoupling capacitors CPB and CB close to the pins VDD PLL1 CPB1 CPB2 CB RCB1 Recommended values RCB1 RCB2 10 Ω CPB1 CPB2 10 μF RB 10 Ω CB 10 μF RCB2 RB Power Supply VDD Power Supply VDDQ VSS PLL1 VDD PLL2 SH7751 SH7751R VSS PLL2 VDD CPG VSS CPG Figure 10 5 Points for Attention when Using PLL Oscillator Circuit...

Page 343: ...T IT and RSTS bits in WTCSR 2 Before the counter WTCNT is incremented by the clock specified by the WTCSR CKS bit 3 The value of at least one of the TME WT IT and RSTS bits in WTCSR is 0 4 A value of 1 is written to the TME WT IT and RSTS bits in WTCSR Workaround A workaround for this problem is to use software to increment WTCNT before writing 1 to the TME WT IT and RSTS bits in WTCSR Specific li...

Page 344: ...Section 10 Clock Oscillation Circuits SH7751 Group SH7751R Group Page 290 of 1128 R01UH0457EJ0301 Rev 3 01 Sep 24 2013 ...

Page 345: ... 1 to 64 Hz timer binary display The 64 Hz counter register indicates a state of 64 Hz to 1 Hz within the RTC frequency divider Start stop function 30 second adjustment function Alarm interrupts Comparison with second minute hour day of week day month or year SH7751R only can be selected as the alarm interrupt condition Periodic interrupts An interrupt period of 1 256 second 1 64 second 1 16 secon...

Page 346: ...CCLK 16 384 kHz 32 768 kHz 128 Hz ATI PRI CUI RCR1 RCR2 RCR3 RYRCNT RYRAR RMONCNT RWKCNT RDAYCNT RHRCNT RMINCNT RSECCNT RSECAR RMINAR RHRAR RDAYAR RWKAR RMONAR Prescaler RTC crystal oscillation circuit RTC operation control unit RESET STBY etc Counter unit Interrupt control unit To registers Bus interface Internal peripheral module bus Note SH7751R only Figure 11 1 Block Diagram of RTC ...

Page 347: ...TC RTC oscillation circuit GND pin Note Power must be supplied to the RTC power supply pins even when the RTC is not used 11 1 4 Register Configuration Table 11 2 summarizes the RTC registers Table 11 2 RTC Registers Initialization Name Abbrevia tion R W Power On Reset Manual Reset Standby Mode Initial Value P4 Address Area 7 Address Access Size 64 Hz counter R64CNT R Counts Counts Counts Undefine...

Page 348: ...28 H 1FC80028 8 Day of week alarm register RWKAR R W Initialized 1 Held Held Undefined 1 H FFC8002C H 1FC8002C 8 Day alarm register RDAYAR R W Initialized 1 Held Held Undefined 1 H FFC80030 H 1FC80030 8 Month alarm register RMONAR R W Initialized 1 Held Held Undefined 1 H FFC80034 H 1FC80034 8 RTC control register 1 RCR1 R W Initialized Initialized Held H 00 3 H FFC80038 H 1FC80038 8 RTC control r...

Page 349: ... the simultaneous occurrence of the carry and the 64 Hz counter read In this case the read value is not valid and so R64CNT must be read again after first writing 0 to the CF bit in RCR1 to clear it When the RESET bit or ADJ bit in RTC control register 2 RCR2 is set to 1 the RTC frequency divider is initialized and R64CNT is initialized to H 00 R64CNT is not initialized by a power on or manual res...

Page 350: ...ys be 0 Bit 7 6 5 4 3 2 1 0 10 second units 1 second units Initial value 0 Undefined Undefined Undefined Undefined Undefined Undefined Undefined R W R R W R W R W R W R W R W R W 11 2 3 Minute Counter RMINCNT RMINCNT is an 8 bit readable writable register used as a counter for setting and counting the BCD coded minute value in the RTC It counts on the carry generated once per minute by the second ...

Page 351: ...uld always be 0 Bit 7 6 5 4 3 2 1 0 10 hour units 1 hour units Initial value 0 0 Undefined Undefined Undefined Undefined Undefined Undefined R W R R R W R W R W R W R W R W 11 2 5 Day of Week Counter RWKCNT RWKCNT is an 8 bit readable writable register used as a counter for setting and counting the BCD coded day of week value in the RTC It counts on the carry generated once per day by the hour cou...

Page 352: ...year so care is required when making the setting Taking the year counter RYRCNT value as the year leap year calculation is performed according to whether or not the value is divisible by 400 100 and 4 Bits 7 and 6 are always read as 0 A write to these bits is invalid but the write value should always be 0 Bit 7 6 5 4 3 2 1 0 10 day units 1 day units Initial value 0 0 Undefined Undefined Undefined ...

Page 353: ...counts on the carry generated once per year by the month counter The setting range is decimal 0000 to 9999 The RTC will not operate normally if any other value is set Write processing should be performed after stopping the count with the START bit in RCR2 or by using the carry flag RYRCNT is not initialized by a power on or manual reset or in standby mode Bit 15 14 13 12 11 10 9 8 1000 year units ...

Page 354: ...0 ENB 10 second units 1 second units Initial value 0 Undefined Undefined Undefined Undefined Undefined Undefined Undefined R W R W R W R W R W R W R W R W R W 11 2 10 Minute Alarm Register RMINAR RMINAR is an 8 bit readable writable register used as an alarm register for the RTC s BCD coded minute value counter RMINCNT When the ENB bit is set to 1 the RMINAR value is compared with the RMINCNT valu...

Page 355: ...t or in standby mode Bit 6 is always read as 0 A write to this bit is invalid but the write value should always be 0 Bit 7 6 5 4 3 2 1 0 ENB 10 hour units 1 hour units Initial value 0 0 Undefined Undefined Undefined Undefined Undefined Undefined R W R W R R W R W R W R W R W R W 11 2 12 Day of Week Alarm Register RWKAR RWKAR is an 8 bit readable writable register used as an alarm register for the ...

Page 356: ...n the counter and the alarm register is performed for those registers among RSECAR RMINAR RHRAR RWKAR RDAYAR and RMONAR in which the ENB bit is set to 1 and the RCR1 alarm flag is set when the respective values all match The setting range is decimal 01 to 31 ENB bit The RTC will not operate normally if any other value is set The setting range for RDAYAR depends on the month and whether the year is...

Page 357: ... RMONAR is initialized by a power on reset The other fields in RMONAR are not initialized by a power on or manual reset or in standby mode Bits 6 and 5 are always read as 0 A write to these bits is invalid but the write value should always be 0 Bit 7 6 5 4 3 2 1 0 ENB 10 month unit 1 month units Initial value 0 0 0 Undefined Undefined Undefined Undefined Undefined R W R W R R R W R W R W R W R W 1...

Page 358: ... or 64 Hz counter carry when 64 Hz counter is read Setting conditions Generation of a second counter carry or a 64 Hz counter carry when the 64 Hz counter is read When 1 is written to CF Bit 4 Carry Interrupt Enable Flag CIE Enables or disables interrupt generation when the carry flag CF is set to 1 Bit 4 CIE Description 0 Carry interrupt is not generated when CF flag is set to 1 Initial value 1 C...

Page 359: ...ng 1 does not change the value Bits 6 5 2 and 1 Reserved The initial value of these bits is undefined A write to these bits is invalid but the write value should always be 0 11 2 16 RTC Control Register 2 RCR2 RCR2 is an 8 bit readable writable register used for periodic interrupt control 30 second adjustment and frequency divider RESET and RTC count control RCR2 is basically initialized to H 09 b...

Page 360: ...eriodic Interrupt Enable PES2 PES0 These bits specify the period for periodic interrupts Bit 6 PES2 Bit 5 PES1 Bit 4 PES0 Description 0 0 0 No periodic interrupt generation Initial value 1 Periodic interrupt generated at 1 256 second intervals 1 0 Periodic interrupt generated at 1 64 second intervals 1 Periodic interrupt generated at 1 16 second intervals 1 0 0 Periodic interrupt generated at 1 4 ...

Page 361: ...ormed Bit 1 Reset RESET The frequency divider circuits are initialized by writing 1 to this bit When 1 is written to the RESET bit the frequency divider circuits RTC prescaler and R64CNT are reset and the RESET bit is automatically cleared to 0 i e does not need to be written with 0 Bit 1 RESET Description 0 Normal clock operation Initial value 1 Frequency divider circuits are reset Bit 0 Start Bi...

Page 362: ...ting range of RYRAR is decimal 0000 to 9999 and normal operation is not obtained if a value beyond this range is set here RCR3 is initialized by a power on reset but RYRAR will not be initialized by a power on or manual reset or by the device entering standby mode Bits 6 to 0 of RCR3 are always read as 0 A write to these bits is invalid If a value is written to these bits it should always be 0 RCR...

Page 363: ...ET to 1 Clear RCR2 START to 0 In any order Set RCR2 START to 1 a Setting time after stopping clock Clear carry flag Write to counter register Carry flag 1 No Yes Clear RCR1 CF to 0 Write 1 to RCR1 AF so that alarm flag is not cleared Set RYRCNT first and RSECCNT last Read RCR1 register and check CF bit b Setting time while clock is running Figure 11 2 Examples of Time Setting Procedures The proced...

Page 364: ... for modifying only certain counter values for example only the second data or hour data If a carry occurs during the write operation the write data is automatically updated and there will be an error in the set data The carry flag should therefore be used to check the write status If the carry flag RCR1 CF is set to 1 the write must be repeated The interrupt function can also be used to determine...

Page 365: ...ster and check CF bit a Reading time without using interrupts No Yes Clear carry flag Enable carry interrupts Clear carry flag Read counter register Interrupt generated Yes Disable carry interrupts No b Reading time using interrupts Set RCR1 CIE to 1 Clear RCR1 CF to 0 Write 1 to RCR1 AF so that alarm flag is not cleared Clear RCR1 CIE to 0 Figure 11 3 Examples of Time Reading Procedures If a carr...

Page 366: ...f Use of Alarm Function An alarm can be generated by the second minute hour day of week day month or year SH7751R only value or a combination of these Write 1 to the ENB bit in the alarm registers involved in the alarm setting and set the alarm time in the lower bits Write 0 to the ENB bit in registers not involved in the alarm setting When the counter and the alarm time match RCR1 AF is set to 1 ...

Page 367: ... carry interrupt enable bit CIE is also set to 1 11 5 Usage Notes 11 5 1 Register Initialization After powering on and making the RCR1 register settings reset the frequency divider by setting RCR2 RESET to 1 and make initial settings for all the other registers 11 5 2 Carry Flag and Interrupt Flag in Standby Mode When the carry flag or interrupt flag is set to 1 at the same time this LSI transits ...

Page 368: ... Take care when using a solid earth board 4 The crystal oscillation stabilization time depends on the mounted circuit constants floating capacitance etc and should be decided after consultation with the crystal resonator manufacturer 5 Place the crystal resonator and load capacitors Cin and Cout as close as possible to the chip Correct oscillation may not be possible if there is externally induced...

Page 369: ...er provided for each channel Selection of seven counter input clocks for channels 0 to 2 External clock TCLK on chip RTC output clock five internal clocks Pck 4 Pck 16 Pck 64 Pck 256 Pck 1024 Pck is the peripheral module clock Selection of five internal clocks for channels 3 and 4 Channels 0 to 2 can also operate in module standby mode when the on chip RTC output clock is selected as the counter i...

Page 370: ...with 1 4 1 16 and 1 64 the Pck frequency supplied to the on chip peripheral functions Counter unit Interrupt control unit Counter unit Interrupt control unit Counter unit Interrupt control unit Ch 0 1 Ch 2 Ch 3 4 TMU operation control unit Prescaler TCLK control unit To chan nels 0 to 4 To chan nels 0 to 2 Figure 12 1 Block Diagram of TMU 12 1 3 Pin Configuration Table 12 1 shows the TMU pins Tabl...

Page 371: ...d H FFFFFFFF H FFD80008 H 1FD80008 32 Timer counter 0 TCNT0 R W Ini tialized Ini tialized Held 2 H FFFFFFFF H FFD8000C H 1FD8000C 32 Timer control register 0 TCR0 R W Ini tialized Ini tialized Held H 0000 H FFD80010 H 1FD80010 16 1 Timer constant register 1 TCOR1 R W Ini tialized Ini tialized Held H FFFFFFFF H FFD80014 H 1FD80014 32 Timer counter 1 TCNT1 R W Ini tialized Ini tialized Held 2 H FFFF...

Page 372: ...FFFFFFF H FE100018 H 1E100018 32 Timer control register 4 TCR4 R W Ini tialized Held Held H 0000 H FE10001C H 1E10001C 16 Notes 1 Not initialized in module standby mode when the input clock is the on chip RTC output clock 2 Counts in module standby mode when the input clock is the on chip RTC output clock 12 2 Register Descriptions 12 2 1 Timer Output Control Register TOCR TOCR is an 8 bit readabl...

Page 373: ...s an 8 bit readable writable register that specifies whether the channel 0 2 timer counters TCNT are operated or stopped TSTR is initialized to H 00 by a power on or manual reset In module standby mode TSTR is not initialized when the input clock selected by each channel is the on chip RTC output clock RTCCLK and is initialized only when the input clock is the external clock TCLK or internal clock...

Page 374: ...le register that specifies whether the channel 3 and 4 timer counters TCNT are operated or stopped TSTR2 is initialized to H 00 by a power on reset TSTR retain their contents in standby mode When standby mode is entered when the value of either STR3 or STR4 is 1 the count halts when the peripheral module clock stops and restarts when the clock supply is resumed Bit 7 6 5 4 3 2 1 0 STR4 STR3 Initia...

Page 375: ...tents in standby mode The TCOR registers in channels 3 and 4 are initialized to H FFFFFFFF by a power on reset but are not initialized and retain their contents by a manual reset or in standby mode Bit 31 30 29 2 1 0 Initial value 1 1 1 1 1 1 R W R W R W R W R W R W R W 12 2 5 Timer Counters TCNT The TCNT registers are 32 bit readable writable registers There are five TCNT registers one for each c...

Page 376: ...k TCNT contents are retained in standby mode 12 2 6 Timer Control Registers TCR The TCR registers are 16 bit readable writable registers There are five TCR registers one for each channel Each TCR selects the count clock specifies the edge when an external clock is selected in channels 0 to 2 and controls interrupt generation when the flag indicating timer counter TCNT underflow is set to 1 TCR2 is...

Page 377: ... 0 R W R R R W R W R W R W R W R W 2 Channel 2 TCR bit configuration Bit 15 14 13 12 11 10 9 8 ICPF UNF Initial value 0 0 0 0 0 0 0 0 R W R R R R R R R W R W Bit 7 6 5 4 3 2 1 0 ICPE1 ICPE0 UNIE CKEG1 CKEG0 TPSC2 TPSC1 TPSC0 Initial value 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W 3 Channel 3 and 4 TCR bit configuration Bit 15 14 13 12 11 10 9 8 UNF Initial value 0 0 0 0 0 0 0 0 R W R R R...

Page 378: ...us flag that indicates the occurrence of underflow Bit 8 UNF Description 0 TCNT has not underflowed Initial value Clearing condition When 0 is written to UNF 1 TCNT has underflowed Setting condition When TCNT underflows Note Writing 1 does not change the value Bits 7 and 6 Input Capture Control ICPE1 ICPE0 Channel 2 Only These bits provided in channel 2 only specify whether the input capture funct...

Page 379: ...in the event of input capture 1 Input capture function is used and interrupt due to input capture TICPI2 is enabled Data transfer request is sent to DMAC in the event of input capture Bit 5 Underflow Interrupt Control UNIE Controls enabling or disabling of interrupt generation when the UNF status flag is set to 1 indicating TCNT underflow Bit 5 UNIE Description 0 Interrupt due to underflow TUNI is...

Page 380: ... Pck 64 1 Counts on Pck 256 1 0 0 Counts on Pck 1024 1 Reserved Do not set 1 0 Counts on on chip RTC output clock Do not set in channels 3 and 4 1 Counts on external clock Do not set in channels 3 and 4 12 2 7 Input Capture Register 2 TCPR2 TCPR2 is a 32 bit read only register for use with the input capture function provided only in channel 2 The input capture function is controlled by means of th...

Page 381: ...terrupt request is sent to the CPU At the same time the value is copied from TCOR into TCNT and the count down continues auto reload function Example of Count Operation Setting Procedure Figure 12 2 shows an example of the count operation setting procedure 1 Select the count clock with bits TPSC2 TPSC0 in the timer control register TCR When an external clock in channels 0 to 2 is selected set the ...

Page 382: ...nput capture function is used 3 4 5 6 Input capture interrupt generation setting Timer constant register setting Set initial timer counter value Start count Note When an interrupt is generated clear the source flag in the interrupt handler If the interrupt enabled state is set without clearing the flag another interrupt will be generated Figure 12 2 Example of Count Operation Setting Procedure ...

Page 383: ...alue set in TCNT on underflow Time Figure 12 3 TCNT Auto Reload Operation TCNT Count Timing Operating on internal clock Any of five count clocks Pck 4 Pck 16 Pck 64 Pck 256 or Pck 1024 scaled from the peripheral module clock can be selected as the count clock by means of the TPSC2 TPSC0 bits in TCR Figure 12 4 shows the timing in this case Pck Internal clock TCNT N 1 N N 1 Figure 12 4 Count Timing...

Page 384: ...o 2 the on chip RTC output clock can be selected as the timer clock by means of the TPSC2 TPSC0 bits in TCR Figure 12 6 shows the timing in this case N 1 N N 1 RTC output clock TCNT Figure 12 6 Count Timing when Operating on On Chip RTC Output Clock 12 3 2 Input Capture Function Channel 2 has an input capture function The procedure for using the input capture function is as follows 1 Use the TCOE ...

Page 385: ...on cannot be used in standby mode When input capture occurs the TCNT2 value is set in TCPR2 only when the ICPF bit in TCR2 is 0 Also a new DMAC transfer request is not generated until processing of the previous request is finished Figure 12 7 shows the operation timing when the input capture function is used with TCLK rising edge detection TCOR H 00000000 TCLK TCPR2 TICPI2 TCNT value TCOR value se...

Page 386: ...ICPE0 in TCR2 are 11 The TMU interrupt sources are summarized in table 12 3 Table 12 3 TMU Interrupt Sources Channel Interrupt Source Description 0 TUNI0 Underflow interrupt 0 1 TUNI1 Underflow interrupt 1 2 TUNI2 Underflow interrupt 2 TICPI2 Input capture interrupt 2 3 TUNI3 Underflow interrupt 3 4 TUNI4 Underflow interrupt 4 12 5 Usage Notes 12 5 1 Register Writes When performing a TMU register ...

Page 387: ...a timer count operation and register read processing are performed simultaneously the TCNT counter value prior to the count down operation is read by means of the synchronization processing 12 5 3 Resetting the RTC Frequency Divider When the on chip RTC output clock is selected as the count clock the RTC frequency divider should be reset 12 5 4 External Clock Frequency Ensure that the external clo...

Page 388: ...Section 12 Timer Unit TMU SH7751 Group SH7751R Group Page 334 of 1128 R01UH0457EJ0301 Rev 3 01 Sep 24 2013 ...

Page 389: ...s 0 to 6 Bus width of each area can be set in a register except area 0 which uses an external pin setting Wait state insertion by RDY pin Wait state insertion can be controlled by program Specification of types of memory connectable to each area Output the control signals of memory to each area Automatic wait cycle insertion to prevent data bus collisions in case of consecutive memory accesses to ...

Page 390: ... ROM interface Wait state insertion can be controlled by program Burst operation executing the number of transfers set in a register Connectable areas 0 5 6 Settable bus widths 32 16 8 MPX interface Address data multiplexing Connectable areas 0 to 6 Settable bus widths 32 Byte control SRAM interface SRAM interface with byte control Connectable areas 1 4 Settable bus widths 32 16 PCMCIA interface W...

Page 391: ...TCOR RTCSR Comparator Refresh control unit Memory control unit Area control unit Wait control unit Interrupt controller BSC Peripheral bus Legend WCR Wait control register BCR Bus control register MCR Memory control register PCR PCMCIA control register Note SH7751R only WCR2 WCR3 BCR1 BCR2 BCR3 BCR4 PCR RFCR MCR RDY Module bus RFCR Refresh count register RTCNT Refresh timer count register RTCOR Re...

Page 392: ...t direction designation signal Also used as the DRAM synchronous DRAM PCMCIA interface write designation signal Row address strobe RAS O RAS signal when setting DRAM synchronous DRAM interface Read column address strobe cycle frame RD CASS FRAME O Strobe signal that indicates a read cycle When setting synchronous DRAM interface CAS signal When setting MPX interface FRAME signal Data enable 0 WE0 R...

Page 393: ... signal for D31 D24 Ready RDY I Wait state request signal Area 0 MPX interface specification 16 bit I O MD6 IOIS16 I In power on reset Designates area 0 bus as MPX interface 1 SRAM 0 MPX When setting PCMCIA interface 16 bit I O designation signal Valid only in little endian mode Clock enable CKE O Synchronous DRAM clock enable control signal Bus release request BREQ BSACK I Bus release request sig...

Page 394: ...H 3FFC H FF80 0004 H 1F80 0004 16 Bus control register 3 2 BCR3 R W H 0001 H FF80 0050 H 1F80 0050 16 Bus control register 4 2 BCR4 R W H 0000 0000 H FE0A 00F0 H 1E0A 00F0 32 Wait state control register 1 WCR1 R W H 7777 7777 H FF80 0008 H 1F80 0008 32 Wait state control register 2 WCR2 R W H FFFE EFFF H FF80 000C H 1F80 000C 32 Wait state control register 3 WCR3 R W H 0777 7777 H FF80 0010 H 1F80...

Page 395: ...ronous DRAM is connected to area 2 or 3 signals such as RAS CAS RD WR and DQM are also asserted When the PCMCIA interface is selected for area 5 or 6 CE2A CE2B is asserted in addition to CS5 CS6 for the byte to be accessed H 0000 0000 H 8000 0000 H A000 0000 H C000 0000 H E000 0000 H FFFF FFFF H E400 0000 H 0000 0000 H 0400 0000 H 0800 0000 H 0C00 0000 H 1000 0000 H 1400 0000 H 1800 0000 H 1FFF FF...

Page 396: ...2 2 3 DRAM 16 32 2 3 H 0C000000 H 0FFFFFFF MPX 32 2 8 16 32 64 6 bits 32 bytes 4 64 Mbytes SRAM 8 16 32 2 MPX 32 2 H 10000000 H 13FFFFFF Byte control RAM 16 32 2 8 16 32 64 6 bits 32 bytes 5 64 Mbytes SRAM 8 16 32 2 MPX 32 2 Burst ROM 8 16 32 2 H 14000000 H 17FFFFFF PCMCIA 8 16 2 4 8 16 32 64 6 bits 32 bytes 6 64 Mbytes SRAM 8 16 32 2 MPX 32 2 Burst ROM 8 16 32 2 H 18000000 H 1BFFFFFF PCMCIA 8 16 ...

Page 397: ...erface is for memory and I O card use Figure 13 3 External Memory Space Allocation Memory Bus Width In this LSI the memory bus width can be set independently for each space For area 0 a bus size of 8 16 or 32 bits can be selected in a power on reset by means of the RESET pin using external pins The relationship between the external pins MD4 and MD3 and the bus width in a power on reset is shown be...

Page 398: ...erved space and must not be used 13 1 6 PCMCIA Support This LSI supports PCMCIA interface specifications for external memory space areas 5 and 6 The interfaces supported are the IC memory card interface and I O card interface stipulated in JEIDA specifications version 4 2 PCMCIA2 1 External memory space areas 5 and 6 support both the IC memory card interface and the I O card interface The PCMCIA i...

Page 399: ... enable OE I Output enable RD 10 A11 I Address A11 I Address A11 11 A9 I Address A9 I Address A9 12 A8 I Address A8 I Address A8 13 A13 I Address A13 I Address A13 14 A14 I Address A14 I Address A14 15 WE PGM I Write enable WE PGM I Write enable WE1 16 RDY BSY O Ready busy IREQ O Interrupt request Sensed on port 17 VCC Operating power supply VCC Operating power supply 18 VPP1 Programming power sup...

Page 400: ... D11 I O Data D11 38 D12 I O Data D12 I O Data D12 39 D13 I O Data D13 I O Data D13 40 D14 I O Data D14 I O Data D14 41 D15 I O Data D15 I O Data D15 42 CE2 I Card enable CE2 I Card enable CE2A or CE2B 43 RFSH I Refresh request RFSH I Refresh request Output from port 44 RFU Reserved IORD I I O read ICIORD 45 RFU Reserved IOWR I I O write ICIOWR 46 A17 I Address A17 I Address A17 47 A18 I Address A...

Page 401: ...quest RDY 2 60 RFU Reserved INPACK O Input acknowledge 61 REG I Attribute memory space select REG I Attribute memory space select REG 62 BVD2 O Battery voltage detection SPKR O Digital speech signal Sensed on port 63 BVD1 O Battery voltage detection STSCHG O Card status change Sensed on port 64 D8 I O Data D8 I O Data D8 65 D9 I O Data D9 I O Data D9 66 D10 I O Data D10 I O Data D10 67 CD2 O Card ...

Page 402: ... be accessed until register initialization is completed Bit 31 30 29 28 27 26 25 24 ENDIAN MASTER A0MPX DPUP IPUP OPUP Initial value 0 1 0 1 0 1 0 0 0 0 0 R W R R R R R R W R W R W Bit 23 22 21 20 19 18 17 16 A1MBC A4MBC BREQEN MEMMPX DMABST Initial value 0 0 0 0 0 0 0 0 R W R R R W R W R W R R W R W Bit 15 14 13 12 11 10 9 8 HIZMEM HIZCNT A0BST2 A0BST1 A0BST0 A5BST2 A5BST1 A5BST0 Initial value 0 ...

Page 403: ...r slave status of all spaces is determined by this bit MASTER is a read only bit Bit 30 MASTER Description 0 In a power on reset the master slave setting external pin MD7 is high designating master mode for this LSI 1 In a power on reset the master slave setting external pin MD7 is low designating slave mode for this LSI Bit 29 Area 0 Memory Type A0MPX Samples the value of the area 0 memory type s...

Page 404: ...scription 0 Pull up resistor is on for control input pins NMI IRL0 IRL3 BREQ MD6 IOIS16 SLEEP RDY Initial value 1 Pull up resistor is off for control input pins NMI IRL0 IRL3 BREQ MD6 IOIS16 SLEEP RDY Bit 24 Control Output Pin Pull Up Resistor Control OPUP Specifies the pull up resistor status for control output pins A 25 0 BS CSn RD WEn CASn RD WR RAS CE2A CE2B MD5 when high impedance OPUP is ini...

Page 405: ... Initial value 1 External requests and bus requests from PCIC are accepted Bit 17 Area 1 to 6 MPX Bus Specification MEMMPX Sets the MPX interface when areas 1 to 6 are set as SRAM interface or burst ROM interface MEMMPX is initialized by a power on reset Bit 17 MEMMPX Description 0 SRAM interface or burst ROM interface is selected when areas 1 to 6 are set as SRAM interface or burst ROM interface ...

Page 406: ... impedance Hi Z in standby mode and when the bus is released Initial value 1 The A 25 0 BS CSn RD WR CE2A and CE2B signals drive in standby mode Bit 14 High Impedance Control HIZCNT Specifies the state of the RAS and CAS signals in standby mode and when the bus is released Bit 14 HIZCNT Description 0 The RAS WEn CASn DQMn and RD CASS FRAME signals go to high impedance Hi Z in standby mode and when...

Page 407: ...0BST1 Bit 11 A0BST0 Description 0 0 0 Area 0 is accessed as SRAM interface Initial value 1 Area 0 is accessed as burst ROM interface 4 consecutive accesses Can be used with 8 16 or 32 bit bus width 1 0 Area 0 is accessed as burst ROM interface 8 consecutive accesses Can be used with 8 16 or 32 bit bus width 1 Area 0 is accessed as burst ROM interface 16 consecutive accesses Can only be used with 8...

Page 408: ...ption 0 0 0 Area 5 is accessed as SRAM interface Initial value 1 Area 5 is accessed as burst ROM interface 4 consecutive accesses Can be used with 8 16 or 32 bit bus width 1 0 Area 5 is accessed as burst ROM interface 8 consecutive accesses Can be used with 8 16 or 32 bit bus width 1 Area 5 is accessed as burst ROM interface 16 consecutive accesses Can only be used with 8 or 16 bit bus width Do no...

Page 409: ...ion 0 0 0 Area 6 is accessed as SRAM interface Initial value 1 Area 6 is accessed as burst ROM interface 4 consecutive accesses Can be used with 8 16 or 32 bit bus width 1 0 Area 6 is accessed as burst ROM interface 8 consecutive accesses Can be used with 8 16 or 32 bit bus width 1 Area 6 is accessed as burst ROM interface 16 consecutive accesses Can only be used with 8 or 16 bit bus width Do not ...

Page 410: ... 3 is synchronous DRAM interface 1 Areas 2 and 3 are accessed as synchronous DRAM interface 1 0 0 Area 2 is accessed as SRAM interface or MPX interface area 3 is DRAM interface 1 Reserved Cannot be set 1 0 Reserved Cannot be set 1 Reserved Cannot be set Note Selection of SRAM interface or MPX interface is determined by the setting of the MEMMPX bit Bit 0 Area 5 and 6 Bus Type A56PCM Specifies whet...

Page 411: ...accessed until register initialization is completed Bit 15 14 13 12 11 10 9 8 A0SZ1 A0SZ0 A6SZ1 A6SZ0 A5SZ1 A5SZ0 A4SZ1 A4SZ0 Initial value 0 1 0 1 1 1 1 1 1 1 R W R R R W R W R W R W R W R W Bit 7 6 5 4 3 2 1 0 A3SZ1 A3SZ0 A2SZ1 A2SZ0 A1SZ1 A0SZ0 PORTEN Initial value 1 1 1 1 1 1 0 0 R W R W R W R W R W R W R W R W Note These bits sample the values of the external pins that specify the area 0 bus ...

Page 412: ...us width is 8 bits 1 0 Bus width is 16 bits 1 Bus width is 32 bits Initial value 1 0 0 Reserved Setting prohibited 1 Bus width is 8 bits 1 0 Bus width is 16 bits 1 Bus width is 32 bits Bit 1 Reserved This bit is always read as 0 and should only be written with 0 Bit 0 Port Function Enable PORTEN Specifies whether pins AD31 to AD0 are used as a 32 bit port However select PCI disable mode when using...

Page 413: ...ed by a manual reset or in standby mode No external memory space other than area 0 should be accessed before register initialization has been completed Bit 15 14 13 12 11 10 9 8 Bit name MEMMODE A1MPX A4MPX Initial value 0 0 0 0 0 0 0 0 R W R W R W R W R R R R R Bit 7 6 5 4 3 2 1 0 Bit name SDBL Initial value 0 0 0 0 0 0 0 1 R W R R R R R R R R W Bit 15 A1MPX A4MPX Enable MEMMODE Determines whethe...

Page 414: ...4 A1MPX Description 0 SRAM byte control SRAM interface is selected for area 1 Initial value 1 MPX interface is selected for area 1 Bit 13 A4MPX Description 0 SRAM byte control SRAM interface is selected for area 4 Initial value 1 MPX interface is selected for area 4 Bit 0 Burst Length SDBL Sets the burst length when the synchronous DRAM interface is used The burst length setting is only valid when...

Page 415: ...lier than when synchronous input is set ASYNCn 0 see figure 13 4 The timings shown in this section and section 23 Electrical Characteristics are all for the case where synchronous input is set ASYNCn 0 Note With the synchronous input setting ensure that setup and hold times are observed Bit 31 30 29 28 27 26 25 24 Initial value 0 0 0 0 0 0 0 0 R W R R R R R R R R Bit 23 22 21 20 19 18 17 16 Initia...

Page 416: ...orresponding pins Bit 4 0 ASYNCn Description 0 Corresponding pin is synchronous input with respect to CKIO Initial value 1 Asynchronous input with respect to CKIO is enabled for corresponding pin Bit 4 IOIS16 3 DREQ1 2 DREQ0 1 BREQ 0 RDY T1 Tw Tw Twe T2 CKIO RDY RDY BCR4 ASYNC0 0 BCR4 ASYNC0 1 Figure 13 4 Example of RDY Sampling Timing at which BCR4 Is Set Two Wait Cycles Are Inserted by WCR2 ...

Page 417: ...les set in the WCR1 register are inserted automatically if there is a possibility of this kind of data bus collision WCR1 is initialized to H 77777777 by a power on reset but is not initialized by a manual reset or in standby mode Bit 31 30 29 28 27 26 25 24 DMAIW2 DMAIW1 DMAIW0 A6IW2 A6IW1 A6IW0 Initial value 0 1 1 1 0 1 1 1 R W R R W R W R W R R W R W R W Bit 23 22 21 20 19 18 17 16 A5IW2 A5IW1 ...

Page 418: ...access on the same device The DMAIW bits are valid only for DMA single address transfer with DMA dual address transfer inter area idle cycles are inserted Bits 4n 2 to 4n Area n 6 to 0 Inter Cycle Idle Specification AnlW2 AnlW0 These bits specify the number of idle cycles between bus cycles to be inserted when switching from external memory space area n n 6 to 0 to another space or from a read acc...

Page 419: ...erted when device is switched 2 On the MPX interface a WCR1 idle wait may be inserted before an access either read or write to the same area after a write access The specific conditions for idle wait insertion in accesses to the same area are shown below a Synchronous DRAM set to RAS down mode b Synchronous DRAM accessed by on chip DMAC Apart from use under above conditions a and b an idle wait is...

Page 420: ... circuitry WCR2 is initialized to H FFFEEFFF by a power on reset but is not initialized by a manual reset or in standby mode Bit 31 30 29 28 27 26 25 24 A6W2 A6W1 A6W0 A6B2 A6B1 A6B0 A5W2 A5W1 Initial value 1 1 1 1 1 1 1 1 R W R W R W R W R W R W R W R W R W Bit 23 22 21 20 19 18 17 16 A5W0 A5B2 A5B1 A5B0 A4W2 A4W1 A4W0 Initial value 1 1 1 1 1 1 1 0 R W R W R W R W R W R W R W R W R Bit 15 14 13 1...

Page 421: ...Pin 0 0 0 0 Ignored 1 1 Enabled 1 0 2 Enabled 1 3 Enabled 1 0 0 6 Enabled 1 9 Enabled 1 0 12 Enabled 1 15 Initial value Enabled Bits 28 to 26 Area 6 Burst Pitch A6B2 A6B0 These bits specify the number of wait states to be inserted from the second data access onward at the time of setting the burst ROM in a burst transfer Description Burst Cycle Excluding First Cycle Bit 28 A6B2 Bit 27 A6B1 Bit 26 ...

Page 422: ...Pin 0 0 0 0 Ignored 1 1 Enabled 1 0 2 Enabled 1 3 Enabled 1 0 0 6 Enabled 1 9 Enabled 1 0 12 Enabled 1 15 Initial value Enabled Bits 22 to 20 Area 5 Burst Pitch A5B2 A5B0 These bits specify the number of wait states to be inserted from the second data access onward at the time of setting the burst ROM in a burst transfer Description Burst Cycle Excluding First Cycle Bit 22 A5B2 Bit 21 A5B1 Bit 20 ...

Page 423: ...bled 1 15 Initial value Enabled Bits 16 and 12 Reserved These bits are always read as 0 and should only be written with 0 Bits 15 to 13 Area 3 Wait Control A3W2 A3W0 These bits specify the number of wait states to be inserted for area 3 External wait input is only enabled when the SRAM interface or MPX interface is used and is ignored when DRAM or synchronous DRAM is used For the case where an MPX...

Page 424: ...ed 1 16 Inhibited Note Inhibited in RAS down mode Bits 11 to 9 Area 2 Wait Control A2W2 A2W0 These bits specify the number of wait states to be inserted for area 2 External wait input is only enabled when the SRAM interface or MPX interface is used and is ignored when synchronous DRAM is used For the case where an MPX interface setting is made see table 13 7 When SRAM Interface is Set Description ...

Page 425: ...1 5 2 1 0 Inhibited 1 Inhibited Notes 1 External wait input is always ignored 2 Inhibited in RAS down mode Bits 8 to 6 Area 1 Wait Control A1W2 A1W0 These bits specify the number of wait states to be inserted for area 1 For the case where an MPX interface setting is made see table 13 7 Description Bit 8 A1W2 Bit 7 A1W1 Bit 6 A1W0 Inserted Wait States RDY Pin 0 0 0 0 Ignored 1 1 Enabled 1 0 2 Enabl...

Page 426: ... Pin 0 0 0 0 Ignored 1 1 Enabled 1 0 2 Enabled 1 3 Enabled 1 0 0 6 Enabled 1 9 Enabled 1 0 12 Enabled 1 15 Initial value Enabled Bits 2 to 0 Area 0 Burst Pitch A0B2 A0B0 These bits specify the number of wait states to be inserted from the second data access onward at the time of setting the burst ROM in a burst transfer Description Burst Cycle Excluding First Cycle Bit 2 A0B2 Bit 1 A0B1 Bit 0 A0B0...

Page 427: ...of 1128 Sep 24 2013 Table 13 7 When MPX Interface Is Set Areas 0 to 6 Description Inserted Wait States 1st Data AnW2 AnW1 AnW0 Read Write 2nd Data Onward RDY Pin 0 0 0 1 0 0 Enabled 1 1 Enabled 1 0 2 2 Enabled 1 3 3 Enabled 1 0 0 1 0 1 Enabled 1 1 Enabled 1 0 2 2 Enabled 1 3 3 Enabled Note n 6 to 0 ...

Page 428: ... manual reset or in standby mode Bit 31 30 29 28 27 26 25 24 A6S0 A6H1 A6H0 Initial value 0 0 0 0 0 1 1 1 R W R R R R R R W R W R W Bit 23 22 21 20 19 18 17 16 A5S0 A5H1 A5H0 A4RDH A4S0 A4H1 A4H0 Initial value 0 1 1 1 0 1 1 1 R W R R W R W R W R W R W R W R W Bit 15 14 13 12 11 10 9 8 Bit name A3S0 A3H1 A3H0 A2S0 A2H1 A2H0 Initial value 0 1 1 1 0 1 1 1 R W R R W R W R W R R W R W R W Bit 7 6 5 4 3...

Page 429: ...egation of the write strobe When reading they specify the number of cycles to be inserted in the hold time from the data sampling timing Valid only for SRAM interface byte control SRAM interface and burst ROM interface Bit 4n 1 AnH1 Bit 4n AnH0 Waits Inserted in Hold 0 0 0 1 1 1 0 2 1 3 Initial value Note n 6 to 0 Bits 4n 3 Area n 4 or 1 Read Strobe Negate Timing AnRDH Setting Only Possible in the...

Page 430: ...EDOMODE are written in the initialization following a power on reset and should not be modified subsequently When writing to bits RFSH and RMODE the same values should be written to the other bits so that they remain unchanged When using DRAM or synchronous DRAM areas 2 and 3 should not be accessed until register initialization is completed Bit 31 30 29 28 27 26 25 24 RASD MRSET TRC2 TRC1 TRC0 Ini...

Page 431: ...0 Mode Register Set MRSET Set when a synchronous DRAM mode register setting is used See Power On Sequence in section 13 3 5 Synchronous DRAM Interface Bit 30 MRSET Description 0 All bank precharge Initial value 1 Mode register setting Bits 26 to 24 22 and 18 Reserved These bits should only be written with 0 Bits 29 to 27 RAS Precharge Time at End of Refresh TRC2 TRC0 Synchronous DRAM auto and self...

Page 432: ... next bank active command after precharging Note For setting values and the period during which no command is issued see 23 3 3 Bus Timing RAS Precharge Time Bit 21 TPC2 Bit 20 TPC1 Bit 19 TPC0 DRAM Synchronous DRAM 0 0 0 0 1 Initial value 1 1 2 1 0 2 3 1 3 4 1 0 0 4 5 1 5 6 1 0 6 7 1 7 8 Note Inhibited in RAS down mode Bits 17 and 16 RAS CAS Delay RCD1 RCD0 When the DRAM interface is set these bi...

Page 433: ... period set by TPC 2 0 and TRWL 2 0 bits In RAS down mode they specify the time until the next precharge command is issued After a write cycle the next precharge command is not issued for a period of TRWL This setting is valid only when synchronous DRAM interface is set Note For setting values and the period during which no command is issued see 23 3 3 Bus Timing Bit 15 TRWL2 Bit 14 TRWL1 Bit 13 T...

Page 434: ...TRAS2 Bit 11 TRAS1 Bit 10 TRAS0 RAS DRAM Assertion Time Command Interval after Synchronous DRAM Refresh 0 0 0 2 4 TRC Initial value 1 3 5 TRC 1 0 4 6 TRC 1 5 7 TRC 1 0 0 6 8 TRC 1 7 9 TRC 1 0 8 10 TRC 1 9 11 TRC Note TRC Bits 29 to 27 RAS precharge interval at end of refresh Bit 9 Burst Enable BE Specifies whether burst access is performed on DRAM interface In synchronous DRAM access burst access ...

Page 435: ... prohibited 1 32 bits 32 bits Bits 6 to 3 Address Multiplexing AMXEXT AMX2 AMX0 These bits specify address multiplexing for DRAM and synchronous DRAM The address shift value is different for the DRAM interface and the synchronous DRAM interface For DRAM Interface Description Bit 6 AMXEXT Bit 5 AMX2 Bit 4 AMX1 Bit 3 AMX0 DRAM 0 0 0 0 8 bit column address product Initial value 1 9 bit column address...

Page 436: ...3 64M 2M 8 bits 4 4 a 24 23 4 64M 512K 32 bits 4 1 a 22 21 5 64M 1M 32 bits 2 1 a 22 6 0 64M 4M 4 bits 4 8 a 25 24 1 32 256M 4M 16 bits 4 2 a 25 24 7 16M 256K 32 bits 2 1 a 20 Note a x External address not address pin Bit 2 Refresh Control RFSH Specifies refresh control Selects whether refreshing is performed for DRAM and synchronous DRAM When the refresh function is not used the refresh request c...

Page 437: ...freshing is performed when RFSH 1 Initial value 1 Self refreshing is performed when RFSH 1 Bit 0 EDO Mode EDOMODE Used to specify the data sampling timing for data reads when using EDO mode DRAM interface The setting of this bit does not affect the operation timing of memory other than DRAM Set this bit to 1 only when DRAM is used 13 2 9 PCMCIA Control Register PCR The PCMCIA control register PCR ...

Page 438: ...A Wait A6PCW1 A6PCW0 These bits specify the number of waits to be added to the number of waits specified by WCR2 in a low speed PCMCIA wait cycle The setting of these bits is selected when the PCMCIA interface access TC bit is 0 Bit 13 A6PCW1 Bit 12 A6PCW0 Waits Inserted 0 0 0 Initial value 1 15 1 0 30 1 50 Bits 11 to 9 Address OE WE Assertion Delay A5TED2 A5TED0 These bits set the delay time from...

Page 439: ...7 A6TED1 Bit 6 A6TED0 Waits Inserted 0 0 0 0 Initial value 1 1 1 0 2 1 3 1 0 0 6 1 9 1 0 12 1 15 Bits 5 to 3 OE WE Negation Address Delay A5TEH2 A5TEH0 These bits set the address hold delay time from OE WE negation in a write on the connected PCMCIA interface or in an I O card read In the case of a memory card read the address hold delay time from the data sampling timing is set The setting of the...

Page 440: ... 12 1 15 13 2 10 Synchronous DRAM Mode Register SDMR The synchronous DRAM mode register SDMR is a write only virtual 16 bit register that is written to via the synchronous DRAM address bus and sets the mode of the area 2 and area 3 synchronous DRAM Settings for the SDMR register must be made before accessing synchronous DRAM Bit 15 14 13 12 11 10 9 8 Initial value R W W W W W W W W W Bit 7 6 5 4 3...

Page 441: ...y data is written to address H FF940000 address Y H 08C0 value X H FF9408C0 As a result H 0230 is written to the SDMR register The range of value X is H 0000 to H 0FFC The lower 16 bits of the address are set in the synchronous DRAM mode register The burst length is 4 and 8 Setting to SDMR writes into the following addresses in byte size Bus Width Burst length CAS Latency Area 2 Area 3 32 4 1 H FF...

Page 442: ...imer control status register RTCSR is a 16 bit readable writable register that specifies the refresh cycle and whether interrupts are to be generated RTSCR is initialized to H 0000 by a power on reset but is not initialized by a manual reset or in standby mode Bit 15 14 13 12 11 10 9 8 Initial value 0 0 0 0 0 0 0 0 R W Bit 7 6 5 4 3 2 1 0 CMF CMIE CKS2 CKS1 CKS0 OVF OVIE LMTS Initial value 0 0 0 0...

Page 443: ... Interrupt Enable CMIE Controls generation or suppression of an interrupt request when the CMF flag is set to 1 in RTCSR Do not set this bit to 1 when CAS before RAS refreshing or auto refreshing is used Bit 6 CMIE Description 0 Interrupt requests initiated by CMF are disabled Initial value 1 Interrupt requests initiated by CMF are enabled Bits 5 to 3 Clock Select Bits CKS2 CKS0 These bits select ...

Page 444: ...E Controls generation or suppression of an interrupt request when the OVF flag is set to 1 in RTCSR Bit 1 OVIE Description 0 Interrupt requests initiated by OVF are disabled Initial value 1 Interrupt requests initiated by OVF are enabled Bit 0 Refresh Count Overflow Limit Select LMTS Specifies the count limit to be compared with the refresh count indicated by the refresh count register RFCR If the...

Page 445: ...dable writable register that specifies the upper limit of the RTCNT counter The RTCOR register and RTCNT counter values lower 8 bits are constantly compared and when they match the CMF bit is set in the RTCSR register and the RTCNT counter is cleared to 0 If the refresh bit RFSH has been set to 1 in the memory control register MCR and CAS before RAS has been selected as the refresh mode a memory r...

Page 446: ...t 7 6 5 4 3 2 1 0 Initial value 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W 13 2 15 Notes on Accessing Refresh Control Registers When the refresh timer control status register RTCSR refresh timer counter RTCNT refresh time constant register RTCOR and refresh count register RFCR are written to a special code is added to the data to prevent inadvertent rewriting in the event of program runaw...

Page 447: ...2 bit for synchronous DRAM and 8 or 16 bits for the PCMCIA interface Data alignment is carried out according to the data bus width and endian mode of each device Accordingly when the data bus width is narrower than the access size multiple bus cycles are automatically generated to reach the access size In this case access is performed by automatically incrementing addresses to the bus width For ex...

Page 448: ...ignment Operation Data Bus Strobe Signals Access Size Address No D31 D24 D23 D16 D15 D8 D7 D0 WE3 CAS3 DQM3 WE2 CAS2 DQM2 WE1 CAS1 DQM1 WE0 CAS0 DQM0 Byte 4n 1 Data 7 0 Asserted 4n 1 1 Data 7 0 Asserted 4n 2 1 Data 7 0 Asserted 4n 3 1 Data 7 0 Asserted Word 4n 1 Data 15 8 Data 7 0 Asserted Asserted 4n 2 1 Data 15 8 Data 7 0 Asserted Asserted Long word 4n 1 Data 31 24 Data 23 16 Data 15 8 Data 7 0 ...

Page 449: ... D15 D8 D7 D0 WE3 CAS3 DQM3 WE2 CAS2 DQM2 WE1 CAS1 DQM1 WE0 CAS0 DQM0 Byte 2n 1 Data 7 0 Asserted 2n 1 1 Data 7 0 Asserted Word 2n 1 Data 15 8 Data 7 0 Asserted Asserted Long word 4n 1 Data 31 24 Data 23 16 Asserted Asserted 4n 2 2 Data 15 8 Data 7 0 Asserted Asserted Quad word 8n 1 Data 63 56 Data 55 48 Asserted Asserted 8n 2 2 Data 47 40 Data 39 32 Asserted Asserted 8n 4 3 Data 31 24 Data 23 16 ...

Page 450: ...D0 WE3 CAS3 DQM3 WE2 CAS2 DQM2 WE1 CAS1 DQM1 WE0 CAS0 DQM0 Byte n 1 Data 7 0 Asserted Word 2n 1 Data 15 8 Asserted 2n 1 2 Data 7 0 Asserted Long word 4n 1 Data 31 24 Asserted 4n 1 2 Data 23 16 Asserted 4n 2 3 Data 15 8 Asserted 4n 3 4 Data 7 0 Asserted Quad word 8n 1 Data 63 56 Asserted 8n 1 2 Data 55 48 Asserted 8n 2 3 Data 47 40 Asserted 8n 3 4 Data 39 32 Asserted 8n 4 5 Data 31 24 Asserted 8n 5...

Page 451: ...S2 DQM2 WE1 CAS1 DQM1 WE0 CAS0 DQM0 Byte 4n 1 Data 7 0 Asserted 4n 1 1 Data 7 0 Asserted 4n 2 1 Data 7 0 Asserted 4n 3 1 Data 7 0 Asserted Word 4n 1 Data 15 8 Data 7 0 Asserted Asserted 4n 2 1 Data 15 8 Data 7 0 Asserted Asserted Long word 4n 1 Data 31 24 Data 23 16 Data 15 8 Data 7 0 Asserted Asserted Asserted Asserted Quad word 8n 1 Data 31 24 Data 23 16 Data 15 8 Data 7 0 Asserted Asserted Asse...

Page 452: ...16 D15 D8 D7 D0 WE3 CAS3 DQM3 WE2 CAS2 DQM2 WE1 CAS1 DQM1 WE0 CAS0 DQM0 Byte 2n 1 Data 7 0 Asserted 2n 1 1 Data 7 0 Asserted Word 2n 1 Data 15 8 Data 7 0 Asserted Asserted Long word 4n 1 Data 15 8 Data 7 0 Asserted Asserted 4n 2 2 Data 31 24 Data 23 16 Asserted Asserted Quad word 8n 1 Data 15 8 Data 7 0 Asserted Asserted 8n 2 2 Data 31 24 Data 23 16 Asserted Asserted 8n 4 3 Data 47 40 Data 39 32 A...

Page 453: ... D0 WE3 CAS3 DQM3 WE2 CAS2 DQM2 WE1 CAS1 DQM1 WE0 CAS0 DQM0 Byte n 1 Data 7 0 Asserted Word 2n 1 Data 7 0 Asserted 2n 1 2 Data 15 8 Asserted Long word 4n 1 Data 7 0 Asserted 4n 1 2 Data 15 8 Asserted 4n 2 3 Data 23 16 Asserted 4n 3 4 Data 31 24 Asserted Quad word 8n 1 Data 7 0 Asserted 8n 1 2 Data 15 8 Asserted 8n 2 3 Data 23 16 Asserted 8n 3 4 Data 31 24 Asserted 8n 4 5 Data 39 32 Asserted 8n 5 6...

Page 454: ... read write strobe signal address and the CS setup hold time can be set respectively to 0 or 1 and to 0 to 3 cycles using the A0S0 A0H1 and A0H0 bits in the WCR3 register Area 1 For area 1 external address bits 28 to 26 are 001 SRAM MPX and byte control SRAM can be set for this area A bus width of 8 16 or 32 bits can be selected with bits A1SZ1 and A1SZ0 in the BCR2 register When MPX interface is ...

Page 455: ...he read write strobe signal address and CS setup and hold times can be set within a range of 0 1 and 0 3 cycles respectively by means of bit A2S0 and bits A2H1 and A2H0 in the WCR3 register When synchronous DRAM interface is set the RAS and CAS signals RD WR signal and byte control signals DQM0 to DQM3 are asserted and address multiplexing is performed RAS CAS and data timing control and address m...

Page 456: ...iplexing control can be set using the MCR register Area 4 For area 4 physical address bits 28 to 26 are 100 SRAM MPX and byte control SRAM can be set to this area A bus width of 8 16 or 32 bits can be selected with bits A4SZ1 and A4SZ0 in the BCR2 register When MPX interface is set a bus width of 32 bit should be selected with bits A4SZ1 and A4SZ0 in the BCR2 register When byte control SRAM interf...

Page 457: ...s connected the CE1A and CE2A signals the RD signal which can be used as OE and the WE1 WE2 WE3 and WE0 signals which can be used as WE ICIORD ICIOWR and REG respectively are asserted As regards the number of bus cycles from 0 to 15 waits can be selected with bits A5W2 to A5W0 in the WCR2 register In addition any number of waits can be inserted in each bus cycle by means of the external wait pin R...

Page 458: ...ace is connected the CE1B and CE2B signals the RD signal which can be used as OE and the WE1 WE2 WE3 and WE0 signals which can be used as WE ICIORD ICIOWR and REG respectively are asserted As regards the number of bus cycles from 0 to 15 waits can be selected with bits A6W2 to A6W0 in the WCR2 register In addition any number of waits can be inserted in each bus cycle by means of the external wait ...

Page 459: ...o negation period in case of access at minimum pitch There is no access size specification when reading The correct access address is output to the address pins A 25 0 but since there is no access size specification 32 bits are always read in the case of a 32 bit device and 16 bits in the case of a 16 bit device When writing only the WE signal for the byte to be written is asserted For details see...

Page 460: ...up Page 406 of 1128 R01UH0457EJ0301 Rev 3 01 Sep 24 2013 T1 CKIO A25 A0 CSn RD WR RD D31 D0 read WEn D31 D0 write BS T2 RDY DACKn SA IO memory DACKn SA IO memory DACKn DA Legend SA DA Single address DMA Dual address DMA Figure 13 6 Basic Timing of SRAM Interface ...

Page 461: ...7 13 8 and 13 9 show examples of connection to 32 16 and 8 bit data width SRAM A16 A0 CS OE I O7 I O0 WE A18 A2 CSn RD D31 D24 WE3 D23 D16 WE2 D15 D8 WE1 D7 D0 WE0 SH7751 SH7751R 128K 8 bit SRAM A16 A0 CS OE I O7 I O0 WE A16 A0 CS OE I O7 I O0 WE A16 A0 CS OE I O7 I O0 WE Figure 13 7 Example of 32 Bit Data Width SRAM Connection ...

Page 462: ...oup SH7751R Group Page 408 of 1128 R01UH0457EJ0301 Rev 3 01 Sep 24 2013 A16 A0 CS OE I O7 I O0 WE A17 A1 CSn RD D15 D8 WE1 D7 D0 WE0 SH7751 SH7751R 128K 8 bit SRAM A16 A0 CS OE I O7 I O0 WE Figure 13 8 Example of 16 Bit Data Width SRAM Connection ...

Page 463: ... Connection Wait State Control Wait state insertion on the SRAM interface can be controlled by the WCR2 settings If the WCR2 wait specification bits corresponding to a particular area are not zero a software wait is inserted in accordance with that specification For details see section 13 2 6 Wait Control Register 2 WCR2 The specified number of Tw cycles are inserted as wait cycles using the SRAM ...

Page 464: ...H0457EJ0301 Rev 3 01 Sep 24 2013 T1 CKIO A25 A0 CSn RD WR RD D31 D0 read WEn D31 D0 write BS Tw T2 RDY DACKn SA IO memory DACKn SA IO memory DACKn DA Note For DACKn an example is shown where CHCRn AL access level 0 for the DMAC Figure 13 10 SRAM Interface Wait Timing Software Wait Only ...

Page 465: ...it Sampling is performed at the transition from the Tw state to the T2 state therefore the RDY signal has no effect if asserted in the T1 cycle or the first Tw cycle The RDY signal is sampled on the rising edge of the clock T1 CKIO A25 A0 CSn RD WR RD read D31 D0 read WEn write D31 D0 write BS Tw Twe T2 RDY DACKn SA IO memory DACKn SA IO memory DACKn DA Note For DACKn an example is shown where CHC...

Page 466: ...ecified by the setting of the A1RDH and A4RDH bits of the WCR3 register For information about this setting see the description of the WCR3 register When a byte control SRAM setting is made AnRDH should be cleared to 0 TS1 CKIO A25 A0 CSn RD WR RD D31 D0 BS T1 Tw Tw Tw Tw T2 TH1 TH2 TS1 Setup wait WCR3 AnS 0 to 1 Tw Access wait WCR2 AnW 0 to 15 TH1 TH2 Hold wait WCR3 AnH 0 to 3 Note When AnRDH is s...

Page 467: ...CAS 16 bit DRAMs can be connected since CAS is used to control byte access Signals used for connection are CS3 RAS CAS0 to CAS3 and RD WR CAS2 to CAS3 are not used when the data width is 16 bits In addition to normal read and write access modes fast page mode is supported for burst access EDO mode which enables the DRAM access time to be increased is supported A10 A2 RAS CS3 RD WR D31 D16 CAS3 CAS...

Page 468: ...ble 13 14 The address output pins subject to address multiplexing are A17 to A1 The address signals output by pins A25 to A18 are undefined Table 13 14 Relationship between AMXEXT and AMX2 0 Bits and Address Multiplexing Setting External Address Pins AMXEXT AMX2 AMX1 AMX0 Number of Column Address Bits Output Timing A1 A13 A14 A15 A16 A17 0 0 0 0 8 bits Column address A1 A13 A14 A15 A16 A17 Row add...

Page 469: ...r the RAS assert cycle Tc1 the CAS assert cycle and Tc2 the read data latch cycle Tr1 CKIO Address CSn RD WR RAS D31 D0 read CASn D31 D0 write BS Tr2 Tc1 Tc2 Tpc Row Column DACKn SA IO memory DACKn SA IO memory Legend IO DACK device SA Single address DMA transfer DA Dual address DMA transfer The DACK is in the high active setting Note For DACKn an example is shown where CHCRn AL access level 0 for...

Page 470: ...o secure the RAS precharge time can be inserted by means of the TPC bit in MCR giving from 1 to 7 cycles The number of cycles from RAS assertion to CAS assertion can be set to between 2 and 5 by inserting Trw cycles by means of the RCD bit in MCR Also the number of cycles from CAS assertion to the end of the access can be varied between 1 and 16 according to the setting of A3W2 to A3W0 in WCR2 Tr1...

Page 471: ...y means of the burst enable BE bit in MCR The timing for burst access using fast page mode is shown in figure 13 16 If the access size exceeds the set bus width burst access is performed In a 32 byte transfer the first access comprises a longword that includes the data requiring access The remaining accesses are performed on 32 byte boundary data that includes the relevant data In burst transfer w...

Page 472: ...nal is next asserted In this LSI the EDO mode bit EDOMODE in MCR enables either normal access burst access using fast page mode or EDO mode normal access burst access to be selected for DRAM When EDO mode is set BE must be set to 1 in MCR EDO mode normal access is shown in figure 13 17 and burst access in figure 13 18 CAS Negation Period The CAS negation period can be set to 1 or 2 by means of the...

Page 473: ...d also setting RAS down mode specification bit RASD to 1 it is possible to select RAS down mode in which RAS remains asserted after the end of an access When RAS down mode is used if the refresh cycle is longer than the maximum DRAM RAS assert time the refresh cycle must be decreased to or below the maximum value of tRAS In RAS down mode in the event of an access to an address with a different row...

Page 474: ... Tc1 Tc2 Tc1 Tc1 Tpc Row c1 c2 c8 Tc2 Tc2 Tc1 Tc2 CKIO Address CSn RD WR RAS CASn D31 D0 read D31 D0 write BS DACKn SA IO memory DACKn SA IO memory d8 d2 d1 d8 d2 d1 Note For DACKn an example is shown where CHCRn AL access level 0 for the DMAC Figure 13 19 1 DRAM Burst Bus Cycle RAS Down Mode Start Fast Page Mode RCD 0 AnW 0 ...

Page 475: ... Tc2 Tc1 Tc1 Tc2 Tc2 CKIO Address CSn RD WR RAS CASn D31 D0 read D31 D0 write BS DACKn SA IO memory DACKn SA IO memory c1 c2 c8 d1 d1 d2 d8 d2 d8 End of RAS down mode Note For DACKn an example is shown where CHCRn AL access level 0 for the DMAC Figure 13 19 2 DRAM Burst Bus Cycle RAS Down Mode Continuation Fast Page Mode RCD 0 AnW 0 ...

Page 476: ...1 Sep 24 2013 Tpc Tr2 Tc1 Tc2 Tc1 Tc2 Tc2 Tr1 c1 c2 c8 Tc1 Tc1 Tce Tc2 CKIO Address CSn RD WR RAS CASn D31 D0 read BS DACKn SA IO memory d8 d2 d1 Row Note For DACKn an example is shown where CHCRn AL access level 0 for the DMAC Figure 13 19 3 DRAM Burst Bus Cycle RAS Down Mode Start EDO Mode RCD 0 AnW 0 ...

Page 477: ... 2013 Tc2 Tc1 Tc2 Tc1 Tc2 Tc2 Tc1 c1 c2 c8 Tc1 Tnop Tce CKIO Address CSn RD WR RAS CASn D31 D0 read BS DACKn SA IO memory d8 d2 d1 End of RAS down mode Note For DACKn an example is shown where CHCRn AL access level 0 for the DMAC Figure 13 19 4 DRAM Burst Bus Cycle RAS Down Mode Continuation EDO Mode RCD 0 AnW 0 ...

Page 478: ...2 CKS0 setting When the clock is selected by CKS2 CKS0 RTCNT starts counting up from the value at that time The RTCNT value is constantly compared with the RTCOR value and if the two values are the same a refresh request is generated and the BACK pin goes high If this LSI external bus can be used CAS before RAS refreshing is performed At the same time RTCNT is cleared to zero and the count up is r...

Page 479: ... time immediately after the end of the self refreshing can be set by bits TRC2 TRC0 in MCR CAS before RAS refreshing is performed in normal operation in sleep mode and in the case of a manual reset Self refreshing is performed in normal operation in sleep mode in standby mode and in the case of a manual reset When the bus has been released in response to a bus arbitration request or when a transit...

Page 480: ... when DMAC dual address transfer is executed If a refresh request occurs when the bus has been released by the bus arbiter refresh execution is deferred until the bus is acquired If a match between RTCNT and RTCOR occurs while a refresh is waiting to be executed so that a new refresh request is generated the previous refresh request is eliminated In order for refreshing to be performed normally ca...

Page 481: ...essing synchronous DRAM is by burst length 4 burst read write operations 16 byte data transfer is also performed in a single write but DQMn is not asserted when unnecessary data is transferred In the SH7751R an 8 burst length burst read burst write mode is also supported as a synchronous DRAM operating mode The data bus width is 32 bits and the SZ size bits in MCR must be set to 11 Burst enable bi...

Page 482: ...DQM3 A read write is performed for the byte for which the corresponding DQM signal is low When the bus width is 32 bits in big endian mode DQM3 specifies an access to address 4n and DQM0 specifies an access to address 4n 3 In little endian mode DQM3 specifies an access to address 4n 3 and DQM0 specifies an access to address 4n Figure 13 23 shows examples of the connection of 16M 16 bit synchronous...

Page 483: ...le 13 15 Example of Correspondence between LSI and Synchronous DRAM Address Pins 32 Bit Bus Width AMX2 AMX0 000 AMXEXT 0 LSI Address Pin Synchronous DRAM Address Pin RAS Cycle CAS Cycle Function A13 A21 A21 A11 BANK select bank address A12 A20 H L A10 Address precharge setting A11 A19 0 A9 Address A10 A18 0 A8 A9 A17 A9 A7 A8 A16 A8 A6 A7 A15 A7 A5 A6 A14 A6 A4 A5 A13 A5 A3 A4 A12 A4 A2 A3 A11 A3 ...

Page 484: ...e can be extended by setting WCR2 and MCR bits The number of cycles from the ACTV command output cycle Tr to the READ command output cycle Tc1 can be specified by bits RCD1 and RCD0 in MCR with a value of 0 to 3 specifying 2 to 4 cycles respectively In the case of 2 or more cycles a Trw cycle in which an NOP command is issued for the synchronous DRAM is inserted between the Tr cycle and the Tc cyc...

Page 485: ... Tc2 Tc3 Tc4 Td1 Td3 Td2 Td4 CKIO Bank Precharge sel Address CSn RD WR RAS CASS D31 D0 read DQMn BS DACKn SA IO memory CKE H L c5 Td5 Td6 Td8 Td7 Tpc c1 c1 c2 c3 c4 c5 c6 Row Row Row c7 c8 H L Note For DACKn an example is shown where CHCRn AL access level 0 for the DMAC Figure 13 24 Basic Timing for Synchronous DRAM Burst Read ...

Page 486: ...etween 32 byte boundaries Single Read With this LSI as synchronous DRAM is set to burst read burst write mode read data output continues after the required data has been read To prevent data collisions after the required data is read in Td1 empty read cycles Td2 to Td4 are performed and this LSI waits for the end of the synchronous DRAM operation The BS signal is asserted only in Td1 There are 4 b...

Page 487: ...te operation the WRIT command is issued in the Tc1 cycle following the Tr cycle in which the ACTV command is output and 4 cycles later the WRITA command is issued In the write cycle the write data is output at the same time as the write command In the case of the write with auto precharge command precharging of the relevant bank is performed in the synchronous DRAM after completion of the write co...

Page 488: ...ndary data is written in wraparound mode DACK is asserted two cycles before the data write cycle Tr Tc1 Tc2 Tc3 Tc4 Tc5 Tc7 Trw c1 Tc6 CKIO Bank Precharge sel Address CSn DQMn RD WR RAS CASS D31 D0 write BS CKE DACKn SA IO memory c1 c2 c3 c4 c5 c6 c7 c8 Row Row Tc8 Trw1 Tpc Trw1 H L H L c5 Row Note For DACKn an example is shown where CHCRn AL access level 0 for the DMAC Figure 13 26 Basic Timing f...

Page 489: ...nk is performed in the synchronous DRAM after completion of the write command and therefore no command can be issued for the synchronous DRAM until precharging is completed Consequently in addition to the precharge wait cycle Tpc used in a read access cycle Trwl is also added as a wait interval until precharging is started following the write command Issuance of a new command for the same bank is ...

Page 490: ...1 Sep 24 2013 Tr Tc1 Tc2 Tc3 Tc4 Trwl Tpc Trw H L c1 Trwl CKIO Bank Precharge sel Address CSn DQMn RD WR RAS CASS D31 D0 write BS CKE DACKn SA IO memory c1 Row Row Row Note For DACKn an example is shown where CHCRn AL access level 0 for the DMAC Figure 13 27 Basic Timing for Synchronous DRAM Single Write ...

Page 491: ...C2 TPC0 in MCR There is a limit on tRAS the time for placing each bank in the active state If there is no guarantee that there will not be a cache hit and another row address will be accessed within the period in which this value is maintained by program execution it is necessary to set auto refresh and set the refresh cycle to no more than the maximum value of tRAS In this way it is possible to o...

Page 492: ...13 29 or 13 32 In RAS down mode too a PALL command is issued before a refresh cycle or before bus release due to bus arbitration c2 c3 c4 Tr Tc1 Tc2 c1 c6 c7 c8 c5 Tc3 Tc4 Td1 Td2 Td4 Td5 Trw H L c1 H L c5 Td3 Td6 Td8 Td7 CKIO Bank Precharge sel Address CSn DQMn RD WR RAS CASS D31 D0 read BS CKE DACKn SA IO memory Row Row Row Note For DACKn an example is shown where CHCRn AL access level 0 for the...

Page 493: ...3 c2 c3 c4 Tc1 Tc3 Tc4 Td1 c1 c5 c6 c7 c8 Td2 Td3 Td4 Tc2 H L c1 H L c5 Td5 Td6 Td7 Td8 CKIO Bank Precharge sel Address CSn DQMn RD WR RAS CASS D31 D0 read BS CKE DACKn SA IO memory Note For DACKn an example is shown where CHCRn AL access level 0 for the DMAC Figure 13 29 Burst Read Timing RAS Down Same Row Address ...

Page 494: ...2 c3 c4 c5 c6 c7 c8 Tc1 Tc2 Tc3 Td2 Tpc H L H L c1 c5 Tc4 Td1 Td3 Td4 Td5 Td6 Td7 Td8 CKIO Bank Precharge sel Address CSn DQMn RD WR RAS CASS D31 D0 read BS CKE DACKn SA IO memory Row Row Row Note For DACKn an example is shown where CHCRn AL access level 0 for the DMAC Figure 13 30 Burst Read Timing RAS Down Different Row Addresses ...

Page 495: ...24 2013 Tr Tc1 Tc2 Tc3 Tc4 Tc5 Trw H L H L c1 c5 Tc6 Tc7 Tc8 Trwl Trwl CKIO Bank Precharge sel Address CSn DQMn RD WR RAS CASS D31 D0 read BS CKE c1 c2 c3 c4 c5 c6 c7 c8 Row Row Row DACKn SA IO memory Note For DACKn an example is shown where CHCRn AL access level 0 for the DMAC Figure 13 31 Burst Write Timing ...

Page 496: ...D31 D0 write BS CKE c1 c2 c3 c4 c5 c6 DACKn SA IO memory Note c8 c7 Normal write Single address DMA The Tnop cycle is inserted only for SA DMA The DACKn signal is output as indicated by the solid line In the case of a normal write the Tnop cycle is deleted and the DACKn signal is output as indicated by the dotted line For DACKn an example is shown where CHCRn AL access level 0 for the DMAC Figure ...

Page 497: ... Tc1 Tc2 Tc3 Tpc H L H L c1 c5 Tc4 Tc5 Tc6 Tc7 Tc8 Trwl Trwl CKIO Bank Precharge sel Address CSn DQMn RD WR RAS CASS D31 D0 write BS CKE DACKn SA IO memory c1 c2 c3 c4 c5 c6 c7 c8 Row H L Row Row Note For DACKn an example is shown where CHCRn AL access level 0 for the DMAC Figure 13 33 Burst Write Timing Different Row Addresses ...

Page 498: ...til the last but one data latch cycle If a read access is followed by a write access it may be possible to issue a PRE or ACTV command depending on the bank and row address but since the write data is output at the same time as the WRIT command the PRE ACTV and WRIT commands are issued in such a way that one or two empty cycles occur automatically on the data bus Similarly with a read access follo...

Page 499: ...cles in Which Pipelined Access Can Be Used Following Access CPU DMAC Dual DMAC Single Preceding Access Read Write Read Write Read Write CPU Read X X O X O O Write X X O X O O DMAC dual Read X X X X X X Write O O O X O O DMAC single Read O O O X O O Write O O O X O O Legend O Pipelined access possible X Pipelined access not possible ...

Page 500: ...0457EJ0301 Rev 3 01 Sep 24 2013 Tc1_A Tc1_B H L H L H L CKIO Bank Precharge sel Address CSn DQMn RD WR RAS CASS D31 D0 read BS CKE a1 a2 a3 a4 a5 a6 a7 a8 b1 b2 c1_A c5_A c1_B c5_B H L Figure 13 34 Burst Read Cycle for Different Bank and Row Address Following Preceding Burst Read Cycle ...

Page 501: ...RMODE and RFSH bits in MCR then make the CKS2 CKS0 setting last of all When the clock is selected by CKS2 CKS0 RTCNT starts counting up from the value at that time The RTCNT value is constantly compared with the RTCOR value and if the two values are the same a refresh request is generated and an auto refresh is performed At the same time RTCNT is cleared to zero and the count up is restarted Figur...

Page 502: ... 00000000 RTCSR CKS2 0 External bus Refresh request cleared by start of refresh cycle 000 000 RTCNT cleared to 0 when RTCNT RTCOR Auto refresh cycle Time Refresh request Figure 13 35 Auto Refresh Operation TRr2 TRr3 TRr4 TRr5 Trc TRr1 Trc TRrw Trc CKIO CSn RD WR RAS DQMn BS CKE D31 D0 CASS Figure 13 36 Synchronous DRAM Auto Refresh Timing ...

Page 503: ...med at the correct intervals When self refreshing is activated from the state in which auto refreshing is set or when exiting standby mode other than through a power on reset auto refreshing is restarted if RFSH is set to 1 and RMODE is cleared to 0 when self refresh mode is cleared If the transition from clearing of self refresh mode to the start of auto refreshing takes time this time should be ...

Page 504: ... or write back and also between read and write cycles during execution of a TAS instruction and between read and write cycles when DMAC dual address transfer is executed If a refresh request occurs when the bus has been released by the bus arbiter refresh execution is deferred until the bus is acquired If a match between RTCNT and RTCOR occurs while a refresh is waiting to be executed so that a ne...

Page 505: ...04C H FF94004C 2 H FF90008C H FF94008C 3 H FF9000CC H FF9400CC Note SH7751R only The value set in MCR MRSET is used to select whether a precharge all banks command or a mode register setting command is issued The timing for the precharge all banks command is shown in figure 13 38 1 and the timing for the mode register setting command in figure 13 38 2 Before mode register a 200 µs idle time depend...

Page 506: ... the TMw1 cycle by setting MCR MRSET to 1 and performing a write to address H FF900000 X or H FF940000 X Synchronous DRAM mode register setting should be executed once only after power on reset and before synchronous DRAM access and no subsequent changes should be made CKIO Bank Precharge sel Address CSn RD WR RAS CASS D31 D0 CKE TRp1 TRp2 TRp3 TRp4 TMw1 TMw2 TMw3 TMw4 High TMw5 Figure 13 38 1 Syn...

Page 507: ...SH7751R a burst length of either 4 or 8 can be selected by the setting of the SDBL bit of the BCR3 register For more details see the description of the BCR3 register Burst Read Figure 13 39 is the timing chart for burst read operations For the example shown below we assume that two synchronous DRAMs of 512k 16 bits 2 banks are connected and are used with a 32 bit data width and a burst length of 8...

Page 508: ... extended by the settings of the bits in WCR2 and MCR The number of cycles from cycle Tr on which the ACTV command is output to cycle Tc1 on which the READA command is output can be specified by the RCD1 and RCD0 bits in MCR the number of cycles is 2 3 or 4 for the setting value of 1 2 or 3 respectively When two or more cycles are specified the Trw cycle which is for the issuing of NOP commands to...

Page 509: ...n example is shown where CHCRn AL access level 0 for the DMAC Figure 13 39 Basic Timing of a Burst Read from Synchronous DRAM Burst Length 8 In a cycle of access to synchronous DRAM the BS signal is asserted for one clock cycle at the beginning of a bus cycle Data are accessed in the following sequence in the fill operation for a cache miss the data between the 32 bit boundaries that include the m...

Page 510: ...AM and takes place on completion of the write command so no new command that accesses the same bank can be issued until precharging has been completed For this reason the Trwl cycles are added as a period of waiting for precharging to start after the write command has been issued This is additional to the precharge waiting cycle as used in read access The Trwl cycles delay the issuing of new comma...

Page 511: ... 8 16 or 32 with bits A0BST2 A0BST0 A5BST2 A5BST0 or A6BST2 A6BST0 When 16 bit ROM is connected 4 8 or 16 can be set in the same way When 32 bit ROM is connected 4 or 8 can be set RDY pin sampling is always performed when one or more wait states are set The second and subsequent access cycles also comprise two cycles when a burst ROM setting is made and the wait specification is 0 The timing in th...

Page 512: ... 458 of 1128 R01UH0457EJ0301 Rev 3 01 Sep 24 2013 T1 TB1 TB2 TB1 TB2 TB1 TB2 T2 CKIO A25 A5 A4 A0 CSn RD WR RD D31 D0 read BS RDY DACKn SA IO memory Note For DACKn an example is shown where CHCRn AL access level 0 for the DMAC Figure 13 41 Burst ROM Basic Access Timing ...

Page 513: ...301 Rev 3 01 Page 459 of 1128 Sep 24 2013 T1 Twe TB2 TB1 Tw TB2 Tw Tw TB1 TB2 Tw T2 TB1 CKIO A25 A5 A4 A0 CSn RD WR RD D31 D0 read BS RDY DACKn SA IO memory Note For DACKn an example is shown where CHCRn AL access level 0 for the DMAC Figure 13 42 Burst ROM Wait Access Timing ...

Page 514: ...shows an example of PCMCIA card connection to this LSI To enable active insertion of the PCMCIA cards i e insertion or removal while system power is being supplied a 3 state buffer must be connected between this LSI bus interface and the PCMCIA cards As operation in big endian mode is not explicitly stipulated in the JEIDA PCMCIA standard this LSI supports only little endian mode setting and the l...

Page 515: ... CHCRn STC and CHCRn DTC values AnPCW1 AnPCW0 specify the number of wait states to be inserted in a low speed bus cycle a value of 0 15 30 or 50 can be set and this value is added to the number of wait states for insertion specified by WCR2 AnTED2 AnTED0 can be set to a value from 0 to 15 enabling the address CS CE2A CE2B and REG setup times with respect to the RD and WE1 signals to be secured AnT...

Page 516: ...r read data Even Don t care Second 1 0 1 Invalid Upper read data Odd Don t care Write 8 Even Don t care 1 0 0 Invalid Write data Odd Don t care 1 0 1 Invalid Write data 16 Even Don t care First 1 0 0 Invalid Lower write data Even Don t care Second 1 0 1 Invalid Upper write data Odd Don t care 16 Read 8 Even Don t care 1 0 0 Invalid Read data Odd Don t care 0 1 1 Read data Invalid 16 Even Don t car...

Page 517: ...ite data Odd 0 Read 8 Even 1 1 0 0 Invalid Read data Odd 1 First 0 1 1 Ignored Invalid Odd 1 Second 1 0 1 Invalid Read data 16 Even 1 First 0 0 0 Invalid Lower read data Even 1 Second 1 0 1 Invalid Upper read data Odd 1 Write 8 Even 1 1 0 0 Invalid Write data Odd 1 First 0 1 1 Invalid Write data Odd 1 Second 1 0 1 Invalid Write data 16 Even 1 First 0 0 0 Upper write data Lower write data Even 1 Se...

Page 518: ... PGM IORD IOWR IOIS16 WAIT A25 A0 D15 D0 CD1 CD2 CE1 CE2 OE WE PGM WAIT A25 A0 SH7751 SH7751R D15 D0 RD WR CE2B CE2A RD WE1 CE1B CS6 CE1A CS5 ICIORD ICIOWR RDY IOIS16 G DIR D7 D0 D15 D8 G DIR G G G DIR G DIR D7 D0 D15 D8 REG REG REG PC card memory I O PC card memory I O Card detection circuit Card detection circuit Figure 13 44 Example of PCMCIA Interface ...

Page 519: ...shows the basic timing for the PCMCIA memory card interface and figure 13 46 shows the wait timing for the PCMCIA memory card interface CKIO Tpcm1 Tpcm2 A25 A0 CExx RD WR D15 D0 read D15 D0 write RD read WE1 write BS DACKn DA REG Note For DACKn an example is shown where CHCRn AL access level 0 for the DMAC Figure 13 45 Basic Timing for PCMCIA Memory Card Interface ...

Page 520: ...0301 Rev 3 01 Sep 24 2013 CKIO Tpcm0 A25 A0 RD WR CExx REG RD read D15 D0 read D15 D0 write WE1 write BS RDY DACKn DA Tpcm0w Tpcm1 Tpcm1w Tpcm1w Tpcm2 Tpcm2w Note For DACKn an example is shown where CHCRn AL access level 0 for the DMAC Figure 13 46 Wait Timing for PCMCIA Memory Card Interface ...

Page 521: ... 2 1 KB page 1 KB page Common memory 2 Access by CS6 wait controller Figure 13 47 PCMCIA Space Allocation I O Card Interface Timing Figures 13 48 and 13 49 show the timing for the PCMCIA I O card interface When an I O card interface access is made to a PCMCIA card dynamic sizing of the I O bus width is possible using the IOIS16 pin When a 16 bit bus width is set if the IOIS16 signal is high during...

Page 522: ...1128 R01UH0457EJ0301 Rev 3 01 Sep 24 2013 CKIO Tpci1 Tpci2 A25 A0 RD WR CExx ICIORD read D15 D0 read ICIOWR write D15 D0 write BS DACKn DA REG Note For DACKn an example is shown where CHCRn AL access level 0 for the DMAC Figure 13 48 Basic Timing for PCMCIA I O Card Interface ...

Page 523: ...of 1128 Sep 24 2013 CKIO A25 A0 RD WR CExx ICIORD read ICIOWR write DACKn DA D15 D0 read D15 D0 write BS RDY IOIS16 Tpci0 Tpci0w Tpci1 Tpci1w Tpci1w Tpci2 Tpci2w REG Note For DACKn an example is shown where CHCRn AL access level 0 for the DMAC Figure 13 49 Wait Timing for PCMCIA I O Card Interface ...

Page 524: ...3 Tpci Tpci0 Tpci1w Tpci2 Tpci2w Tpci0 Tpci Tpci2 Tpci1w Tpci2w CKIO A25 A1 A0 RD WR IORD WE2 read IOWR WE3 write D15 D0 write D15 D0 read BS IOIS16 CExx REG RDY DACKn DA Note For DACKn an example is shown where CHCRn AL access level 0 for the DMAC Figure 13 50 Dynamic Bus Sizing Timing for PCMCIA I O Card Interface ...

Page 525: ...hase Therefore a negation period does not occur in the case of minimum pitch access The FRAME signal is asserted at the rise of Tm1 and negated when the last data transfer cycle starts in the data phase Therefore an external device for the MPX interface must hold the address information and access size output in the address phase within itself and peripheral function data input output for the data...

Page 526: ...O31 I O0 RDY Figure 13 51 Example of 32 Bit Data Width MPX Connection The MPX interface timing is shown below When the MPX interface is used for areas 1 to 6 a bus size of 32 bit should be specified in BCR2 For wait control waits specified by WCR2 and wait insertion by means of the RDY pin can be used In a read one wait cycle is automatically inserted after address output even if WCR2 is cleared t...

Page 527: ...0457EJ0301 Rev 3 01 Page 473 of 1128 Sep 24 2013 Tm1 CKIO A RD FRAME CSn RD WR D31 D0 BS Tmd1w Tmd1 RDY DACKn DA D0 Note For DACKn an example is shown where CHCRn AL access level 0 for the DMAC Figure 13 52 MPX Interface Timing 1 Single Read Cycle AnW 0 No External Wait ...

Page 528: ...f 1128 R01UH0457EJ0301 Rev 3 01 Sep 24 2013 Tm1 CKIO A RD FRAME CSn RD WR D31 D0 BS Tmd1w Tmd1w Tmd1 RDY DACKn DA D0 Note For DACKn an example is shown where CHCRn AL access level 0 for the DMAC Figure 13 53 MPX Interface Timing 2 Single Read AnW 0 One External Wait Inserted ...

Page 529: ...UH0457EJ0301 Rev 3 01 Page 475 of 1128 Sep 24 2013 Tm1 CKIO A RD FRAME CSn RD WR D31 D0 BS Tmd1 RDY DACKn DA D0 Note For DACKn an example is shown where CHCRn AL access level 0 for the DMAC Figure 13 54 MPX Interface Timing 3 Single Write Cycle AnW 0 No External Wait ...

Page 530: ... 1128 R01UH0457EJ0301 Rev 3 01 Sep 24 2013 Tm1 CKIO A RD FRAME CSn RD WR D31 D0 BS Tmd1w Tmd1w Tmd1 RDY DACKn DA D0 Note For DACKn an example is shown where CHCRn AL access level 0 for the DMAC Figure 13 55 MPX Interface Timing 4 Single Write AnW 1 One External Wait Inserted ...

Page 531: ... of 1128 Sep 24 2013 Tm1 CKIO RD FRAME CSn RD WR D31 D0 BS Tmd1w Tmd1 Tmd2 Tmd3 Tmd4 Tmd5 Tmd6 Tmd7 Tmd8 RDY DACKn DA D2 D3 D4 D6 D7 D8 D5 A D1 Note For DACKn an example is shown where CHCRn AL access level 0 for the DMAC Figure 13 56 MPX Interface Timing 5 Burst Read Cycle AnW 0 No External Wait ...

Page 532: ...301 Rev 3 01 Sep 24 2013 Tm1 CKIO A RD FRAME CSn RD WR D31 D0 BS Tmd1w Tmd1 Tmd2w Tmd2 Tmd3 Tmd7 Tmd8w Tmd8 RDY DACKn DA D7 D8 D2 D3 D1 Note For DACKn an example is shown where CHCRn AL access level 0 for the DMAC Figure 13 57 MPX Interface Timing 6 Burst Read Cycle AnW 0 External Wait Control ...

Page 533: ...479 of 1128 Sep 24 2013 Tm1 CKIO A RD FRAME CSn RD WR D31 D0 BS Tmd1 Tmd2 Tmd3 Tmd4 Tmd5 Tmd6 Tmd7 Tmd8 RDY DACKn DA D1 D2 D3 D4 D5 D6 D7 D8 Note For DACKn an example is shown where CHCRn AL access level 0 for the DMAC Figure 13 58 MPX Interface Timing 7 Burst Write Cycle AnW 0 No External Wait ...

Page 534: ...01 Rev 3 01 Sep 24 2013 D3 D2 Tm1 CKIO A RD FRAME CSn RD WR D31 D0 BS Tmd1w Tmd1 Tmd2w Tmd2 Tmd3 Tmd7 Tmd8w Tmd8 RDY DACKn DA D1 D7 D8 Note For DACKn an example is shown where CHCRn AL access level 0 for the DMAC Figure 13 59 MPX Interface Timing 8 Burst Write Cycle AnW 1 External Wait Control ...

Page 535: ...81 of 1128 Sep 24 2013 Tm1 CKIO A RD FRAME CSn RD WR D31 D0 BS Tmd1w Tmd1 Tmd2 RDY DACKn DA D0 D1 Note For DACKn an example is shown where CHCRn AL access level 0 for the DMAC Figure 13 60 MPX Interface Timing 9 Burst Read Cycle AnW 0 No External Wait Bus Width 32 Bits Transfer Data Size 64 Bits ...

Page 536: ...1 Sep 24 2013 Tm1 CKIO A RD FRAME CSn RD WR D31 D0 BS Tmd1w Tmd1w Tmd1 Tmd2 RDY DACKn DA D0 D1 Note For DACKn an example is shown where CHCRn AL access level 0 for the DMAC Figure 13 61 MPX Interface Timing 10 Burst Read Cycle AnW 0 One External Wait Inserted Bus Width 32 Bits Transfer Data Size 64 Bits ...

Page 537: ... 483 of 1128 Sep 24 2013 Tm1 CKIO A RD FRAME CSn RD WR D31 D0 BS Tmd1 Tmd2 RDY DACKn DA D0 D1 Note For DACKn an example is shown where CHCRn AL access level 0 for the DMAC Figure 13 62 MPX Interface Timing 11 Burst Write Cycle AnW 0 No External Wait Bus Width 32 Bits Transfer Data Size 64 Bits ...

Page 538: ...1 Sep 24 2013 Tm1 CKIO A RD FRAME CSn RD WR D31 D0 BS Tmd1w Tmd1w Tmd1 Tmd2 RDY DACKn DA D0 D1 Note For DACKn an example is shown where CHCRn AL access level 0 for the DMAC Figure 13 63 MPX Interface Timing 12 Burst Write Cycle AnW 1 One External Wait Inserted Bus Width 32 Bits Transfer Data Size 64 Bits ...

Page 539: ...ss only the WE signal for the byte being read is asserted Assertion is synchronized with the fall of the CKIO clock as for the WE signal while negation is synchronized with the rise of the CKIO clock using the same timing as the RD signal 32 byte transfer is performed consecutively for a total of 32 bytes according to the set bus width The first access is performed on the data for which there was ...

Page 540: ...ge 486 of 1128 R01UH0457EJ0301 Rev 3 01 Sep 24 2013 T1 T2 CKIO A25 A0 CSn RD WR RD D31 D0 read BS DACKn SA IO memory DACKn DA RDY WEn Note For DACKn an example is shown where CHCRn AL access level 0 for the DMAC Figure 13 65 Byte Control SRAM Basic Read Cycle No Wait ...

Page 541: ...301 Rev 3 01 Page 487 of 1128 Sep 24 2013 T1 Tw T2 CKIO A25 A0 CSn RD WR RD D31 D0 read BS DACKn SA IO memory DACKn DA RDY WEn Note For DACKn an example is shown where CHCRn AL access level 0 for the DMAC Figure 13 66 Byte Control SRAM Basic Read Cycle One Internal Wait Cycle ...

Page 542: ...UH0457EJ0301 Rev 3 01 Sep 24 2013 T1 Tw Twe T2 CKIO A25 A0 CSn RD WR RD D31 D0 read BS DACKn SA IO memory DACKn DA RDY WEn Note For DACKn an example is shown where CHCRn AL access level 0 for the DMAC Figure 13 67 Byte Control SRAM Basic Read Cycle One Internal Wait One External Wait ...

Page 543: ...ame data buffer and wait cycle insertion is not performed If there is originally space between accesses according to the setting of bits AnIW2 AnIW0 n 0 to 6 in WCR1 the number of idle cycles inserted is the specified number of idle cycles minus the number of empty cycles When bus arbitration is performed the bus is released after waits are inserted between cycles In single address mode DMA transf...

Page 544: ...her device in response to a bus request In slave mode the bus is not held on a constant basis a bus request is issued each time an external bus cycle occurs and the bus is released again at the end of the access Master mode and slave mode can be specified by the external mode pins See appendix C Mode Pin Settings for the external mode pin settings In master mode and slave mode the bus goes to the ...

Page 545: ...the bus is resumed See appendix D Pin Functions for the pin states when the bus is released When a refresh request is generated this LSI performs a refresh operation as soon as the currently executing bus cycle ends However refresh operations are deferred during multiple bus cycles generated because the data bus width is smaller than the access size for example when performing longword access to 8...

Page 546: ... BACK A25 A0 CSn RD WR RD WEn BREQ BSACK BACK BSREQ A25 A0 CSn RD WR RD WEn D31 D0 read Hi Z Hi Z Hi Z Hi Z Hi Z Hi Z Negated within 2 cycles Asserted for at least 2 cycles Slave mode device access Negated within 2 cycles Hi Z Hi Z Hi Z Hi Z Hi Z Master access Master access Slave access Note For the SH7751 refer to the Usage Note in section 13 3 15 Figure 13 69 Arbitration Sequence ...

Page 547: ...trol DMA transfers With DRAM the bus is released after precharging is completed With synchronous DRAM also a precharge command is issued for the active bank and the bus is released after precharging is completed The actual bus release sequence is as follows First the bus use permission signal is asserted in synchronization with the rising edge of the clock The address bus and data bus go to the hi...

Page 548: ...uire the bus the slave device asserts drives low the BSREQ signal in synchronization with the rising edge of the clock The bus use permission BSACK signal is sampled for assertion low level in synchronization with the rising edge of the clock When BSACK assertion is detected the bus control signals are driven at the negated level after two cycles The bus cycle is started at the next rising edge of...

Page 549: ...ble bit only after the master has performed the necessary processing refresh settings etc for exiting self refresh mode 13 3 15 Notes on Usage Refresh Auto refresh operations stop when a transition is made to standby mode hardware standby mode or deep sleep mode If the memory system requires refresh operations set the memory in the self refresh state prior to making the transition to standby mode ...

Page 550: ... be satisfied when setting the synchronous DRAM mode register The DMAC must not be activated until synchronous DRAM mode register setting is completed 1 Register setting for the on chip peripheral modules 2 must not be performed until synchronous DRAM mode register setting is completed 3 Notes 1 If a conflict occurs between synchronous DRAM mode register setting and memory access using the DMAC ne...

Page 551: ... the following features Four channels SH7751 eight channels SH7751R Physical address space Choice of 8 bit 16 bit 32 bit 64 bit or 32 byte transfer data length Maximum of 16 M 16 777 216 transfers Choice of single or dual address mode Single address mode Either the transfer source or the transfer destination external device is accessed by a DACK signal while the other is accessed by address One da...

Page 552: ...est Transfer requests from the SCI SCF and TMU These can be accepted on all channels Auto request A transfer request is generated automatically within the DMAC Channel functions Transfer modes that can be set are different for each channel 1 Normal DMA mode Channel 0 Single or dual address mode External requests are accepted Channel 1 Single or dual address mode External requests are accepted Chan...

Page 553: ...uest queue clear for each channel SH7751R only Request queues can be cleared on a channel by channel basis in either of the following two ways Clearing a request queue by DTR format The request queues of the relevant channel are cleared when it receives DTR SZ 110 DTR ID 00 DTR MD 11 and DTR COUNT 7 4 1 8 Using software to clear the request queue The request queues of the relevant channel are clea...

Page 554: ...ster DMATCRn DMAC transfer count register CHCRn DMAC channel control register Note n 0 to 3 On chip peripheral module Peripheral bus Internal bus DMAC module Count control Register control Activation control Request priority control Bus interface 32B data buffer Bus state controller CH0 CH1 CH2 CH3 Request controller DTR command buffer DDT module SAR0 DAR0 DMATCR0 CHCR0 only External bus BAVL TDAC...

Page 555: ...MA transfer from channel 0 to external device Notification to external device of start of execution DMA transfer end notification DACK0 Output Strobe output to external device of DMA transfer request from channel 0 to external device 1 DMA transfer request DREQ1 Input DMA transfer request input from external device to channel 1 DREQ acceptance confirmation DRAK1 Output Acceptance of request for DM...

Page 556: ...signal TR DREQ1 Input If asserted 2 cycles after BAVL assertion DTR format is sent Only TR asserted DMA request DBREQ and TR asserted simultaneously Direct request to channel 2 DMAC strobe TDACK DACK0 Output Reply strobe signal for external device from DMAC Channel number notification ID 1 0 DRAK1 DACK1 Output Notification of channel number to external device at same time as TDACK output ID 1 DRAK...

Page 557: ...r 1 CHCR1 R W H 00000000 H FFA0001C H 1FA0001C 32 2 DMA source address register 2 SAR2 R W Undefined H FFA00020 H 1FA00020 32 DMA destination address register 2 DAR2 R W Undefined H FFA00024 H 1FA00024 32 DMA transfer count register 2 DMATCR2 R W Undefined H FFA00028 H 1FA00028 32 DMA channel control register 2 CHCR2 R W H 00000000 H FFA0002C H 1FA0002C 32 3 DMA source address register 3 SAR3 R W ...

Page 558: ...ss of a DMA transfer These registers have a counter feedback function and during a DMA transfer they indicate the next source address In single address mode the SAR value is ignored when a device with DACK has been specified as the transfer source Specify a 16 bit 32 bit 64 bit or 32 byte boundary address when performing a 16 bit 32 bit 64 bit or 32 byte data transfer respectively If a different a...

Page 559: ...t 64 bit or 32 byte data transfer respectively If a different address is specified an address error will be detected and the DMAC will halt The initial value of these registers after a power on or manual reset is undefined They retain their values in standby mode sleep mode and deep sleep mode Notes 1 When a 16 bit 32 bit 64 bit or 32 byte boundary address is specified take care with the setting o...

Page 560: ... R W R W R W R W DMA transfer count registers 0 3 DMATCR0 DMATCR3 are 32 bit readable writable registers that specify the transfer count for the corresponding channel byte count word count longword count quadword count or 32 byte count Specifying H 000001 gives a transfer count of 1 while H 000000 gives the maximum setting 16 777 216 16M transfers During DMAC operation the remaining number of tran...

Page 561: ...ear the flag The RL AM AL and DS bits may be absent depending on the channel DMA channel control registers 0 3 CHCR0 CHCR3 are 32 bit readable writable registers that specify the operating mode transfer method etc for each channel Bits 31 28 and 27 24 indicate the source address and destination address respectively these settings are only valid when the transfer involves the CS5 or CS6 space and t...

Page 562: ...1 16 bit attribute memory space Bit 28 Source Address Wait Control Select STC Specifies CS5 or CS6 space wait control for PCMCIA interface area access This bit selects the wait control register in the BSC that performs area 5 and 6 wait cycle control Bit 28 STC Description 0 CS5 space wait cycle selection Initial value Settings of bits A5W2 A5W0 in wait control register 2 WCR2 and bits A5PCW1 A5PC...

Page 563: ...on Address Wait Control Select DTC Specifies CS5 or CS6 space wait cycle control for PCMCIA interface area access This bit selects the wait control register in the BSC that performs area 5 and 6 wait cycle control Bit 24 DTC Description 0 CS5 space wait cycle selection Initial value Settings of bits A5W2 A5W0 in wait control register 2 WCR2 and bits A5PCW1 A5PCW0 A5TED2 A5TED0 and A5TEH2 A5TEH0 in...

Page 564: ... 1 Bit 18 Request Check Level RL Selects whether the DRAK signal that notifies an external device of the acceptance of DREQ is an active high or active low output In normal DMA mode this bit is valid only in CHCR0 and CHCR1 It is invalid in DDT mode Bit 18 RL Description 0 DRAK is an active high output Initial value 1 DRAK is an active low output Bit 17 Acknowledge Mode AM In dual address mode sel...

Page 565: ...nation address incremented 1 in 8 bit transfer 2 in 16 bit transfer 4 in 32 bit transfer 8 in 64 bit transfer 32 in 32 byte burst transfer 1 0 Destination address decremented 1 in 8 bit transfer 2 in 16 bit transfer 4 in 32 bit transfer 8 in 64 bit transfer 32 in 32 byte burst transfer 1 Setting prohibited Bits 13 and 12 Source Address Mode 1 and 0 SM1 SM0 These bits specify incrementing decrement...

Page 566: ...ule external address space 2 1 Setting prohibited 1 0 0 0 SCI transmit data empty interrupt transfer request external address space SCTDR1 2 1 SCI receive data full interrupt transfer request SCRDR1 external address space 2 1 0 SCIF transmit data empty interrupt transfer request external address space SCFTDR2 2 1 SCIF receive data full interrupt transfer request SCFRDR2 external address space 2 1 ...

Page 567: ...reated as a register access size Bit 6 TS2 Bit 5 TS1 Bit 4 TS0 Description 0 0 0 Quadword size 64 bit specification Initial value 1 Byte size 8 bit specification 1 0 Word size 16 bit specification 1 Longword size 32 bit specification 1 0 0 32 byte block transfer specification Bit 3 Reserved This bit is always read as 0 and should only be written with 0 Bit 2 Interrupt Enable IE When this bit is se...

Page 568: ...R not completed Initial value Clearing conditions When 0 is written to TE after reading TE 1 In a power on or manual reset and in standby mode 1 Number of transfers specified in DMATCR completed Bit 0 DMAC Enable DE Enables operation of the corresponding channel Bit 0 DE Description 0 Operation of corresponding channel is disabled Initial value 1 Operation of corresponding channel is enabled When ...

Page 569: ...The AE and NMIF bits can only be written with 0 after being read as 1 to clear the flags DMAOR is a 32 bit readable writable register that specifies the DMAC transfer mode DMAOR is initialized to H 00000000 by a power on or manual reset They retain their values in standby mode and deep sleep mode Bits 31 to 16 Reserved These bits are always read as 0 and should only be written with 0 Bit 15 On Dem...

Page 570: ... transfer transfers on all channels are suspended and an interrupt request DMAE is generated The CPU cannot write 1 to AE This bit can only be cleared by writing 0 after reading 1 Bit 2 AE Description 0 No address error DMA transfer enabled Initial value Clearing condition When 0 is written to AE after reading AE 1 1 Address error DMA transfer disabled Setting condition When an address error is ca...

Page 571: ...e steal mode can be selected as the bus mode 14 3 1 DMA Transfer Procedure After the desired transfer conditions have been set in the DMA source address register SAR DMA destination address register DAR DMA transfer count register DMATCR DMA channel control register CHCR and DMA operation register DMAOR the DMAC transfers data according to the following procedure 1 The DMAC checks to see if transf...

Page 572: ...UH0457EJ0301 Rev 3 01 Sep 24 2013 Figure 14 2 shows a flowchart of this procedure Note If a transfer request is issued while transfer is disabled the transfer enable wait state transfer suspended state is entered Transfer is started when subsequently enabled by setting DE 1 DME 1 TE 0 NMIF 0 AE 0 ...

Page 573: ...r DME 0 End of transfer Normal end NMIF or AE 1 or DE 0 or DME 0 Bus mode transfer request mode DREQ detection method Transfer suspended 4 2 3 No No Yes Yes Yes No No No Yes Yes No Yes Notes 1 In auto request mode transfer begins when the NMIF AE and TE bits are all 0 and the DE and DME bits are set to 1 2 DREQ level detection external request in burst mode or cycle steal mode 3 DREQ edge detectio...

Page 574: ...C to automatically generate a transfer request signal internally When the DE bit in CHCR0 CHCR3 and the DME bit in the DMA operation register DMAOR are set to 1 the transfer begins so long as the TE bit in CHCR0 CHCR3 and the NMIF and AE bits in DMAOR are all 0 External Request Mode In this mode a transfer is performed in response to a transfer request signal DREQ from an external device One of th...

Page 575: ...fer is not initiated DMA transfer is started after it is enabled DME 1 DE 1 DMAOR NMIF 0 DMAOR AE 0 CHCR TE 0 2 When DMA transfer is enabled DME 1 DE 1 DMAOR NMIF 0 DMAOR AE 0 CHCR TE 0 if an external request DREQ is input DMA transfer is started 3 An external request DREQ will be ignored if input when CHCR TE 1 DMAOR NMIF 1 DMAOR AE 1 during a power on reset or manual reset in deep sleep mode sta...

Page 576: ...e transfer request is set to TXI transfer request by SCI SCIF transmit data empty interrupt the transfer destination must be the SCI SCIF s transmit data register SCTDR1 SCFTDR2 Table 14 5 Selecting On Chip Peripheral Module Request Mode with RS Bits RS3 RS2 RS1 RS0 DMAC Transfer Request Source DMAC Transfer Request Signal Transfer Source Transfer Destination Bus Mode 1 0 0 0 SCI transmitter SCTDR...

Page 577: ...own in table 14 5 is carried out the signal is discontinued automatically This occurs every transfer in cycle steal mode and in the last transfer in burst mode 14 3 3 Channel Priorities If the DMAC receives simultaneous transfer requests on two or more channels it selects a channel according to a predetermined priority system either in a fixed mode or round robin mode The mode is selected with pri...

Page 578: ...annel 2 are also shifted simultaneously If there is a transfer request for channel 1 only immediately afterward channel 1 is given the lowest priority and the priorities of channels 3 and 0 are simultaneously shifted down Transfer on channel 3 Initial priority order Priority order after transfer No change in priority order CH0 CH1 CH2 CH3 CH3 CH0 CH1 CH2 CH2 CH3 CH0 CH1 CH0 CH1 CH2 CH3 CH0 CH1 CH2...

Page 579: ...the channel 1 transfer is started channel 3 is on transfer standby 6 At the end of the channel 1 transfer channel 1 shifts to the lowest priority level 7 The channel 3 transfer is started 8 At the end of the channel 3 transfer the channel 3 and channel 2 priority levels are lowered giving channel 3 the lowest priority 3 1 3 3 Transfer request Channel waiting DMAC operation Channel priority order 1...

Page 580: ...The actual transfer operation timing depends on the bus mode which can be either burst mode or cycle steal mode Table 14 6 Supported DMA Transfers Transfer Destination Transfer Source External Device with DACK External Memory Memory Mapped External Device On Chip Peripheral Module External device with DACK Not available Single address mode Single address mode Not available External memory Single a...

Page 581: ...n external memory and an external device with DACK in which the external device outputs data to the data bus and that data is written to external memory in the same bus cycle DMAC DACK DREQ External memory External device with DACK SH7751 SH7751R External address bus Data flow External data bus Legend Figure 14 5 Data Flow in Single Address Mode Two types of transfer are possible in single address...

Page 582: ...evice with DACK WE signal to external memory space Address output to external memory space Data output from external memory space RD signal to external memory space DACK signal to external device with DACK a From external device with DACK to external memory space b From external memory space to external device with DACK CKIO A28 A0 CSn D63 D0 DACK WE CKIO A28 A0 CSn D63 D0 RD DACK Figure 14 6 DMA ...

Page 583: ...oller BSC In a transfer between external memories such as that shown in figure 14 7 data is read from external memory into the BSC s data buffer in the read cycle then written to the other external memory in the write cycle Figure 14 8 shows the timing for this operation Data buffer Address bus Data bus Address bus Data bus Memory Transfer source module Transfer destination module Memory Transfer ...

Page 584: ... two bus modes cycle steal mode and burst mode selected with the TM bit in CHCR0 CHCR3 Cycle Steal Mode In cycle steal mode the DMAC releases the bus to the CPU at the end of each transfer unit 8 bit 16 bit 32 bit 64 bit or 32 byte transfer When the next transfer request is issued the DMAC reacquires the bus from the CPU and carries out another transfer unit transfer At the end of this transfer th...

Page 585: ...ase by means of BREQ and refresh requests conform to the DMAC burst mode transfer priority specification in bus control register 1 BCRL DMABST With DREQ low level detection in external request mode however when DREQ is driven high the bus passes to another bus master after the end of the DMAC transfer request that has already been accepted even if the transfer end condition has not been satisfied ...

Page 586: ...d external device Internal 1 external 7 B C 8 16 32 64 32B 0 1 2 3 5 6 External memory and on chip peripheral module Internal 2 B C 3 8 16 32 64 4 0 1 2 3 5 6 Memory mapped external device and on chip peripheral module Internal 2 B C 3 8 16 32 64 4 0 1 2 3 5 6 Legend 32B 32 byte burst transfer B Burst C Cycle steal External External request Internal Auto request on chip peripheral module request N...

Page 587: ...Transfer Direction Settable Memory Interface Transfer Source Transfer Destination Address Mode Usable DMAC Channels 1 Synchronous DRAM External device with DACK Single 0 1 2 External device with DACK Synchronous DRAM Single 0 1 3 SRAM type DRAM External device with DACK Single 0 1 4 External device with DACK SRAM type DRAM Single 0 1 5 Synchronous DRAM SRAM type MPX PCMCIA Dual 0 1 6 SRAM type MPX...

Page 588: ...yte control SRAM or burst ROM setting The only memory interface on which single address mode transfer is possible in DDT mode is synchronous DRAM When performing dual address mode transfer make the DACK output setting for the SRAM byte control SRAM burst ROM PCMCIA or MPX interface DACK output setting in dual address mode transfer Bus Mode and Channel Priority Order When for example channel 1 is t...

Page 589: ...ng Timing Number of States in Bus Cycle The number of states in the bus cycle when the DMAC is the bus master is controlled by the bus state controller BSC just as it is when the CPU is the bus master See section 13 Bus State Controller BSC for details DREQ Pin Sampling Timing In external request mode the DREQ pin is sampled at the rising edge of CKIO clock pulses When DREQ input is detected a DMA...

Page 590: ...cycle steal mode single address mode and level detection In this case too transfer is started at the earliest four CKIO cycles after the first DREQ sampling operation The second sampling operation is performed one cycle after the start of the first DMAC transfer bus cycle Figure 14 19 shows the case of cycle steal mode single address mode and edge detection In this case transfer is started at the ...

Page 591: ...fers set in DMATCR DREQ is not sampled during this time and therefore DRAK is output in the first cycle only In the case of dual address mode transfer initiated by an external request the DACK signal can be output in either the read cycle or the write cycle of the DMAC transfer according to the specification of the AM bit in CHCR 5 Burst Mode Single Address Mode Edge Detection In burst mode using ...

Page 592: ...ceptance 2nd acceptance Write Bus locked Source address Destination address Bus locked Destination address CPU CPU DMAC CPU DMAC DRAK0 DREQ1 DREQ0 level detection DACK0 Bus cycle A 25 0 CKIO D 31 0 DREQ sampling and determination of channel priority Legend Figure 14 12 Dual Address Mode Cycle Steal Mode External Bus External Bus DREQ Level Detection DACK Read Cycle ...

Page 593: ...ce 1st acceptance 2nd acceptance Write Bus locked Source address Source address Destination address Bus locked Destination address CPU DMAC CPU DMAC CPU DMAC DRAK0 DREQ1 DREQ0 edge detection DACK0 Bus cycle A 25 0 CKIO D 31 0 DREQ sampling and determination of channel priority Legend Figure 14 13 Dual Address Mode Cycle Steal Mode External Bus External Bus DREQ Edge Detection DACK Read Cycle ...

Page 594: ... acceptance 2nd acceptance Write Bus locked Source address Destination address Bus locked Destination address CPU DMAC 2 CPU DMAC 1 DRAK0 DREQ1 DREQ0 level detection DACK0 Bus cycle A 25 0 CKIO D 31 0 DREQ sampling and determination of channel priority Legend Figure 14 14 Dual Address Mode Burst Mode External Bus External Bus DREQ Level Detection DACK Read Cycle ...

Page 595: ...acceptance Write Bus locked Source address Destination address Bus locked Destination address CPU DMAC 2 CPU DMAC 1 TE bit transfer end DRAK0 DREQ1 DREQ0 edge detection DACK0 Bus cycle A 25 0 CKIO D 31 0 DREQ sampling and determination of channel priority Legend Figure 14 15 Dual Address Mode Burst Mode External Bus External Bus DREQ Edge Detection DACK Read Cycle ...

Page 596: ...eripheral address bus CKIO Source address On chip peripheral data bus Read Read Read D 31 0 Write Write Write Source address Source address A 25 0 Destination address Destination address Destination address CPU CPU DMAC CPU DMAC CPU DMAC Note When Bcyc Pcyc 1 1 Figure 14 16 Dual Address Mode Cycle Steal Mode On Chip SCI Level Detection External Bus ...

Page 597: ...ess Read Read Read D 31 0 Write Write Write Source address Source address A 25 0 Destination address Destination address Destination address CPU DMAC CPU DMAC CPU DMAC T1 T2 T1 T2 T1 T2 On chip peripheral address bus On chip peripheral data bus Note When Bcyc Pcyc 1 1 Figure 14 17 Dual Address Mode Cycle Steal Mode External Bus On Chip SCI Level Detection ...

Page 598: ...U CPU CPU DMAC CPU DMAC DMAC CPU DMAC Source address 2nd acceptance Source address 3rd acceptance Source address 4th acceptance Source address DRAK0 DREQ1 DREQ0 level detection DACK0 Bus cycle A 25 0 CKIO D 31 0 DREQ sampling and determination of channel priority Legend Figure 14 18 Single Address Mode Cycle Steal Mode External Bus External Bus DREQ Level Detection ...

Page 599: ... Read Read Read 3rd acceptance 1st acceptance 2nd acceptance Source address Source address CPU CPU DMAC CPU DMAC CPU DMAC DRAK0 DREQ1 DREQ0 edge detection DACK0 Bus cycle A 25 0 CKIO D 31 0 DREQ sampling and determination of channel priority Legend Figure 14 19 Single Address Mode Cycle Steal Mode External Bus External Bus DREQ Edge Detection ...

Page 600: ...ad 4th acceptance 3rd acceptance 1st acceptance 2nd acceptance Source address Source address Source address CPU DMAC 4 DMAC 2 DMAC 3 CPU DMAC 1 DREQ sampling and determination of channel priority DRAK0 DREQ1 DREQ0 level detection DACK0 Bus cycle A 25 0 CKIO D 31 0 Legend Figure 14 20 Single Address Mode Burst Mode External Bus External Bus DREQ Level Detection ...

Page 601: ...Read Read TE bit transfer end Read Read 1st acceptance Source address Source address Source address CPU DMAC 2 DMAC 4 DMAC 3 CPU DMAC 1 DRAK0 DREQ0 edge detection DACK0 Bus cycle A 25 0 CKIO D 31 0 DREQ sampling and determination of channel priority Legend Figure 14 21 Single Address Mode Burst Mode External Bus External Bus DREQ Edge Detection ...

Page 602: ...acceptance CPU CPU D1 D6 D8 Asserted 2 cycles before start of bus cycle Asserted 2 cycles before start of bus cycle Asserted 2 cycles before start of bus cycle 2nd acceptance 3rd acceptance DMAC 1 DMAC 2 DMAC 3 Destination address Destination address Destination address D1 D6 D8 D1 D6 D7 D8 D7 D7 Legend Figure 14 22 Single Address Mode Burst Mode External Bus External Bus DREQ Level Detection 32 B...

Page 603: ... the DMAC but the timing of stop request DE 0 in CHCR DME 0 in DMAOR sampling is the same as the transfer request sampling timing shown in 4 and 5 under Operation in section 14 3 5 Number of Bus Cycle States and DREQ Pin Sampling Timing Therefore a transfer request is regarded as having been issued until a stop request is detected and the corresponding processing is executed before the DMAC stops ...

Page 604: ... Channels Transfer ends on all channels simultaneously when either of the following conditions is satisfied The address error bit AE or NMI flag NMIF in the DMA operation register DMAOR is set The DMA master enable bit DME in DMAOR is cleared to 0 1 End of transfer when AE 1 in DMAOR If the AE bit in DMAOR is set to 1 due to an address error DMA transfer is suspended on all channels in accordance ...

Page 605: ...from it As in the case of AE being set to 1 acceptance of external requests is suspended while NMIF is set to 1 so a DMA transfer request must be reissued when resuming transfer Acceptance of internal requests is also suspended so when resuming transfer the DMA transfer request enable bit for the relevant on chip peripheral module must be cleared to 0 before the new setting is made 3 End of transf...

Page 606: ...g register settings Table 14 10 Conditions for Transfer between External Memory and an External Device with DACK and Corresponding Register Settings Transfer Conditions Register Set Value Transfer source external memory SAR1 H 0C000000 Transfer source external device with DACK DAR1 Accessed by DACK Number of transfers 32 DMATCR1 H 00000020 Transfer source address decremented CHCR1 H 000022A5 Trans...

Page 607: ... DTR BSC SAR0 DAR0 DMATCR0 CHCR0 DREQ0 3 Data buffer bavl BAVL DBREQ TDACK ID 1 0 ddtmode Data buffer Address bus ddtmode tdack id 1 0 Data bus Request controller TR FIFO or memory Figure 14 23 On Demand Transfer Mode Block Diagram After first making the normal DMA transfer settings for DMAC channels 0 to 3 using the CPU a transfer request is output from an external device using the DBREQ BAVL TR ...

Page 608: ...fied by means of the two ID bits in the DTR command 3 Handshake protocol using the data bus valid for channel 0 only This mode is only valid for channel 0 After the initial settings have been made in the DMAC channel 0 control register the DDT module asserts a data transfer request for the DMAC by setting the DTR command ID 00 MD 00 and SZ 101 110 and driving the DTR command 4 Handshake protocol w...

Page 609: ...ve the data bus released by asserting DBREQ When DBREQ is accepted the BSC asserts BAVL BAVL Data bus D31 D0 release signal Assertion of BAVL means that the data bus will be released two cycles later TR Transfer request signal Assertion of TR has the following different meanings In normal data transfer mode channel 0 except channel 0 TR is asserted and at the same time the DTR format is output two...

Page 610: ...29 27 25 23 26 24 0 Reserved Figure 14 25 Data Transfer Request Format The data transfer request format DTR format consists of 32 bits In the case of normal data transfer mode channel 0 except channel 0 and the handshake protocol using the data bus channel number and transfer request mode are specified Connection is made to D31 through D0 Bits 31 to 29 Transmit Size SZ2 SZ0 000 DTR format selected...

Page 611: ...or channel 0 set DTR ID 00 DTR MD 00 and DTR SZ 101 110 for the DTR format Use the MOV instruction to make settings in the DMAC s SAR0 DAR0 CHCR0 and DMATCR0 registers Either single address mode or dual address mode can be used as the transfer mode Select one of the following settings CHCR0 RS3 RS0 0000 0010 0011 Operation is not guaranteed if the DTR format data settings are DTR ID 00 DTR MD 00 a...

Page 612: ... external device by means of the DTR format ID 01 10 or 11 after making DMAC control register settings in the same way as in normal DMA mode Each of channels 1 to 3 has a request queue that can accept up to four transfer requests When a request queue is full the fifth and subsequent transfer requests will be ignored and so transfer requests must not be output When CHCR TE 1 when a transfer request...

Page 613: ... D31 D0 READ CSn CASn RAS DBREQ BAVL TR TDACK BS RD WR tAD tCSD tAD tCSD Row Row Row tAD c1 H L tRASD tDQMD tCASD2 tCASD2 tRDS tBSD tBSD c1 c2 c4 c3 tDQMD tRDH DMAC Channel tIDD tTDAD tTDAD tIDD tTRS tTRH tBAVD 2CKIO cycles tDTRS 18ns 100MHz DTR 1CKIO cycle 10ns 100MHz tDTRS tDTRH tDBQH tBAVD tRASD Figure 14 26 Single Address Mode Synchronous DRAM External Device Longword Transfer SDRAM Auto Prech...

Page 614: ...AD CSn CASn RAS DBREQ BAVL TR TDACK BS RD WR tAD tCSD tDQMD c1 tBSD tWDD 2CKIO cycles tDTRS 18ns 100MHz DTR 1CKIO cycle 10ns 100MHz tBSD tWDD tRWD tCSD Row Row tRASD Row tAD H L c1 tAD tRASD tCASD2 tCASD2 tRWD tDQMD c4 c3 c2 tDTRS tDTRH tDBQS tDBQH tBAVD tBAVD tTRS tTRH tTDAD DMAC Channel tIDD tIDD tTDAD Figure 14 27 Single Address Mode External Device Synchronous DRAM Longword Transfer SDRAM Auto...

Page 615: ...ANK Precharge sel Addr DQMn ID1 ID0 D31 D0 READ CSn CASn RAS DBREQ BAVL TR TDACK BS RD WR tAD tCSD tAD tCSD Row Row Row tAD c1 H L tRASD tDQMD tCASD2 tCASD2 tRDS tBSD tBSD c1 c2 c4 c3 tDQMD tRDH DMAC Channel tTDAD tTRS tTRH tBAVD 2CKIO cycles tDTRS 18ns 100MHz DTR 1CKIO cycle 10ns 100MHz tDTRS tDTRH tDBQH tBAVD tRASD tTDAD DMAC Channel Figure 14 28 Dual Address Mode Synchronous DRAM SRAM Longword ...

Page 616: ...EQ RA CA D0 D1 D2 D3 RD BA DTR 00 Figure 14 29 Single Address Mode Burst Mode External Bus External Device 32 Byte Block Transfer Channel 0 On Demand Data Transfer RA CA WT BA D0 D1 D2 D3 D4 D5 DTR CKIO ID1 ID0 TDACK RAS CAS WE D31 D0 A25 A0 TR BAVL DBREQ Figure 14 30 Single Address Mode Burst Mode External Device External Bus 32 Byte Block Transfer Channel 0 On Demand Data Transfer ...

Page 617: ...01UH0457EJ0301 Rev 3 01 Page 563 of 1128 Sep 24 2013 RA CA CA CA D1 D0 DTR BA RD RD RD 00 00 CKIO ID1 ID0 TDACK RAS CAS WE D31 D0 A25 A0 TR BAVL DBREQ DQMn Figure 14 31 Single Address Mode Burst Mode External Bus External Device 32 Bit Transfer Channel 0 On Demand Data Transfer ...

Page 618: ...roup Page 564 of 1128 R01UH0457EJ0301 Rev 3 01 Sep 24 2013 RA CA CA D1 D0 DTR BA WT WT CKIO ID1 ID0 TDACK RAS CAS WE D31 D0 A25 A0 TR BAVL DBREQ DQMn Figure 14 32 Single Address Mode Burst Mode External Device External Bus 32 Bit Transfer Channel 0 On Demand Data Transfer ...

Page 619: ...1UH0457EJ0301 Rev 3 01 Page 565 of 1128 Sep 24 2013 CA CA D0 D1 DTR MD 00 D0 D1 D2 D3 WT WT DTR MD 00 Start of data transfer Next transfer request CKIO ID1 ID0 TDACK D31 D0 A25 A0 TR BAVL DBREQ CMD Figure 14 33 Handshake Protocol Using Data Bus Channel 0 On Demand Data Transfer ...

Page 620: ... 566 of 1128 R01UH0457EJ0301 Rev 3 01 Sep 24 2013 CA CA D0 D1 D2 D3 D0 D1 D2 D3 WT WT MD 00 Start of data transfer Next transfer request CKIO ID1 ID0 TDACK DTR D31 D0 A25 A0 TR BAVL DBREQ CMD Figure 14 34 Handshake Protocol without Use of Data Bus Channel 0 On Demand Data Transfer ...

Page 621: ...1128 Sep 24 2013 CKIO DBREQ BAVL TR A25 A0 D31 D0 RAS CAS WE D0 RA CA D1 D2 D3 BA RD Figure 14 35 Read from Synchronous DRAM Precharge Bank CKIO DBREQ BAVL TR A25 A0 D31 D0 RAS CAS WE RA CA D0 D1 D2 D3 PCH BA RD Transfer requests can be accepted Figure 14 36 Read from Synchronous DRAM Non Precharge Bank Row Miss ...

Page 622: ... 568 of 1128 R01UH0457EJ0301 Rev 3 01 Sep 24 2013 CKIO DBREQ BAVL TR A25 A0 D31 D0 RAS CAS WE CA RD D0 D1 D2 D3 Figure 14 37 Read from Synchronous DRAM Row Hit CKIO DBREQ BAVL TR A25 A0 D31 D0 RAS CAS WE RA CA BA WT D0 D1 D2 D3 Figure 14 38 Write to Synchronous DRAM Precharge Bank ...

Page 623: ... 569 of 1128 Sep 24 2013 CKIO DBREQ BAVL TR A25 A0 D31 D0 RAS CAS WE RA CA D0 D1 D2 D3 PCH BA WT Transfer requests can be accepted Figure 14 39 Write to Synchronous DRAM Non Precharge Bank Row Miss CKIO DBREQ BAVL TR A25 A0 D31 D0 RAS CAS WE D0 CA D1 D2 D3 WT Figure 14 40 Write to Synchronous DRAM Row Hit ...

Page 624: ...oup Page 570 of 1128 R01UH0457EJ0301 Rev 3 01 Sep 24 2013 00 D0 D1 D2 RA CA RD BA DTR CKIO ID1 ID0 TDACK RAS CAS WE D31 D0 A25 A0 TR BAVL DBREQ Figure 14 41 Single Address Mode Burst Mode External Bus External Device 32 Byte Block Transfer Channel 0 On Demand Data Transfer ...

Page 625: ...8 2 1 0 DDT PR 1 0 AE NMIF DME Note DDT 0 Normal DMA mode 1 On demand data transfer mode Figure 14 42 DDT Mode Setting DTR CA CA D0 D1 D2 D3 D0 D1 D2 D3 D1 D2 D3 WT WT CKIO ID1 ID0 TDACK CMD D31 D0 A25 A0 TR BAVL DBREQ Start of data transfer No DMA request sampling Figure 14 43 Single Address Mode Burst Mode Edge Detection External Device External Bus Data Transfer ...

Page 626: ...request CKIO ID1 ID0 TDACK CMD D31 D0 A25 A0 TR BAVL DBREQ Figure 14 44 Single Address Mode Burst Mode Level Detection External Bus External Device Data Transfer CA CA CA RD RD RD DTR D0 D3 D2 CKIO ID1 ID0 TDACK DQMn D31 D0 A25 A0 TR BAVL DBREQ CMD Idle cycle Idle cycle Idle cycle Figure 14 45 Single Address Mode Burst Mode Edge Detection Byte Word Longword Quadword External Bus External Device Da...

Page 627: ...01 Rev 3 01 Page 573 of 1128 Sep 24 2013 CA CA CA WT DTR D0 D3 D1 CKIO ID1 ID0 TDACK DQMn D31 D0 A25 A0 TR BAVL DBREQ CMD Idle cycle Idle cycle Idle cycle WT WT Figure 14 46 Single Address Mode Burst Mode Edge Detection Byte Word Longword Quadword External Device External Bus Data Transfer ...

Page 628: ... 574 of 1128 R01UH0457EJ0301 Rev 3 01 Sep 24 2013 DTR ID 1 2 or 3 RA CA BA RD D0 D1 D2 D3 CKIO ID1 ID0 TDACK RAS CAS WE D31 D0 A25 A0 TR BAVL DBREQ 01 or 10 or 11 Figure 14 47 Single Address Mode Burst Mode 32 Byte Block Transfer DMA Transfer Request to Channels 1 3 Using Data Bus ...

Page 629: ...2013 RA CA BA RD 10 D0 D1 D2 D3 D4 D5 D6 D7 CKIO ID1 ID0 TDACK RAS CAS WE D31 D0 A25 A0 TR BAVL DBREQ No DTR cycle so requests can be made at any time Figure 14 48 Single Address Mode Burst Mode 32 Byte Block Transfer External Bus External Device Data Transfer Direct Data Transfer Request to Channel 2 without Using Data Bus ...

Page 630: ...DACK D31 D0 A25 A0 TR BAVL DBREQ CA CA D0 D1 D2 D3 RAS CAS WE D0 D1 D2 D3 D0 D1 D2 3rd 4th 1st 2nd 5th Four requests can be queued Handshaking is necessary to send additional requests No more requests Must be ignored no request transmitted Figure 14 49 Single Address Mode Burst Mode External Bus External Device Data Transfer Direct Data Transfer Request to Channel 2 ...

Page 631: ...D0 TDACK D31 D0 A25 A0 TR BAVL DBREQ CA CA D0 D1 D2 D3 RAS CAS WE D0 D1 D2 D3 3rd 4th 5th Handshaking is necessary to send additional requests Must be ignored no request transmitted D0 D1 D2 D3 WT Four requests can be queued 1st 2nd Figure 14 50 Single Address Mode Burst Mode External Device External Bus Data Transfer Direct Data Transfer Request to Channel 2 ...

Page 632: ... TDACK D31 D0 A25 A0 TR BAVL DBREQ RAS CAS WE D0 D1 D2 D3 D0 D1 D2 D3 D0 D1 D2 3rd 4th 5th Handshaking is necessary to send additional requests Must be ignored no request transmitted Four requests can be queued 1st 2nd Figure 14 51 Single Address Mode Burst Mode External Bus External Device Data Transfer Active Bank Address Direct Data Transfer Request to Channel 2 ...

Page 633: ...D0 A25 A0 TR BAVL DBREQ CA CA D0 D1 D2 D3 RAS CAS WE D0 D1 D2 D3 3rd 4th 5th Handshaking is necessary to send additional requests Must be ignored no request transmitted D0 D1 D2 D3 WT Four requests can be queued 1st 2nd Figure 14 52 Single Address Mode Burst Mode External Device External Bus Data Transfer Active Bank Address Direct Data Transfer Request to Channel 2 ...

Page 634: ...and a DMA transfer request is input when channel 0 DMA transfer has ended and CHCR0 TE 1 the DMAC will freeze Before issuing a DMA transfer request the TE flag must be cleared by writing CHCR0 TE 0 after reading CHCR0 TE 1 4 Handshake protocol without use of the data bus a With the handshake protocol without use of the data bus a DMA transfer request can be input to the DMAC again for the channel ...

Page 635: ...l 0 DMA transfer Therefore if edge detection and burst mode are set for channel 0 transfer cannot be ended midway b When a transfer end request DTR ID 00 MD 00 SZ 111 is accepted the values set in CHCR0 SAR0 DAR0 and DMATCR0 are retained In this case execution cannot be restarted from an external device To restart execution set CHCR0 DE 1 with an MOV instruction 9 Request queue clearance a When se...

Page 636: ...ue to this signal 11 Clearing DDT mode Check that DMA transfer is not in progress on any channel before setting the DMAOR DDT bit If the DMAOR DDT setting is changed from 1 to 0 during DMA transfer in DDT mode the DMAC will freeze This also applies when switching from normal DMA mode DMAOR DDT 0 to DDT mode 12 Confirming DMA transfer requests and number of transfers executed The channel associated...

Page 637: ...odule DDTD External bus TR DBREQ tdack id 2 0 TDACK ID 1 0 D 31 0 DBREQ BAVL ID2 SAR0 7 DAR0 7 DMATCR0 7 CHCR0 7 DMAOR Bus interface Peripheral bus Internal bus DMAC module Count control Registr control Activation control Request priority control 32B data buffer Bus state controller On chip peripheral module External address on chip peripheral module address TMU SCI SCIF DACK0 DACK1 DRAK0 DRAK1 DR...

Page 638: ...equest for DMA transfer from channel 0 to external device Notification to external device of start of execution DMA transfer end notification DACK0 Output Strobe output to external device of DMA transfer request from channel 0 to external device 1 DMA transfer request DREQ1 Input DMA transfer request input from external device to channel 1 DREQ acceptance confirmation DRAK1 Output Acceptance of re...

Page 639: ...TR asserted DMA request DBREQ and TR asserted simultaneously Direct request to channel 2 DMAC strobe TDACK DACK0 Output Reply strobe signal for external device from DMAC Channel number notification ID 1 0 DRAK1 DACK1 Output Notification of channel number to external device at same time as TDACK output ID 1 DRAK1 ID 0 DACK1 Requests for DMA transfer from external devices are normally accepted only ...

Page 640: ...ndefined H FFA00014 H 1FA00014 32 DMA transfer count register 1 DMATCR1 R W Undefined H FFA00018 H 1FA00018 32 1 DMA channel control register 1 CHCR1 R W H 00000000 H FFA0001C H 1FA0001C 32 DMA source address register 2 SAR2 R W Undefined H FFA00020 H 1FA00020 32 DMA destination address register 2 DAR2 R W Undefined H FFA00024 H 1FA00024 32 DMA transfer count register 2 DMATCR2 R W Undefined H FFA...

Page 641: ...MA channel control register 5 CHCR5 R W H 00000000 H FFA0006C H 1FA0006C 32 DMA source address register 6 SAR6 R W Undefined H FFA00070 H 1FA00070 32 DMA destination address register 6 DAR6 R W Undefined H FFA00074 H 1FA00074 32 DMA transfer count register 6 DMATCR6 R W Undefined H FFA00078 H 1FA00078 32 6 DMA channel control register 6 CHCR6 R W H 00000000 H FFA0007C H 1FA0007C 32 DMA source addr...

Page 642: ...address for a DMA transfer The functions of these registers are the same as on the SH7751 For more information see section 14 2 1 DMA Source Address Registers 0 3 SAR0 SAR3 14 7 2 DMA Destination Address Registers 0 7 DAR0 DAR7 Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Initial value R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 ...

Page 643: ...nt Registers 0 3 DMATCR0 DMATCR3 14 7 4 DMA Channel Control Registers 0 7 CHCR0 CHCR7 Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 SSA2 SSA1 SSA0 STC DSA2 DSA1 DSA0 DTC DS RL AM AL Initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W R R R R R W R W R W R W Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DM1 DM0 SM1 SM0 RS3 RS2 RS1 RS0 TM TS2 TS1 TS0 QCL IE TE DE Init...

Page 644: ...se bits specify the space attribute for PCMCIA access These bits are only valid in the case of page mapping to PCMCIA connected to areas 5 and 6 For details of the settings see the description of the DSA2 DSA0 bits in section 14 2 4 DMA Channel Control Registers 0 3 CHCR0 CHCR3 Bit 24 Destination Address Wait Control Select DTC Specifies CS5 or CS6 space wait cycle control for PCMCIA access This b...

Page 645: ...ored when data is transferred from external memory to an external device in single address mode For details of the settings see the description of the DM1 and DM0 bits in section 14 2 4 DMA Channel Control Registers 0 3 CHCR0 CHCR3 Bits 13 and 12 Source Address Mode 1 and 0 SM1 SM0 These bits specify incrementing decrementing of the DMA transfer source address The specification of these bits is ig...

Page 646: ...e number of data transfers specified in DMATCR when TE 1 For details of the settings see the description of the IE bit in section 14 2 4 DMA Channel Control Registers 0 3 CHCR0 CHCR3 Bit 1 Transfer End TE This bit is set to 1 after the number of transfers specified in DMATCR If the IE bit is set to 1 at this time an interrupt request DMTE is generated If data transfer ends before TE is set to 1 fo...

Page 647: ...tain their values in standby mode and deep sleep mode Bits 31 to 16 Reserved These bits are always read as 0 and should only be written with 0 Bit 15 On Demand Data Transfer DDT Specifies on demand data transfer mode For details of the settings see the description of the DDT bit in section 14 2 5 DMA Operation Register DMAOR Bit 14 Number of DDT Mode Channels DBL Selects the number of channels tha...

Page 648: ...ese bits determine the order of priority for channel execution when transfer requests are made for a number of channels simultaneously DMAOR Bit 9 DMAOR Bit 8 PR1 PR0 Description 0 0 CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7 Initial value 0 1 CH0 CH2 CH3 CH4 CH5 CH6 CH7 CH1 1 0 CH2 CH0 CH1 CH3 CH4 CH5 CH6 CH7 1 1 Round robin mode Bits 7 to 3 Reserved These bits are always read as 0 and should only be writte...

Page 649: ...eration SH7751R Operation specific to the SH7751R is described here For details of operation see section 14 3 Operation 14 8 1 Channel Specification for a Normal DMA Transfer In normal DMA transfer mode the DMAC always operates with eight channels and external requests are only accepted on channel 0 DREQ0 and channel 1 DREQ1 After setting the registers of the channels in use including CHCR SAR DAR...

Page 650: ... ID 1 0 bits and the simultaneous on the timing of TDACK assertion assertion of ID2 from the BAVL data bus available pin are used to notify the external device of the DMAC channel that is to be used see table 14 16 Notification of Transfer Channel in Eight Channel DDT Mode When the DMAC is set up for eight channel external request acceptance in DDT mode DMAOR DBL 1 it is important to note that the...

Page 651: ... 00 11 110 Setting prohibited 10 Clear the request queues of all channels 1 7 Clear the CH0 request accepted flag 0001 Clear the CH0 request accepted flag 0010 Clear the CH1 request queues 0011 Clear the CH2 request queues 0100 Clear the CH3 request queues 0101 Clear the CH4 request queues 0110 Clear the CH5 request queues 0111 Clear the CH6 request queues 1 00 11 110 1000 Clear the CH7 request qu...

Page 652: ...er end interrupt H 680 DMTE3 CH3 transfer end interrupt H 6A0 DMTE4 CH4 transfer end interrupt H 780 DMTE5 CH5 transfer end interrupt H 7A0 DMTE6 CH6 transfer end interrupt H 7C0 DMTE7 CH7 transfer end interrupt H 7E0 DMAE Address error interrupt H 6C0 Low DMTE4 DMTE7 These codes are not used in the SH7751 CKIO RA DTR CA D1 D2 RD BA 00 ID1 ID0 TDACK RAS CAS WE D63 D0 A25 A0 TR BAVL ID2 DBREQ D0 Fi...

Page 653: ...UH0457EJ0301 Rev 3 01 Page 599 of 1128 Sep 24 2013 CKIO RA DTR CA D1 D2 RD BA 00 ID1 ID0 TDACK RAS CAS WE D63 D0 A25 A0 TR BAVL ID2 DBREQ D0 Figure 14 56 Single Address Mode Cycle Steal Mode External Bus External Device 32 Byte Block Transfer On Demand Data Transfer on Channel 4 ...

Page 654: ...curred Check the set values in CHCR SAR and DAR 3 Check that DMA transfer is not in progress before making a transition to the module standby state standby mode or deep sleep mode Either check that TE 1 in the SH7751 s CHCR0 CHCR3 or in the SH7751R s CHCR0 CHCR7 or clear DME to 0 in DMAOR to terminate DMA transfer When DME is cleared to 0 in DMAOR transfer halts at the end of the currently executi...

Page 655: ...128 Sep 24 2013 7 When falling edge detection is used for external requests keep the external request pin high when making DMAC settings 8 When using the DMAC in single address mode set an external address as the address All channels will halt due to an address error if an on chip peripheral module address is set ...

Page 656: ...Section 14 Direct Memory Access Controller DMAC SH7751 Group SH7751R Group Page 602 of 1128 R01UH0457EJ0301 Rev 3 01 Sep 24 2013 ...

Page 657: ...ee section 16 Serial Communication Interface with FIFO SCIF 15 1 1 Features SCI features are listed below Choice of synchronous or asynchronous serial communication mode Asynchronous mode Serial data communication is executed using an asynchronous system in which synchronization is achieved character by character Serial data communication can be carried out with standard asynchronous communication...

Page 658: ...reception to be executed simultaneously Double buffering is used in both the transmitter and the receiver enabling continuous transmission and continuous reception of serial data On chip baud rate generator allows any bit rate to be selected Choice of serial clock source internal clock from baud rate generator or external clock from SCK pin Four interrupt sources There are four interrupt sources t...

Page 659: ...y generation Parity check Transmission reception control Baud rate generator Clock External clock Pck Pck 4 Pck 16 Pck 64 TEI TXI RXI ERI SCI Bus interface Internal data bus SCSPTR1 Legend SCRSR1 Receive shift register SCRDR1 Receive data register SCTSR1 Transmit shift register SCTDR1 Transmit data register SCSMR1 Serial mode register SCSCR1 Serial control register SCSSR1 Serial status register SC...

Page 660: ...s mode the data format and the bit rate and to perform transmitter receiver control With the exception of the serial port register the SCI registers are initialized in standby mode and in the module standby state as well as after a power on reset or manual reset When recovering from standby mode or the module standby state the registers must be set again Table 15 2 SCI Registers Name Abbreviation ...

Page 661: ...1 cannot be directly read or written to by the CPU 15 2 2 Receive Data Register SCRDR1 Bit 7 6 5 4 3 2 1 0 Initial value 0 0 0 0 0 0 0 0 R W R R R R R R R R SCRDR1 is the register that stores received serial data When the SCI has received one byte of serial data it transfers the received data from SCRSR1 to SCRDR1 where it is stored and completes the receive operation SCRSR1 is then enabled for re...

Page 662: ...CTSR1 is not performed if the TDRE flag in the serial status register SCSSR1 is set to 1 SCTSR1 cannot be directly read or written to by the CPU 15 2 4 Transmit Data Register SCTDR1 Bit 7 6 5 4 3 2 1 0 Initial value 1 1 1 1 1 1 1 1 R W R W R W R W R W R W R W R W R W SCTDR1 is an 8 bit register that stores data for serial transmission When the SCI detects that SCTSR1 is empty it transfers the tran...

Page 663: ...n to by the CPU at all times SCSMR1 is initialized to H 00 by a power on reset or manual reset in standby mode and in the module standby state Bit 7 Communication Mode C A Selects asynchronous mode or synchronous mode as the SCI operating mode Bit 7 C A Description 0 Asynchronous mode Initial value 1 Synchronous mode Bit 6 Character Length CHR Selects 7 or 8 bits as the data length in asynchronous...

Page 664: ...dition and checking is disabled in asynchronous mode Bit 4 O E Description 0 Even parity 1 Initial value 1 Odd parity 2 Notes 1 When even parity is set parity bit addition is performed in transmission so that the total number of 1 bits in the transmit character plus the parity bit is even In reception a check is performed to see if the total number of 1 bits in the receive character plus the parit...

Page 665: ... Multiprocessor function disabled Initial value 1 Multiprocessor format selected Bits 1 and 0 Clock Select 1 and 0 CKS1 CKS0 These bits select the clock source for the on chip baud rate generator The clock source can be selected from Pck Pck 4 Pck 16 and Pck 64 according to the setting of bits CKS1 and CKS0 For the relation between the clock source the bit rate register setting and the baud rate s...

Page 666: ...bles receive data full interrupt RXI request and receive error interrupt ERI request generation when serial receive data is transferred from SCRSR1 to SCRDR1 and the RDRF flag in SCSSR1 is set to 1 Bit 6 RIE Description 0 Receive data full interrupt RXI request and receive error interrupt ERI request disabled Initial value 1 Receive data full interrupt RXI request and receive error interrupt ERI r...

Page 667: ...he MPIE bit setting is invalid in synchronous mode or when the MP bit is cleared to 0 Bit 3 MPIE Description 0 Multiprocessor interrupts disabled normal reception performed Initial value Clearing conditions When the MPIE bit is cleared to 0 When data with MPB 1 is received 1 Multiprocessor interrupts enabled Note When receive data including MPB 1 is received the MPIE bit is cleared to 0 automatica...

Page 668: ...g the SCI s operating mode with SCSMR1 For details of clock source selection see table 15 9 in section 15 3 Operation Bit 1 CKE1 Bit 0 CKE0 Description 0 0 Asynchronous mode Internal clock SCK pin functions as input pin input signal ignored 1 Synchronous mode Internal clock SCK pin functions as serial clock output 1 1 Asynchronous mode Internal clock SCK pin functions as clock output 2 Synchronous...

Page 669: ...gs they must be read as 1 beforehand The TEND flag and MPB flag are read only flags and cannot be modified SCSSR1 is initialized to H 84 by a power on reset or manual reset in standby mode and in the module standby state Bit 7 Transmit Data Register Empty TDRE Indicates that data has been transferred from SCTDR1 to SCTSR1 and the next serial transmit data can be written to SCTDR1 Bit 7 TDRE Descri...

Page 670: ...is cleared to 0 If reception of the next data is completed while the RDRF flag is still set to 1 an overrun error will occur and the receive data will be lost Bit 5 Overrun Error ORER Indicates that an overrun error occurred during reception causing abnormal termination Bit 5 ORER Description 0 Reception in progress or reception has ended normally 1 Initial value Clearing conditions Power on reset...

Page 671: ...stop bit is not checked If a framing error occurs the receive data is transferred to SCRDR1 but the RDRF flag is not set Serial reception cannot be continued while the FER flag is set to 1 Bit 3 Parity Error PER Indicates that a parity error occurred during reception with parity addition in asynchronous mode causing abnormal termination Bit 3 PER Description 0 Reception in progress or reception ha...

Page 672: ... Bit MPB This bit is read only and cannot be written to The read value is undefined Note This bit is prepared for storing a multi processor bit in the received data when the receipt is carried out with a multi processor format in asynchronous mode however this does not function correctly in this LSI Do not use the read value from this bit Bit 0 Multiprocessor Bit Transfer MPBT When transmission is...

Page 673: ...f bits 2 and 0 is undefined SCSPTR1 is not initialized in the module standby state or standby mode Bit 7 Error Interrupt Only EIO When the EIO bit is 1 an RXI interrupt request is not sent to the CPU even if the RIE bit is set to 1 When the DMAC is used this setting means that only ERI interrupts are handled by the CPU The DMAC transfers read data to memory or another peripheral module This bit sp...

Page 674: ...ecifies the serial port TxD pin output condition When the TxD pin is actually set as a port output pin and outputs the value set by the SPB0DT bit the TE bit in SCSCR1 should be cleared to 0 Bit 1 SPB0IO Description 0 SPB0DT bit value is not output to the TxD pin Initial value 1 SPB0DT bit value is output to the TxD pin Bit 0 Serial Port Break Data SPB0DT Specifies the serial port RxD pin input da...

Page 675: ...ternal data bus SPTRW SPTRW SCI R Q D SPB1IO C R Q D SPB1DT C SPTRR Clock output enable signal Serial clock output signal Serial clock input signal Clock input enable signal SCK Legend SPTRW Write to SPTR SPTRR Read SPTR Note Signals that set the SCK pin function as internal clock output or external clock input according to the CKE0 and CKE1 bits in SCSCR1 and the C A bit in SCSMR1 Figure 15 2 SCK...

Page 676: ...0457EJ0301 Rev 3 01 Sep 24 2013 Reset Internal data bus SPTRW SCI R Q D SPB0IO C Reset SPTRW R Q D SPB0DT C TxD Transmit enable signal Serial transmit data Legend SPTRW Write to SPTR Figure 15 3 TxD Pin Internal data bus SCI RxD SPTRR Serial receive data Legend SPTRR Read SPTR Figure 15 4 RxD Pin ...

Page 677: ... SCBRR1 can be read or written to by the CPU at all times SCBRR1 is initialized to H FF by a power on reset or manual reset in standby mode and in the module standby state The SCBRR1 setting is found from the following equations Asynchronous mode N 106 1 64 22n 1 B Pck Synchronous mode N 106 1 8 22n 1 B Pck Where B Bit rate bits s N SCBRR1 setting for baud rate generator 0 N 255 Pck Peripheral mod...

Page 678: ... of 1128 R01UH0457EJ0301 Rev 3 01 Sep 24 2013 The bit rate error in asynchronous mode is found from the following equation Error 100 Pck 106 N 1 B 64 22n 1 1 Table 15 3 shows sample SCBRR1 settings in asynchronous mode and table 15 4 shows sample SCBRR1 settings in synchronous mode ...

Page 679: ...0 0 12 0 16 0 13 2 48 0 15 0 00 0 19 2 34 9600 0 6 6 99 0 6 2 48 0 7 0 00 0 9 2 34 19200 0 2 8 51 0 2 13 78 0 3 0 00 0 4 2 34 31250 0 1 0 00 0 1 4 86 0 1 22 88 0 2 0 00 38400 0 1 18 62 0 1 14 67 0 1 0 00 Pck MHz 3 6864 4 4 9152 5 Bit Rate bits s n N Error n N Error n N Error n N Error 110 2 64 0 70 2 70 0 03 2 86 0 31 2 88 0 25 150 1 191 0 00 1 207 0 16 1 255 0 00 2 64 0 16 300 1 95 0 00 1 103 0 1...

Page 680: ...4 0 19 0 00 0 23 0 00 0 25 0 16 19200 0 9 2 34 0 9 0 00 0 11 0 00 0 12 0 16 31250 0 5 0 00 0 5 2 40 0 6 5 33 0 7 0 00 38400 0 4 2 34 0 4 0 00 0 5 0 00 0 6 6 99 Pck MHz 9 8304 10 12 12 288 Bit Rate bits s n N Error n N Error n N Error n N Error 110 2 174 0 26 2 177 0 25 2 212 0 03 2 217 0 08 150 2 127 0 00 2 129 0 16 2 155 0 16 2 159 0 00 300 1 255 0 00 2 64 0 16 2 77 0 16 2 79 0 00 600 1 127 0 00 ...

Page 681: ...3 0 00 0 25 0 16 0 31 0 00 0 32 1 36 31250 0 14 1 70 0 15 0 00 0 19 1 70 0 19 0 00 38400 0 11 0 00 0 12 0 16 0 15 0 00 0 15 1 73 Pck MHz 24 24 576 28 7 30 Bit Rate bits s n N Error n N Error n N Error n N Error 110 3 106 0 44 3 108 0 08 3 126 0 31 3 132 0 13 150 3 77 0 16 3 79 0 00 3 92 0 46 3 97 0 35 300 2 155 0 16 2 159 0 00 2 186 0 08 2 194 0 16 600 2 77 0 16 2 79 0 00 2 92 0 46 2 97 0 35 1200 ...

Page 682: ... 223 3 233 1k 1 249 2 124 2 249 3 111 3 116 2 5k 1 99 1 199 2 99 2 178 2 187 5k 0 199 1 99 1 199 2 89 2 93 10k 0 99 0 199 1 99 1 178 1 187 25k 0 39 0 79 0 159 1 71 1 74 50k 0 19 0 39 0 79 0 143 0 149 100k 0 9 0 19 0 39 0 71 0 74 250k 0 3 0 7 0 15 0 29 500k 0 1 0 3 0 7 0 14 1M 0 0 0 1 0 3 2M 0 0 0 1 Legend Blank No setting is available A setting is available but error occurs Notes As far as possibl...

Page 683: ...rates with external clock input Table 15 5 Maximum Bit Rate for Various Frequencies with Baud Rate Generator Asynchronous Mode Settings Pck MHz Maximum Bit Rate bits s n N 2 62500 0 0 2 097152 65536 0 0 2 4576 76800 0 0 3 93750 0 0 3 6864 115200 0 0 4 125000 0 0 4 9152 153600 0 0 8 250000 0 0 9 8304 307200 0 0 12 375000 0 0 14 7456 460800 0 0 16 500000 0 0 19 6608 614400 0 0 20 625000 0 0 24 75000...

Page 684: ...8400 3 0 7500 46875 3 6864 0 9216 57600 4 1 0000 62500 4 9152 1 2288 76800 8 2 0000 125000 9 8304 2 4576 153600 12 3 0000 187500 14 7456 3 6864 230400 16 4 0000 250000 19 6608 4 9152 307200 20 5 0000 312500 24 6 0000 375000 24 576 6 1440 384000 28 7 7 1750 448436 30 7 5000 468750 Table 15 7 Maximum Bit Rate with External Clock Input Synchronous Mode Pck MHz External Input Clock MHz Maximum Bit Rat...

Page 685: ...d addition of 1 or 2 stop bits the combination of these parameters determines the transfer format and character length Detection of framing parity and overrun errors and breaks during reception Choice of internal or external clock as SCI clock source When internal clock is selected The SCI operates on the baud rate generator clock and a clock with the same frequency as the bit rate can be output W...

Page 686: ... Bit 6 CHR Bit 2 MP Bit 5 PE Bit 3 STOP Mode Data Length Multi processor Bit Parity Bit Stop Bit Length 0 1 bit 0 1 No 2 bits 0 1 bit 0 1 1 8 bit data Yes 2 bits 0 1 bit 0 1 No 2 bits 0 1 bit 1 0 1 1 Asynchronous mode 7 bit data No Yes 2 bits 0 No 1 bit 0 1 8 bit data 2 bits 0 1 bit 0 1 1 1 Asynchronous mode multiprocessor format 7 bit data Yes 2 bits 1 Synchronous mode 8 bit data No None Note An ...

Page 687: ... a character by character basis Inside the SCI the transmitter and receiver are independent units enabling full duplex communication Both the transmitter and the receiver also have a double buffered structure so that data can be read or written during transmission or reception enabling continuous data transfer Figure 15 5 shows the general format for asynchronous serial communication In asynchrono...

Page 688: ... bit or none 1 or 2 bits Stop bit s 1 1 0 D0 D1 D2 D3 D4 D5 D6 D7 0 1 1 1 Idle state mark state Start bit 1 bit MSB Transmit receive data Figure 15 5 Data Format in Asynchronous Communication Example with 8 Bit Data Parity Two Stop Bits Data Transfer Format Table 15 10 shows the data transfer formats that can be used in asynchronous mode Any of 12 transfer formats can be selected according to the ...

Page 689: ... PE MP STOP 1 2 3 4 5 6 7 8 9 10 11 12 0 0 0 0 S 8 bit data STOP 0 0 0 1 S 8 bit data STOP STOP 0 1 0 0 S 8 bit data P STOP 0 1 0 1 S 8 bit data P STOP STOP 1 0 0 0 S 7 bit data STOP 1 0 0 1 S 7 bit data STOP STOP 1 1 0 0 S 7 bit data P STOP 1 1 0 1 S 7 bit data P STOP STOP 0 1 0 S 8 bit data MPB STOP 0 1 1 S 8 bit data MPB STOP STOP 1 1 0 S 7 bit data MPB STOP 1 1 1 S 7 bit data MPB STOP STOP Leg...

Page 690: ...he rising edge of the clock is at the center of each transmit data bit as shown in figure 15 6 D0 D1 D2 D3 D4 D5 D6 D7 0 1 1 1 One frame 0 Figure 15 6 Relation between Output Clock and Transfer Data Phase Asynchronous Mode Data Transfer Operations SCI Initialization Asynchronous Mode Before transmitting and receiving data it is necessary to clear the TE and RE bits in SCSCR1 to 0 then initialize t...

Page 691: ...us mode it is output immediately after SCSCR1 settings are made 2 Set the data transfer format in SCSMR1 3 Write a value corresponding to the bit rate into SCBRR1 Not necessary if an external clock is used 4 Wait at least one bit interval then set the TE bit or RE bit in SCSCR1 to 1 Also set the RIE TIE TEIE and MPIE bits Setting the TE and RE bits enables the TxD and RxD pins to be used When tran...

Page 692: ...flag is set to 1 then write transmit data to SCTDR1 and clear the TDRE flag to 0 2 Serial transmission continuation procedure To continue serial transmission read 1 from the TDRE flag to confirm that writing is possible then write data to SCTDR1 and then clear the TDRE flag to 0 Checking and clearing of the TDRE flag is automatic when the direct memory access controller DMAC is activated by a tran...

Page 693: ...order c Parity bit or multiprocessor bit One parity bit even or odd parity or one multiprocessor bit is output A format in which neither a parity bit nor a multiprocessor bit is output can also be selected d Stop bit s One or two 1 bits stop bits are output e Mark state 1 is output continuously until the start bit that starts the next transmission is sent 3 The SCI checks the TDRE flag at the timi...

Page 694: ...ity bit Stop bit TXI interrupt request Data written to SCTDR1 and TDRE flag cleared to 0 by TXI interrupt handler One frame TEI interrupt request TXI interrupt request Figure 15 9 Example of Transmit Operation in Asynchronous Mode Example with 8 Bit Data Parity One Stop Bit Serial Data Reception Asynchronous Mode Figure 15 10 shows a sample flowchart for serial reception Use the following procedur...

Page 695: ...ng the appropriate error handling ensure that the ORER PER and FER flags are all cleared to 0 Reception cannot be resumed if any of these flags are set to 1 In the case of a framing error a break can be detected by reading the value of the RxD pin 2 SCI status check and receive data read Read SCSSR1 and check that RDRF 1 then read the receive data in SCRDR1 and clear the RDRF flag to 0 3 Serial re...

Page 696: ...UH0457EJ0301 Rev 3 01 Sep 24 2013 Error handling ORER 1 FER 1 Break PER 1 End Yes Yes No Yes No No No Yes Clear ORER PER and FER flags in SCSSR1 to 0 Parity error handling Framing error handling Clear RE bit in SCSCR1 to 0 Overrun error handling Figure 15 10 Sample Serial Reception Flowchart 2 ...

Page 697: ...error is detected in the error check the operation is as shown in table 15 11 Note No further receive operations can be performed when a receive error has occurred Also note that the RDRF flag is not set to 1 in reception and so the error flags must be cleared to 0 4 If the EIO bit in SCSPTR1 is cleared to 0 and the RIE bit in SCSCR1 is set to 1 when the RDRF flag changes to 1 a receive data full ...

Page 698: ...multiprocessor communication is carried out each receiving station is addressed by a unique ID code The serial communication cycle consists of two cycles an ID transmission cycle which specifies the receiving station and a data transmission cycle The multiprocessor bit is used to differentiate between the ID transmission cycle and the data transmission cycle The transmitting station first sends th...

Page 699: ...he MPIE bit in SCSCR1 and skips the receive data if the MPIE bit is 1 Skipping of unnecessary data is achieved by collaborative operation with the exception handling routine Transmitting station Receiving station A Receiving station B Receiving station C Receiving station D ID 01 ID 02 ID 03 ID 04 Serial transmission line MPB 1 MPB 0 H 01 H AA Legend MPB Multiprocessor bit Serial data ID transmiss...

Page 700: ...pecified the parity bit specification is invalid For details see table 15 10 Clock See the description under Clock in section 15 3 2 Operation in Asynchronous Mode Data Transfer Operations Multiprocessor Serial Data Transmission Figure 15 13 shows a sample flowchart for multiprocessor serial data transmission Use the following procedure for multiprocessor serial data transmission after enabling th...

Page 701: ...s set to 1 then set the MPBT bit in SCSSR1 to 1 and write ID data to SCTDR1 Finally clear the TDRE flag to 0 2 Preparation for data transfer Read SCSSR1 and check that the TEND flag is set to 1 then set the MPBT bit in SCSSR1 to 1 3 Serial data transmission Write the first transmit data to SCTDR1 then clear the TDRE flag to 0 To continue data transmission be sure to read 1 from the TDRE flag to co...

Page 702: ...1 is output continuously until the start bit that starts the next transmission is sent 3 The SCI checks the TDRE flag at the timing for sending the stop bit If the TDRE flag is set to 1 the TEND flag in SCSSR1 is set to 1 the stop bit is sent and then the line goes to the mark state in which 1 is output If the TEIE bit in SCSCR1 is set to 1 at this time a transmit end interrupt TEI request is gene...

Page 703: ...g receive operation is a multiprocessor interrupt When an interrupt such as RXI occurs during receive operation using the on chip SCI multiprocessor communication function check the state of the MPIE bit in the SCSCR1 register as part of the interrupt handling routine a If the MPIE bit in the SCSCR1 register is set to 1 Ignore the received data Data with the multiprocessor bit MPB set to 0 and int...

Page 704: ...f 1128 R01UH0457EJ0301 Rev 3 01 Sep 24 2013 When using software processing to determine whether received data is ID MPB 1 or data MPB 0 use a procedure such as saving a user defined flag in memory to indicate receive start Figure 15 15 shows a flowchart of a sample software workaround ...

Page 705: ...g to 1 End of ID reception handling End of data reception RTE Error handling Read ORER and FER flags in SCSSR1 Read receive data in SCRDR1 Clear user defined receive start flag to 0 Set RDRF 0 and MPIE 1 FER or ORER 1 FER or ORER 1 MPIE 0 This station s ID All data received Figure 15 15 Sample Flowchart of Multiprocessor Serial Reception with Interrupt Generation Figure 15 16 shows a sample flowch...

Page 706: ...R and FER flags in SCSSR1 Read RDRF flag in SCSSR1 Read receive data in SCRDR1 Set user defined receive start flag to 1 Read ORER and FER flags in SCSSR1 Read receive data in SCRDR1 Clear user defined receive start flag to 0 Set RDRF 0 and MPIE 1 FER or ORER 1 FER or ORER 1 MPIE 0 This station s ID All data received End of data reception RTE Error handling RXI 1 End of ID reception handling Figure...

Page 707: ...7EJ0301 Rev 3 01 Page 653 of 1128 Sep 24 2013 ORER 1 FER 1 Error handling Overrun error handling Break Framing error handling Clear RE bit in SCSCR1 to 0 Clear ORER and FER flags in SCSSR1 to 0 End Yes No No Yes Yes No Figure 15 16 Sample Multiprocessor Serial Reception Flowchart 2 ...

Page 708: ...PIE 0 SCRDR1 data read and RDRF flag cleared to 0 by RXI interrupt handler As data is not this station s ID MPIE bit is set to 1 again RXI interrupt request MPB Serial data Start bit Data ID2 Stop bit Start bit Data Data2 Stop bit Idle state mark state a Data does not match station s ID SCRDR1 value RXI interrupt request multiprocessor interrupt MPIE 0 SCRDR1 data read and RDRF flag cleared to 0 b...

Page 709: ...ng error bit is set If RDRF is 0 the value in SCRSR1 is transferred to SCRDR1 and if the stop bit is 0 RDRF is set to 1 15 3 4 Operation in Synchronous Mode In synchronous mode data is transmitted or received in synchronization with clock pulses making it suitable for high speed serial communication Inside the SCI the transmitter and receiver are independent units enabling full duplex communicatio...

Page 710: ... the CKE1 and CKE0 bits in SCSCR1 For details of SCI clock source selection see table 15 9 When the SCI is operated on an internal clock the serial clock is output from the SCK pin Eight serial clock pulses are output in the transfer of one character and when no transfer is performed the clock is fixed high In reception only if an on chip clock source is selected clock pulses are output while RE 1...

Page 711: ... TE and RE bits cleared to 0 Clear TE and RE bits in SCSCR1 to 0 Initialization 1 Set the clock selection in SCSCR1 Be sure to clear bits RIE TIE TEIE and MPIE TE and RE to 0 2 Set the data transfer format in SCSMR1 3 Write a value corresponding to the bit rate into SCBRR1 Not necessary if an external clock is used 4 Wait at least one bit interval then set the TE bit or RE bit in SCSCR1 to 1 Also ...

Page 712: ...d TEND 1 No Yes No Yes Yes No Write transmit data to SCTDR1 and clear TDRE flag in SCSSR1 to 0 1 SCI status check and transmit data write Read SCSSR1 and check that the TDRE flag is set to 1 then write transmit data to SCTDR1 and clear the TDRE flag to 0 2 To continue serial transmission be sure to read 1 from the TDRE flag to confirm that writing is possible then write data to SCTDR1 and then cle...

Page 713: ...he SCI outputs 8 serial clock pulses When use of an external clock has been specified data is output synchronized with the input clock The serial transmit data is sent from the TxD pin starting with the LSB bit 0 and ending with the MSB bit 7 3 The SCI checks the TDRE flag at the timing for sending the MSB bit 7 If the TDRE flag is cleared to 0 data is transferred from SCTDR1 to SCTSR1 and serial ...

Page 714: ...pt request One frame TXI interrupt request Figure 15 21 Example of SCI Transmit Operation Serial Data Reception Synchronous Mode Figure 15 22 shows a sample flowchart for serial reception Use the following procedure for serial data reception after enabling the SCI for reception When changing the operating mode from asynchronous to synchronous be sure to check that the ORER PER and FER flags are al...

Page 715: ...to 0 Transfer cannot be resumed if the ORER flag is set to 1 2 SCI status check and receive data read Read SCSSR1 and check that the RDRF flag is set to 1 then read the receive data in SCRDR1 and clear the RDRF flag to 0 Transition of the RDRF flag from 0 to 1 can also be identified by an RXI interrupt 3 Serial reception continuation procedure To continue serial reception finish reading the RDRF f...

Page 716: ...he receive data can be transferred from SCRSR1 to SCRDR1 If this check is passed the RDRF flag is set to 1 and the receive data is stored in SCRDR1 If a receive error is detected in the error check the operation is as shown in table 15 11 Neither transmit nor receive operations can be performed subsequently when a receive error has been found in the error check Also as the RDRF flag is not set to ...

Page 717: ...DRF flag cleared to 0 in RXI interrupt handler One frame RXI interrupt request ERI interrupt request due to overrun error Figure 15 23 Example of SCI Receive Operation Simultaneous Serial Data Transmission and Reception Synchronous Mode Figure 15 24 shows a sample flowchart for simultaneous serial transmit and receive operations Use the following procedure for simultaneous serial data transmit and...

Page 718: ...atus check and receive data read Read SCSSR1 and check that the RDRF flag is set to 1 then read the receive data in SCRDR1 and clear the RDRF flag to 0 Transition of the RDRF flag from 0 to 1 can also be identified by an RXI interrupt 4 Serial transmission reception continuation procedure To continue serial transmission reception finish reading the RDRF flag reading SCRDR1 and clearing the RDRF fl...

Page 719: ... to the transmit data register SCTDR1 is performed by the DMAC When the RDRF flag in SCSSR1 is set to 1 an RDR full request is generated separately from the interrupt request An RDR full request can activate the DMAC to perform data transfer The RDRF flag is cleared to 0 automatically when a receive data register SCRDR1 read is performed by the DMAC When the ORER FER or PER flag in SCSSR1 is set t...

Page 720: ... Flag The TDRE flag in SCSSR1 is a status flag that indicates that transmit data has been transferred from SCTDR1 to SCTSR1 When the SCI transfers data from SCTDR1 to SCTSR1 the TDRE flag is set to 1 Data can be written to SCTDR1 regardless of the state of the TDRE flag However if new data is written to SCTDR1 when the TDRE flag is cleared to 0 the data stored in SCTDR1 will be lost since it has n...

Page 721: ... of all 0s so the FER flag is set and the parity error flag PER may also be set Note that the SCI receiver continues to operate in the break state so if the FER flag is cleared to 0 it will be set to 1 again Sending a Break Signal The input output condition and level of the TxD pin are determined by bits SPB0IO and SPB0DT in the serial port register SCSPTR1 This feature can be used to send a break...

Page 722: ...is set to 1 Be sure to clear the receive error flags to 0 before starting transmission Note also that the receive error flags are not cleared to 0 by clearing the RE bit to 0 Receive Data Sampling Timing and Receive Margin in Asynchronous Mode The SCI operates on a base clock with a frequency of 16 times the bit rate In reception the SCI synchronizes internally with the fall of the start bit which...

Page 723: ...erial clock the transmit clock should not be input until at least 5 peripheral operating clock cycles after SCTDR1 is updated by the DMAC Incorrect operation may result if the transmit clock is input within 4 cycles after SCTDR1 is updated See figure 15 26 SCK TDRE TxD D0 D1 D2 D3 D4 D5 D6 D7 t Note When operating on an external clock set t 4 Figure 15 26 Example of Synchronous Transmission by DMA...

Page 724: ...s Internal Clock Mode In reception note that if RE is cleared to zero 1 5 peripheral operating clock cycles after the rising edge of the RxD D7 bit SCK output RDRF will be set to 1 but copying to SCRDR1 will not be possible When Using DMAC When using the DMAC for transmission reception make a setting to suppress output of RXI and TXI interrupt requests to the interrupt controller Even if a setting...

Page 725: ... with standard asynchronous communication chips such as a Universal Asynchronous Receiver Transmitter UART or Asynchronous Communication Interface Adapter ACIA There is a choice of 8 serial data transfer formats Data length 7 or 8 bits Stop bit length 1 or 2 bits Parity Even odd none Receive error detection Parity framing and overrun errors Break detection If the receive data following that in whi...

Page 726: ...t can issue requests independently The DMA controller DMAC can be activated to execute a data transfer by issuing a DMA transfer request in the event of a transmit FIFO data empty or receive FIFO data full interrupt When not in use the SCIF can be stopped by halting its clock supply to reduce power consumption Modem control functions RTS2 and CTS2 are provided The amount of data in the transmit re...

Page 727: ...Transmission reception control Baud rate generator Clock External clock Pck Pck 4 Pck 16 Pck 64 TXI RXI ERI BRI SCIF Bus interface Internal data bus SCSCR2 SCSPTR2 Legend SCRSR2 Receive shift register SCFRDR2 Receive FIFO data register SCTSR2 Transmit shift register SCFTDR2 Transmit FIFO data register SCSMR2 Serial mode register SCSCR2 Serial control register SCFSR2 Serial status register SCBRR2 B...

Page 728: ... in table 16 2 These registers are used to specify the data format and bit rate and to perform transmitter receiver control Table 16 2 SCIF Registers Name Abbrevia tion R W Initial Value P4 Address Area 7 Address Access Size Serial mode register SCSMR2 R W H 0000 H FFE80000 H IFE80000 16 Bit rate register SCBRR2 R W H FF H FFE80004 H IFE80004 8 Serial control register SCSCR2 R W H 0000 H FFE80008 ...

Page 729: ...eceive FIFO Data Register SCFRDR2 Bit 7 6 5 4 3 2 1 0 R W R R R R R R R R SCFRDR2 is a 16 stage FIFO register that stores received serial data When the SCIF has received one byte of serial data it transfers the received data from SCRSR2 to SCFRDR2 where it is stored and completes the receive operation SCRSR2 is then enabled for reception and consecutive receive operations can be performed until th...

Page 730: ...CFTDR2 to SCTSR2 and transmission started automatically SCTSR2 cannot be directly read or written to by the CPU 16 2 4 Transmit FIFO Data Register SCFTDR2 Bit 7 6 5 4 3 2 1 0 R W W W W W W W W W SCFTDR2 is a 16 stage FIFO register that stores 8 bit data for serial transmission If SCTSR2 is empty when transmit data has been written to SCFTDR2 the SCIF transfers the transmit data written in SCFTDR2 ...

Page 731: ...n standby mode or in the module standby state Bits 15 to 7 Reserved These bits are always read as 0 and should only be written with 0 Bit 6 Character Length CHR Selects 7 or 8 bits as the asynchronous mode data length Bit 6 CHR Description 0 8 bit data Initial value 1 7 bit data Note When 7 bit data is selected the MSB bit 7 of SCFTDR2 is not transmitted Bit 5 Parity Enable PE Selects whether or n...

Page 732: ...lus the parity bit is even 2 When odd parity is set parity bit addition is performed in transmission so that the total number of 1 bits in the transmit character plus the parity bit is odd In reception a check is performed to see if the total number of 1 bits in the receive character plus the parity bit is odd Bit 3 Stop Bit Length STOP Selects 1 or 2 bits as the stop bit length Bit 3 STOP Descrip...

Page 733: ... value 1 Pck 4 clock 1 0 Pck 16 clock 1 Pck 64 clock Note Pck Peripheral clock 16 2 6 Serial Control Register SCSCR2 Bit 15 14 13 12 11 10 9 8 Initial value 0 0 0 0 0 0 0 0 R W R R R R R R R R Bit 7 6 5 4 3 2 1 0 TIE RIE TE RE REIE CKE1 CKE0 Initial value 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R R W R W The SCSCR2 register performs enabling or disabling of SCIF transfer operations serial clock ou...

Page 734: ... is set to 1 a receive error interrupt ERI request when the ER flag in SCFSR2 is set to 1 and a break interrupt BRI request when the BRK flag in SCFSR2 or the ORER flag in SCLSR2 is set to 1 Bit 6 RIE Description 0 Receive data full interrupt RXI request receive error interrupt ERI request and break interrupt BRI request disabled Initial value 1 Receive data full interrupt RXI request receive erro...

Page 735: ...terrupt ERI and break interrupt BRI requests can be cleared by reading 1 from the ER BRK or ORER flag then clearing the flag to 0 or by clearing the RIE and REIE bits to 0 When REIE is set to 1 ERI and BRI interrupt requests will be generated even if RIE is cleared to 0 In DMAC transfer this setting is made if the interrupt controller is to be notified of ERI and BRI interrupt requests Bits 1 and ...

Page 736: ...Also note that in order to clear these flags they must be read as 1 beforehand The FER flag and PER flag are read only flags and cannot be modified SCFSR2 is initialized to H 0060 by a power on reset or manual reset It is not initialized in standby mode or in the module standby state Bits 15 to 12 Number of Parity Errors PER3 PER0 These bits indicate the number of data bytes in which a parity erro...

Page 737: ... PER bits in SCFSR2 can be used to determine whether there is a receive error in the data read from SCFRDR2 Bit 7 ER Description 0 No framing error or parity error occurred during reception Initial value Clearing conditions Power on reset or manual reset When 0 is written to ER after reading ER 1 1 A framing error or parity error occurred during reception Setting conditions When the SCIF checks wh...

Page 738: ...transmission has been ended Bit 6 TEND Description 0 Transmission is in progress Clearing conditions When transmit data is written to SCFTDR2 and 0 is written to TEND after reading TEND 1 When data is written to SCFTDR2 by the DMAC 1 Transmission has been ended Initial value Setting conditions Power on reset or manual reset When the TE bit in SCSCR2 is 0 When there is no transmit data in SCFTDR2 o...

Page 739: ...igger set number Initial value Setting conditions Power on reset or manual reset When the number of SCFTDR2 transmit data bytes falls to or below the transmit trigger set number as the result of a transmit operation Note As SCFTDR2 is a 16 byte FIFO register the maximum number of bytes that can be written when TDFE 1 is 16 transmit trigger set number Data written in excess of this will be ignored ...

Page 740: ...here is a framing error in the receive data that is to be read from SCFRDR2 Setting condition When there is a framing error in the data that is to be read next from SCFRDR2 Bit 2 Parity Error PER Indicates whether or not a parity error has been found in the data that is to be read from the receive FIFO data register SCFRDR2 Bit 2 PER Description 0 There is no parity error in the receive data that ...

Page 741: ...t When SCFRDR2 is read until the number of receive data bytes in SCFRDR2 falls below the receive trigger set number after reading RDF 1 and 0 is written to RDF When SCFRDR2 is read by the DMAC until the number of receive data bytes in SCFRDR2 falls below the receive trigger set number 1 The number of receive data bytes in SCFRDR2 is equal to or greater than the receive trigger set number Setting c...

Page 742: ...FRDR2 has been read by the DMAC 1 No further receive data has arrived Setting condition When SCFRDR2 contains fewer than the receive trigger set number of receive data bytes and no further data has arrived for at least 15 etu after the stop bit of the last data received Note Equivalent to 1 5 frames with an 8 bit 1 stop bit format etu Elementary time unit time for transfer of 1 bit 16 2 8 Bit Rate...

Page 743: ...d rate generator input clock n 0 to 3 See the table below for the relation between n and the clock SCSMR2 Setting n Clock CKS1 CKS0 0 Pck 0 0 1 Pck 4 0 1 2 Pck 16 1 0 3 Pck 64 1 1 The bit rate error in asynchronous mode is found from the following equation Error 1 100 Pck 106 N 1 B 64 22n 1 16 2 9 FIFO Control Register SCFCR2 Bit 15 14 13 12 11 10 9 8 RSTRG2 RSTRG1 RSTRG0 Initial value 0 0 0 0 0 0...

Page 744: ... RTS2 Output Active Trigger RSTRG2 RSTG1 and RSTG0 These bits output the high level to the RTS2 signal when the number of received data stored in the receive FIFO data register SCFRDR2 exceeds the trigger number as shown in the table below Bit 10 RSTRG2 Bit 9 RSTRG1 Bit 8 RSTRG0 RTS2 Output Active Trigger 0 0 0 15 Initial value 1 1 1 0 4 1 6 1 0 0 8 1 10 1 0 12 1 14 Bits 7 and 6 Receive FIFO Data ...

Page 745: ...Bit 3 Modem Control Enable MCE Enables the CTS2 and RTS2 modem control signals Bit 3 MCE Description 0 Modem signals disabled Initial value 1 Modem signals enabled Note CTS2 is fixed at active 0 regardless of the input value and RTS2 output is also fixed at 0 Bit 2 Transmit FIFO Data Register Reset TFRST Invalidates the transmit data in the transmit FIFO data register and resets it to the empty st...

Page 746: ...upper 8 bits show the number of transmit data bytes in SCFTDR2 and the lower 8 bits show the number of receive data bytes in SCFRDR2 SCFDR2 can be read by the CPU at all times Bit 15 14 13 12 11 10 9 8 T4 T3 T2 T1 T0 Initial value 0 0 0 0 0 0 0 0 R W R R R R R R R R These bits show the number of untransmitted data bytes in SCFTDR2 A value of H 00 indicates that there is no transmit data and a valu...

Page 747: ...ta written to the SCK2 pin by means of bits 3 and 2 Data can be read from and output data written to the CTS2 pin by means of bits 5 and 4 Data can be read from and output data written to the RTS2 pin by means of bits 6 and 7 SCSPTR2 can be read or written to by the CPU at all times All SCSPTR2 bits except bits 6 4 2 and 0 are initialized to 0 by a power on reset or manual reset the value of bits ...

Page 748: ...R2 should be cleared to 0 Bit 5 CTSIO Description 0 CTSDT bit value is not output to CTS2 pin Initial value 1 CTSDT bit value is output to CTS2 pin Bit 4 Serial Port CTS Port Data CTSDT Specifies the serial port CTS2 pin input output data Input or output is specified by the CTSIO bit see the description of bit 5 CTSIO for details In output mode the CTSDT bit value is output to the CTS2 pin The CTS...

Page 749: ...rt TxD2 pin output condition When the TxD2 pin is actually set as a port output pin and outputs the value set by the SPB2DT bit the TE bit in SCSCR2 should be cleared to 0 Bit 1 SPB2IO Description 0 SPB2DT bit value is not output to the TxD2 pin Initial value 1 SPB2DT bit value is output to the TxD2 pin Bit 0 Serial Port Break Data SPB2DT Specifies the serial port RxD2 pin input data and TxD2 pin ...

Page 750: ...ock diagrams are shown in figures 16 2 to 16 6 Reset Internal data bus SPTRW D7 D6 SCIF R Q D RTSIO C Reset Mode setting register SPTRR SPTRW R Q D RTSDT C MD8 RTS2 Legend SPTRW Write to SPTR SPTRR Read SPTR Note The RTS2 pin function is designated as modem control by the MCE bit in SCFCR2 Modem control enable signal RTS2 signal Figure 16 2 MD8 RTS2 Pin ...

Page 751: ...128 Sep 24 2013 Reset Internal data bus SPTRW D5 D4 SCIF R Q D CTSIO C Reset SPTRR Mode setting register SPTRW R Q D CTSDT C MD7 CTS2 Legend SPTRW Write to SPTR SPTRR Read SPTR Note The CTS2 pin function is designated as modem control by the MCE bit in SCFCR2 Modem control enable signal CTS2 signal Figure 16 3 MD7 CTS2 Pin ...

Page 752: ...Reset Internal data bus SPTRW Mode setting register SCIF R Q D D1 D0 SPB2IO C Reset SPTRW R Q D SPB2DT C MD1 TxD2 Legend SPTRW Write to SPTR Transmit enable signal Serial transmit data Figure 16 4 MD1 TxD2 Pin Internal data bus Mode setting register SCIF MD2 RxD2 SPTRR D0 Serial receive data Legend SPTRR Read SPTR Figure 16 5 MD2 RxD2 Pin ...

Page 753: ...SCIF R Q D SCKIO C R Q D SCKDT C SPTRR Clock output enable signal Serial clock output signal Serial clock input signal Clock input enable signal MD0 SCK2 Mode setting register Legend SPTRW Write to SPTR SPTRR Read SPTR Note Signals that set the SCK2 pin function as internal clock output or external clock input according to the CKE0 and CKE1 bits in SCSCR2 Figure 16 6 MD0 SCK2 Pin ...

Page 754: ...at an overrun error occurred during reception causing abnormal termination Bit 0 ORER Description 0 Reception in progress or reception has ended normally 1 Initial value Clearing conditions Power on reset or manual reset When 0 is written to ORER after reading ORER 1 1 An overrun error occurred during reception 2 Setting condition When the next serial reception is completed while the receive FIFO ...

Page 755: ...16 3 The SCIF clock source is determined by the CKE1 bit in the serial control register SCSCR2 as shown in table 16 4 Data length Choice of 7 or 8 bits Choice of parity addition and addition of 1 or 2 stop bits the combination of these parameters determines the transfer format and character length Detection of framing errors parity errors receive FIFO data full state overrun errors receive data re...

Page 756: ... Parity Bit Stop Bit Length 0 1 bit 0 1 No 2 bits 0 1 bit 0 1 1 8 bit data Yes 2 bits 0 1 bit 0 1 No 2 bits 0 1 bit 1 1 1 Asynchronous mode 7 bit data No Yes 2 bits Table 16 4 SCSCR2 Settings for SCIF Clock Source Selection SCSCR2 Setting SCIF Transmit Receive Clock Bit 1 CKE1 Bit 0 CKE0 Mode Clock Source SCK2 Pin Function 0 SCIF does not use SCK2 pin 0 1 Internal Output clock with frequency of 16...

Page 757: ...sfer formats can be selected according to the SCSMR2 settings Table 16 5 Serial Transfer Formats SCSMR2 Settings Serial Transfer Format and Frame Length CHR PE STOP 1 2 3 4 5 6 7 8 9 10 11 12 0 0 0 S 8 bit data STOP 0 0 1 S 8 bit data STOP STOP 0 1 0 S 8 bit data P STOP 0 1 1 S 8 bit data P STOP STOP 1 0 0 S 7 bit data STOP 1 0 1 S 7 bit data STOP STOP 1 1 0 S 7 bit data P STOP 1 1 1 S 7 bit data ...

Page 758: ...ssary to clear the TE and RE bits in SCSCR2 to 0 then initialize the SCIF as described below When the transfer format etc is changed the TE and RE bits must be cleared to 0 before making the change using the following procedure When the TE bit is cleared to 0 SCTSR2 is initialized Note that clearing the TE and RE bits to 0 does not change the contents of SCFSR2 SCFTDR2 or SCFRDR2 The TE bit should...

Page 759: ...and RE bits in SCSCR2 to 1 and set RIE TIE and REIE bits End Wait No Yes 1 Set the clock selection in SCSCR2 Be sure to clear bits RIE and TIE and bits TE and RE to 0 2 Set the data transfer format in SCSMR2 3 Write a value corresponding to the bit rate into SCBRR2 Not necessary if an external clock is used 4 Wait at least one bit interval then set the TE bit or RE bit in SCSCR2 to 1 Also set the ...

Page 760: ...s check and transmit data write Read SCFSR2 and check that the TDFE flag is set to 1 then write transmit data to SCFTDR2 read 1 from the TDFE and TEND flags then clear these flags to 0 The number of transmit data bytes that can be written is 16 transmit trigger set number 2 Serial transmission continuation procedure To continue serial transmission read 1 from the TDFE flag to confirm that writing ...

Page 761: ... flag is set If the TIE bit in SCSCR2 is set to 1 at this time a transmit FIFO data empty interrupt TXI request is generated The serial transmit data is sent from the TxD2 pin in the following order a Start bit One 0 bit is output b Transmit data 8 bit or 7 bit data is output in LSB first order c Parity bit One parity bit even or odd parity is output A format in which a parity bit is not output ca...

Page 762: ...6 9 Example of Transmit Operation Example with 8 Bit Data Parity One Stop Bit 4 When modem control is enabled transmission can be stopped and restarted in accordance with the CTS2 input value When CTS2 is set to 1 if transmission is in progress the line goes to the mark state after transmission of one frame When CTS2 is set to 0 the next transmit data is output starting from the start bit Figure 1...

Page 763: ...and BRK flags in SCFSR2 and the ORER flag in SCLSR2 to identify any error perform the appropriate error handling then clear the DR ER BRK and ORER flags to 0 In the case of a framing error a break can also be detected by reading the value of the RxD2 pin 2 SCIF status check and receive data read Read SCFSR2 and check that RDF 1 then read the receive data in SCFRDR2 read 1 from the RDF flag and the...

Page 764: ...n SCLSR2 to 0 End Yes Yes Yes No Overrun error handling ORER 1 Yes No No No 1 Whether a framing error or parity error has occurred in the receive data read from SCFRDR2 can be ascertained from the FER and PER bits in SCFSR2 2 When a break signal is received receive data is not transferred to SCFRDR2 while the BRK flag is set However note that the last data in SCFRDR2 is H 00 the break data in whic...

Page 765: ...r receive data can be transferred from the receive shift register SCRSR2 to SCFRDR2 c Overrun error check The SCIF checks that the ORER flag is 0 indicating that no overrun error has occurred d Break check The SCIF checks that the BRK flag is 0 indicating that the break state is not set If all the b c and d checks are passed the receive data is stored in SCFRDR2 Note Reception continues when parit...

Page 766: ...ion Example with 8 Bit Data Parity One Stop Bit 5 When modem control is enabled the RTS2 signal is output when SCFRDR2 is empty When RTS2 is 0 reception is possible When RTS2 is 1 this indicates that SCFRDR2 contains a number of data bytes equal to or greater than the RTS2 output active trigger set number The RTS2 output active trigger value is specified by bits 10 to 8 in the FIFO control registe...

Page 767: ...to 1 while the RIE bit is cleared to 0 it is possible to output ERI and BRI interrupt requests but not RXI interrupt requests When the TDFE flag in the serial status register SCFSR2 is set to 1 a transmit FIFO data empty request is generated separately from the interrupt request A transmit FIFO data empty request can activate the DMAC to perform data transfer When the RDF flag or DR flag in SCFSR2...

Page 768: ...transmit data up to the number of empty bytes in SCFTDR2 can be written allowing efficient continuous transmission However if the number of data bytes written in SCFTDR2 is equal to or less than the transmit trigger number the TDFE flag will be set to 1 again after being read as 1 and cleared to 0 TDFE clearing should therefore be carried out when SCFTDR2 contains more than the transmit trigger nu...

Page 769: ...er SCSPTR2 This feature can be used to send a break signal After the serial transmitter is initialized the TxD2 pin function is not selected and the value of the SPB2DT bit substitutes for the mark state until the TE bit is set to 1 i e transmission is enabled The SPB2IO and SPB2DT bits should therefore be set to 1 designating output and high level beforehand To send a break signal during serial t...

Page 770: ...igure 16 14 Receive Data Sampling Timing in Asynchronous Mode The receive margin in asynchronous mode can therefore be expressed as shown in equation 1 M 0 5 L 0 5 F 1 F 100 1 2N D 0 5 N 1 Legend M Receive margin N Ratio of clock frequency to bit rate N 16 D Clock duty cycle D 0 to 1 0 L Frame length L 9 to 12 F Absolute deviation of clock frequency From equation 1 if F 0 and D 0 5 the receive mar...

Page 771: ...ssion reception inhibit output of RXI and TXI interrupt requests to the interrupt controller If interrupt request output is enabled interrupt requests to the interrupt controller will be cleared by the DMAC without regard to the interrupt handler Serial Ports Note that when the SCIF pin value is read using a serial port the value read will be the value two peripheral clock cycles earlier ...

Page 772: ...Section 16 Serial Communication Interface with FIFO SCIF SH7751 Group SH7751R Group Page 718 of 1128 R01UH0457EJ0301 Rev 3 01 Sep 24 2013 ...

Page 773: ...f the smart card interface are listed below Asynchronous mode Data length 8 bits Parity bit generation and checking Transmission of error signal parity error in receive mode Error signal detection and automatic data retransmission in transmit mode Direct convention and inverse convention both supported On chip baud rate generator allows any bit rate to be selected Three interrupt sources There are...

Page 774: ... Transmission reception control Baud rate generator Clock External clock Pck Pck 4 Pck 16 Pck 64 TXI RXI ERI SCI Bus interface Internal data bus SCSMR1 Legend SCSCMR1 Smart card mode register SCRSR1 Receive shift register SCRDR1 Receive data register SCTSR1 Transmit shift register SCTDR1 Transmit data register SCSMR1 Serial mode register SCSCR1 Serial control register SCSSR1 Serial status register...

Page 775: ...he smart card interface registers are initialized in standby mode and in the module standby state as well as by a power on reset or manual reset When recovering from standby mode or the module standby state the registers must be set again Table 17 2 Smart Card Interface Registers Name Abbreviation R W Initial Value P4 Address Area 7 Address Acces s Size Serial mode register SCSMR1 R W H 00 H FFE00...

Page 776: ...itten with 0 Bit 3 Smart Card Data Transfer Direction SDIR Selects the serial parallel conversion format Bit 3 SDIR Description 0 SCTDR1 contents are transmitted LSB first Initial value Receive data is stored in SCRDR1 LSB first 1 SCTDR1 contents are transmitted MSB first Receive data is stored in SCRDR1 MSB first Bit 2 Smart Card Data Invert SINV Specifies inversion of the data logic level This f...

Page 777: ...iming for setting the TEND flag that indicates completion of transmission and the type of clock output used The details of the additional clock output control mode are specified by the CKE1 and CKE0 bits in the serial control register SCSCR1 In GSM mode the pulse width is guaranteed when SCK start stop specifications are made by CKE1 and CKE0 Bit 7 GM Description 0 Normal smart card interface mode...

Page 778: ...with the smart card interface Bits 1 and 0 Clock Enable 1 and 0 CKE1 CKE0 These bits specify the function of the SCK pin In smart card interface mode an internal clock is always used as the clock source In smart card interface mode it is possible to specify a fixed high level or fixed low level for the clock output in addition to the usual switching between enabling and disabling of the clock outp...

Page 779: ...Status ERS In smart card interface mode bit 4 indicates the status of the error signal sent back from the receiving side during transmission Framing errors are not detected in smart card interface mode Bit 4 ERS Description 0 Normal reception no error signal Initial value Clearing conditions Power on reset manual reset standby mode or module standby When 0 is written to ERS after reading ERS 1 1 A...

Page 780: ...ER ERS 0 normal transmission 1 0 etu after transmission of a 1 byte serial character Note etu Elementary time unit time for transfer of 1 bit Bits 1 and 0 Reserved Not used with the smart card interface 17 3 Operation 17 3 1 Overview The main functions of the smart card interface are as follows One frame consists of 8 bit data plus a parity bit In transmission a guard time of at least 2 etu elemen...

Page 781: ...e VCC power supply side with a resistor When the clock generated on the smart card interface is used by an IC card the SCK pin output is input to the CLK pin of the IC card No connection is needed if the IC card uses an internal clock Chip port output is used as the reset signal Other pins must normally be connected to the power supply or ground Note If an IC card is not connected and both TE and ...

Page 782: ... no parity error When a parity error occurs Transmitting station output Transmitting station output Receiving station output Figure 17 3 Smart Card Interface Data Format The operation sequence is as follows 1 When the data line is not in use it is in the high impedance state and is fixed high with a pull up resistor 2 The transmitting station starts transmission of one frame of data The data frame...

Page 783: ...r 1 must be set to the value shown The setting of other bits is described below Table 17 3 Smart Card Interface Register Settings Bit Register Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 SCSMR1 GM 0 1 O E 1 0 CKS1 CKS0 SCBRR1 BRR7 BRR6 BRR5 BRR4 BRR3 BRR2 BRR1 BRR0 SCSCR1 TIE RIE TE RE 0 0 CKE1 CKE0 SCTDR1 TDR7 TDR6 TDR5 TDR4 TDR3 TDR2 TDR1 TDR0 SCSSR1 TDRE RDRF ORER FER ERS PER TEND 0 0 SCRDR...

Page 784: ...CSCMR1 Settings The SDIR bit and SINV bit are both cleared to 0 if the IC card is of the direct convention type and both set to 1 if of the inverse convention type The SMIF bit is set to 1 when the smart card interface is used Figure 17 5 shows examples of register settings and the waveform of the start character for the two types of IC card direct convention and inverse convention With the direct...

Page 785: ...2 D1 D0 Dp Figure 17 5 Sample Start Character Waveforms 17 3 5 Clock Only an internal clock generated by the on chip baud rate generator can be used as the transmit receive clock for the smart card interface The bit rate is set with the bit rate register SCBRR1 and the CKS1 and CKS0 bits in the serial mode register SCSMR1 The equation for calculating the bit rate is shown below Table 17 5 shows so...

Page 786: ...0 0 16801 1 22177 4 33602 2 2 3200 0 4480 3 4800 0 6400 0 11200 7 14784 9 22401 4 Note Bit rates are rounded to one decimal place The method of calculating the value to be set in the bit rate register SCBRR1 from the peripheral module operating frequency and bit rate is shown below Here N is an integer in the range 0 N 255 and the smaller error is specified N 106 1 1488 22n 1 B Pck Table 17 6 Exam...

Page 787: ...between the smart card interface transmit receive clock register settings and the output state Table 17 8 Register Settings and SCK Pin State Register Values SCK Pin Setting SMIF GM CKE1 CKE0 Output State 1 1 1 0 0 0 Port Determined by setting of SPB1IO and SPB1DT bits in SCSPTR1 1 0 0 1 SCK serial clock output state 2 2 1 1 0 0 Low output Low level output state 1 1 0 1 SCK serial clock output sta...

Page 788: ... serial control register SCSCR1 to 0 2 Clear error flags FER ERS PER and ORER in the serial status register SCSSR1 to 0 3 Set the GM bit parity bit O E and baud rate generator select bits CKS1 and CKS0 in the serial mode register SCSMR1 Clear the CHR and MP bits to 0 and set the STOP and PE bits to 1 4 Set the SMIF SDIR and SINV bits in the smart card mode register SCSCMR1 When the SMIF bit is set...

Page 789: ...and ORER flags in SCSCR1 to 0 In SCSMR1 set parity in O E bit clock in CKS1 and CKS0 bits and set GM Set SMIF SDIR and SINV bits in SCSCMR1 Set value in SCBRR1 In SCSCR1 set clock in CKE1 and CKE0 bits and clear TIE RIE TE RE MPIE and TEIE bits to 0 1 bit interval elapsed Set TIE RIE TE and RE bits in SCSCR1 End Wait No Yes 1 2 3 4 5 6 7 Figure 17 7 Sample Initialization Flowchart ...

Page 790: ... can be confirmed that the TEND flag in SCSSR1 is set to 1 4 Write the transmit data to SCTDR1 clear the TDRE flag to 0 and perform the transmit operation The TEND flag is cleared to 0 5 To continue transmitting data go back to step 2 6 To end transmission clear the TE bit to 0 With the above processing interrupt handling is possible If transmission ends and the TEND flag is set to 1 while the TIE...

Page 791: ...ization Start of transmission Write transmit data to SCTDR1 and clear TDRE flag in SCSSR1 to 0 FER ERS 0 TEND 1 All data transmitted FER ERS 0 TEND 1 Clear TE bit in SCSCR1 to 0 End of transmission Error handling Error handling No Yes Yes Yes Yes No Yes No No No 1 2 3 4 5 6 Figure 17 8 Sample Transmission Processing Flowchart ...

Page 792: ...it can be confirmed that the RDRF flag is set to 1 4 Read the receive data from SCRDR1 5 To continue receiving data clear the RDRF flag to 0 and go back to step 2 6 To end reception clear the RE bit to 0 With the above processing interrupt handling is possible If reception ends and the RDRF flag is set to 1 while the RIE bit is set to 1 and interrupt requests are enabled a receive data full interr...

Page 793: ...essing Flowchart Mode Switching Operation When switching from receive mode to transmit mode first confirm that the receive operation has been completed then start from initialization clearing RE to 0 and setting TE to 1 The RDRF flag or the PER and ORER flags can be used to check that the receive operation has been completed When switching from transmit mode to receive mode first confirm that the ...

Page 794: ...CSSR1 is set to 1 a TXI interrupt is requested If the TXI request is designated beforehand as a DMAC activation source the DMAC will be activated by the TXI request and transfer of the transmit data will be carried out The TEND flag is automatically cleared to 0 when data transfer is performed by the DMAC In the event of an error the SCI retransmits the same data automatically The TEND flag remain...

Page 795: ...I as a smart card interface 1 Receive Data Sampling Timing and Receive Margin In asynchronous mode the SCI operates on a base clock with a frequency of 372 times the transfer rate In reception the SCI synchronizes internally with the fall of the start bit which it samples on the base clock Receive data is latched at the rising edge of the 186th base clock pulse The timing is shown in figure 17 10 ...

Page 796: ... Figure 17 11 illustrates the retransfer operation when the SCI is in receive mode 1 If an error is found when the received parity bit is checked the PER bit in SCSSR1 is automatically set to 1 If the RIE bit in SCSCR1 is enabled at this time an ERI interrupt request is generated The PER bit in SCSSR1 should be cleared to 0 before the next parity bit is sampled 2 The RDRF bit in SCSSR1 is not set ...

Page 797: ...erated The FER ERS bit in SCSSR1 should be cleared to 0 before the next parity bit is sampled 2 The TEND bit in SCSSR1 is not set for a frame for which an error signal indicating an error is received 3 If an error signal is not sent back from the receiving side the FER ERS bit in SCSSR1 is not set 4 If an error signal is not sent back from the receiving side transmission of one frame including a r...

Page 798: ... the fixed output state in standby mode 3 Write 0 to the CKE0 bit in SCSCR1 to stop the clock 4 Wait for one serial clock cycle During this period the duty cycle is preserved and clock output is fixed at the specified level 5 Write H 00 to the serial mode register SCSMR1 and smart card mode register SCSMR1 6 Make the transition to the standby state Returning from Standby Mode to Smart Card Interfa...

Page 799: ... duty cycle after powering on 1 The initial state is port input and high impedance Use pull up or pull down resistors to fix the potential 2 Fix at the output specified by the CKE1 bit in the serial control register SCSCR1 3 Set the serial mode register SCSMR1 and smart card mode register SCSCMR1 and switch to smart card mode operation 4 Set the CKE0 bit in SCSCR1 to 1 to start clock output ...

Page 800: ...Section 17 Smart Card Interface SH7751 Group SH7751R Group Page 746 of 1128 R01UH0457EJ0301 Rev 3 01 Sep 24 2013 ...

Page 801: ...2 Do not set PORTEN 1 when in PCI enabled mode The features of the SCI I O port are as follows Data can be output when the I O port is designated for output and SCI enabling has not been set This allows break function transmission The RxD pin value can be read at all times allowing break state detection SCK pin control is possible when the I O port is designated for output and SCI enabling has not...

Page 802: ...P PORTEN ADnDIR PBnIO 0 1 PDTRW BCK Data input strobe D Q C 0 1 0 1 MPX MPX MPX PTIRENn BCK C Q D Pull up resistor Port 15 input output AD15 to Port 0 input output AD0 ADn output data Internal bus Interrupt controller PORTEN 0 Port not available 1 Port available PBnPuP 0 Pull up 1 Pull up off DnDIR 0 Input 1 Output PBnIO 0 Input 1 Output PTIRENn 0 Interrupt input disabled 1 Interrupt input enabled...

Page 803: ...which has no interrupt function PBnPUP PORTEN ADnDIR PBnIO 0 1 PDTRW BCK D Q C 0 1 0 1 BCK C Q D MPX MPX MPX Data input strobe Pull up resistor Port 31 input output AD31 to Port 16 input output AD16 ADn output data Internal bus PORTEN 0 Port not available 1 Port available PBnPuP 0 Pull up 1 Pull up off DnDIR 0 Input 1 Output PBnIO 0 Input 1 Output Figure 18 2 16 Bit Port B ...

Page 804: ...bus SPTRW SPTRW SCI R Q D SPB1IO C R Q D SPB1DT C SPTRR Clock output enable signal Serial clock output signal Serial clock input signal Clock input enable signal SCK Legend SPTRW Write to SPTR SPTRR Read SPTR Note Signals that set the SCK pin function as internal clock output or external clock input according to the CKE0 and CKE1 bits in SCSCR1 and the C A bit in SCSMR1 Figure 18 3 SCK Pin ...

Page 805: ...1 of 1128 Sep 24 2013 Reset Internal data bus SPTRW SCI R Q D SPB0IO C Reset SPTRW R Q D SPB0DT C TxD Transmit enable signal Serial transmit data Legend SPTRW Write to SPTR Figure 18 4 TxD Pin Internal data bus SCI RxD SPTRR Serial receive data Legend Read SPTR Figure 18 5 RxD Pin ...

Page 806: ...res 18 6 to 18 10 Reset Internal data bus SPTRW Mode setting register SCIF R Q D SPB2IO C Reset SPTRW R Q D SPB2DT C MD1 TxD2 Legend SPTRW Write to SPTR Transmit enable signal Serial transmit data Figure 18 6 MD1 TxD2 Pin Internal data bus Mode setting register SCIF MD2 RxD2 SPTRR Serial receive data Legend SPTRR Read SPTR Figure 18 7 MD2 RxD2 Pin ...

Page 807: ... R Q D SCKDT C SPTRR Clock output enable signal Serial clock output signal Serial clock input signal Clock input enable signal MD0 SCK2 Mode setting register Legend SPTRW Write to SPTR SPTRR Read SPTR Note Signals that set the SCK2 pin function as internal clock output or external clock input according to the CKE0 and CKE1 bits in SCSCR2 Figure 18 8 MD0 SCK2 Pin ...

Page 808: ...Reset Internal data bus SPTRW SCIF R Q D CTSIO C Reset SPTRR SPTRW R Q D CTSDT C MD7 CTS2 Mode setting register Legend SPTRW Write to SPTR SPTRR Read SPTR Note MCE bit in SCFCR2 signal that designates modem control as the CTS2 pin function Modem control enable signal CTS2 signal Figure 18 9 MD7 CTS2 Pin ...

Page 809: ... the RTS2 pin function Modem control enable signal RTS2 signal Figure 18 10 MD8 RTS2 Pin 18 1 3 Pin Configuration Table 18 1 shows the 32 bit general purpose I O port pin configuration Table 18 1 32 Bit General Purpose I O Port Pins Pin Name Signal I O Function Port 31 pin AD31 PORT31 I O I O port Port 30 pin AD30 PORT30 I O I O port Port 29 pin AD29 PORT29 I O I O port Port 28 pin AD28 PORT28 I O...

Page 810: ... O port GPIO interrupt Port 12 pin AD12 PORT12 I O I O port GPIO interrupt Port 11 pin AD11 PORT11 I O I O port GPIO interrupt Port 10 pin AD10 PORT10 I O I O port GPIO interrupt Port 9 pin AD9 PORT9 I O I O port GPIO interrupt Port 8 pin AD8 PORT8 I O I O port GPIO interrupt Port 7 pin AD7 PORT7 I O I O port GPIO interrupt Port 6 pin AD6 PORT6 I O I O port GPIO interrupt Port 5 pin AD5 PORT5 I O ...

Page 811: ...rmed by means of a setting in the SCI s SCSPTR1 register Table 18 3 shows the SCIF I O port pin configuration Table 18 3 SCIF I O Port Pins Pin Name Abbreviation I O Function Serial clock pin MD0 SCK2 I O Clock input output Receive data pin MD2 RxD2 Input Receive data input Transmit data pin MD1 TxD2 Output Transmit data output Modem control pin MD7 CTS2 I O Transmission enabled Modem control pin ...

Page 812: ... Access Size Port control register A PCTRA R W H 00000000 H FF80002C H 1F80002C 32 Port data register A PDTRA R W Undefined H FF800030 H 1F800030 16 Port control register B PCTRB R W H 00000000 H FF800040 H 1F800040 32 Port data register B PDTRB R W Undefined H FF800044 H 1F800044 16 GPIO interrupt control register GPIOIC R W H 00000000 H FF800048 H 1F800048 16 Serial port register SCSPTR1 R W Und...

Page 813: ... PCTRA is initialized to H 00000000 by a power on reset It is not initialized by a manual reset or in standby mode and retains its contents Bit 31 30 29 28 27 26 25 24 PB15PUP PB15IO PB14PUP PB14IO PB13PUP PB13IO PB12PUP PB12IO Initial value 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W Bit 23 22 21 20 19 18 17 16 PB11PUP PB11IO PB10PUP PB10IO PB9PUP PB9IO PB8PUP PB8IO Initial value 0 0 0 0 ...

Page 814: ... 15 of 16 bit port A is an output 18 2 2 Port Data Register A PDTRA Port data register A PDTRA is a 16 bit readable writable register used as a data latch for each bit in the 16 bit port A When a bit is set as an output the value written to the PDTRA register is output from the external pin When a value is read from the PDTRA register while a bit is set as an input the external pin value sampled o...

Page 815: ...PCTRB is initialized to H 00000000 by a power on reset It is not initialized by a manual reset or in standby mode and retains its contents Bit 31 30 29 28 27 26 25 24 PB31PUP PB31IO PB30PUP PB30IO PB29PUP PB29IO PB28PUP PB28IO Initial value 0 0 0 0 0 0 0 0 R W R R R R R R R R Bit 23 22 21 20 19 18 17 16 PB27PUP PB27IO PB26PUP PB26IO PB25PUP PB25IO PB24PUP PB24IO Initial value 0 0 0 0 0 0 0 0 R W R...

Page 816: ... of 16 bit port B is an output 18 2 4 Port Data Register B PDTRB Port data register B PDTRB is a 16 bit readable writable register used as a data latch for each bit in the 16 bit port B When a bit is set as an output the value written to the PDTRB register is output from the external pin When a value is read from the PDTRB register while a bit is set as an input the external pin value sampled on t...

Page 817: ...ich bits interrupts are input to can be identified by reading the PDTRA register Bit 15 14 13 12 11 10 9 8 PTIREN15 PTIREN14 PTIREN13 PTIREN12 PTIREN11 PTIREN10 PTIREN9 PTIREN8 Initial value 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W Bit 7 6 5 4 3 2 1 0 PTIREN7 PTIREN6 PTIREN5 PTIREN4 PTIREN3 PTIREN2 PTIREN1 PTIREN0 Initial value 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W Bit n n...

Page 818: ... controls enabling and disabling of the RXI interrupt SCSPTR1 can be read or written to by the CPU at all times All SCSPTR1 bits except bits 2 and 0 are initialized to 0 by a power on reset or manual reset the value of bits 2 and 0 is undefined SCSPTR1 is not initialized in the module standby state or standby mode Bit 7 Error Interrupt Only EIO See section 15 2 8 Serial Port Register SCSPTR1 Bits ...

Page 819: ...serial port TxD pin output condition When the TxD pin is actually set as a port output pin and outputs the value set by the SPB0DT bit the TE bit in SCSCR1 should be cleared to 0 Bit 1 SPB0IO Description 0 SPB0DT bit value is not output to the TxD pin Initial value 1 SPB0DT bit value is output to the TxD pin Bit 0 Serial Port Break Data SPB0DT Specifies the serial port RxD pin input data and TxD p...

Page 820: ...data writing can be performed by means of bits 3 and 2 CTS2 pin data reading and output data writing can be performed by means of bits 5 and 4 and RTS2 pin data reading and output data writing by means of bits 7 and 6 SCSPTR2 can be read or written to by the CPU at all times All SCSPTR2 bits except bits 6 4 2 and 0 are initialized to 0 by a power on reset or manual reset the value of bits 6 4 2 an...

Page 821: ... 5 CTSIO Description 0 CTSDT bit value is not output to the CTS2 pin Initial value 1 CTSDT bit value is output to the CTS2 pin Bit 4 Serial Port CTS Port Data CTSDT Specifies the serial port CTS2 pin input output data Input or output is specified by the CTSIO pin see the description of bit 5 CTSIO for details When the CTS2 pin is designated as an output the value of the CTSDT bit is output to the ...

Page 822: ... condition When the TxD2 pin is actually set as a port output pin and outputs the value set by the SPB2DT bit the TE bit in SCSCR2 should be cleared to 0 Bit 1 SPB2IO Description 0 SPB2DT bit value is not output to the TxD2 pin Initial value 1 SPB2DT bit value is output to the TxD2 pin Bit 0 Serial Port Break Data SPB2DT Specifies the serial port RxD2 pin input data and TxD2 pin output data The Tx...

Page 823: ...TC has the following features Fifteen interrupt priority levels can be set By setting the five interrupt priority registers the priorities of on chip peripheral module interrupts can be selected from 15 levels for different request sources NMI noise canceler function The NMI input level bit indicates the NMI pin state The pin state can be checked by reading this bit in the interrupt exception hand...

Page 824: ...g interface unit GPIO I O port PCIC PCI bus controller ICR Interrupt control register IPRA IPRD Interrupt priority registers A D INTPRI00 Interrupt priority register 00 SR Status register NMI Input control IRL3 IRL0 TMU RTC SCI SCIF WDT REF DMAC H UDI Priority identifier 4 4 Interrupt request Com parator Bus interface Internal bus ICR IPRA IPRD INTPRI00 Interrupt request Interrupt request Interrup...

Page 825: ...dress Access Size Interrupt control register ICR R W 2 H FFD00000 H 1FD00000 16 Interrupt priority register A IPRA R W H 0000 H FFD00004 H 1FD00004 16 Interrupt priority register B IPRB R W H 0000 H FFD00008 H 1FD00008 16 Interrupt priority register C IPRC R W H 0000 H FFD0000C H 1FD0000C 16 Interrupt priority register D IPRD R W H DA74 H FFD00010 H 1FD00010 16 Interrupt priority register 00 INTPR...

Page 826: ...16 It is always accepted unless the BL bit in the status register in the CPU is set to 1 In sleep or standby mode the interrupt is accepted even if the BL bit is set to 1 A setting can also be made to have the NMI interrupt accepted even if the BL bit is set to 1 Input from the NMI pin is edge detected The NMI edge select bit NMIE in the interrupt control register ICR is used to select either risi...

Page 827: ...ins IRL3 IRL0 The priority level is the level indicated by pins IRL3 IRL0 An IRL3 IRL0 value of 0 0000 indicates the highest level interrupt request interrupt priority level 15 A value of 15 1111 indicates no interrupt request interrupt priority level 0 Interrupt requests Priority encoder IRL3 to IRL0 4 SH7751 SH7751R IRL3 to IRL0 Figure 19 2 Example of IRL Interrupt Connection ...

Page 828: ...upt request 1 0 No interrupt request A noise cancellation feature is built in and the IRL interrupt is not detected unless the levels sampled at every bus clock cycle remain unchanged for three consecutive cycles so that no transient level on the IRL pin change is detected In standby mode as the bus clock is stopped noise cancellation is performed using the 32 768 kHz clock for the RTC instead Whe...

Page 829: ...interrupt mask bits IMASK in the status register SR are not affected by on chip peripheral module interrupt handling On chip peripheral module interrupt source flag and interrupt enable flag updating should only be carried out when the BL bit in the status register SR is set to 1 To prevent acceptance of an erroneous interrupt from an interrupt source that should have been updated first read the o...

Page 830: ...ty of the on chip peripheral modules is specified as desired by setting priority levels from 0 to 15 in interrupt priority registers A to D IPRA IPRD and interrupt priority register 00 INTPRI00 The order of priority of the on chip peripheral modules is set to 0 by a reset When the priorities for multiple interrupt sources are set to the same level and such interrupts are generated simultaneously t...

Page 831: ... IRL0 2 H 240 13 IRL3 IRL0 3 H 260 12 IRL3 IRL0 4 H 280 11 IRL3 IRL0 5 H 2A0 10 IRL3 IRL0 6 H 2C0 9 IRL3 IRL0 7 H 2E0 8 IRL3 IRL0 8 H 300 7 IRL3 IRL0 9 H 320 6 IRL3 IRL0 A H 340 5 IRL3 IRL0 B H 360 4 IRL3 IRL0 C H 380 3 IRL3 IRL0 D H 3A0 2 IRL3 IRL0 E H 3C0 1 IRL0 H 240 15 0 13 IPRD 15 12 IRL1 H 2A0 15 0 10 IPRD 11 8 IRL2 H 300 15 0 7 IPRD 7 4 IRL3 H 360 15 0 4 IPRD 3 0 H UDI H UDI H 600 15 0 0 IP...

Page 832: ...MA2 H A40 PCIDMA3 H A20 INTPRI00 7 4 Low TMU3 TUNI3 H B00 15 0 0 INTPRI00 11 8 TMU4 TUNI4 H B80 15 0 0 INTPRI00 15 12 TMU0 TUNI0 H 400 15 0 0 IPRA 15 12 TMU1 TUNI1 H 420 15 0 0 IPRA 11 8 TMU2 TUNI2 H 440 15 0 0 IPRA 7 4 High TICPI2 H 460 Low RTC ATI H 480 15 0 0 IPRA 3 0 High PRI H 4A0 CUI H 4C0 Low SCI ERI H 4E0 15 0 0 IPRB 7 4 High RXI H 500 TXI H 520 TEI H 540 Low SCIF ERI H 700 15 0 0 IPRC 7 4...

Page 833: ...pty interrupt TEI Transmit end interrupt BRI Break interrupt request ITI Interval timer interrupt RCMI Compare match interrupt ROVI Refresh counter overflow interrupt H UDI H UDI interrupt GPIOI I O port interrupt DMTE0 DMTE7 DMAC transfer end interrupts DMAE DMAC address error interrupt PCISERR PCIC SERR error interrupt PCIERR PCIC error interrupt PCIPWDWN PCIC power down request interrupt PCIPWO...

Page 834: ...are initialized to H 0000 and IPRD is to H DA74 by a reset They are not initialized in standby mode IPRA to IPRC Bit 15 14 13 12 11 10 9 8 Initial value 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W Bit 7 6 5 4 3 2 1 0 Initial value 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W IPRD Bit 15 14 13 12 11 10 9 8 Initial value 1 1 0 1 1 0 1 0 R W R W R W R W R W R W R W R W R W Bit 7 6 5 4 ...

Page 835: ... peripheral modules are assigned to each register Interrupt priority levels are established by setting a value from H F 1111 to H 0 0000 in each of the four bit groups 15 12 11 8 7 4 and 3 0 Setting H F designates priority level 15 the highest level and setting H 0 designates priority level 0 requests are masked 19 3 2 Interrupt Control Register ICR The interrupt control register ICR is a 16 bit r...

Page 836: ...ion and in sleep mode In standby mode all interrupts are masked and standby is not cleared while the NMI pin is low Bit 9 NMI Block Mode NMIB Specifies whether an NMI request is to be held pending or detected immediately while the SR BL bit is set to 1 Bit 9 NMIB Description 0 NMI interrupt requests held pending while SR BL bit is set to 1 Initial value 1 NMI interrupt requests detected while SR B...

Page 837: ...egister INTPRI00 sets the order of priority levels 15 to 0 of the internal peripheral module interrupts The INTPRI00 register is a 32 bit read write register It is initialized to H 00000000 at a reset It is not initialized in standby mode Bit 31 30 29 19 18 17 16 Initial value 0 0 0 0 0 0 0 R W R R R R R R R Bit 15 14 13 3 2 1 0 Initial value 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W Table 19 ...

Page 838: ...TMSK00 the bits in this register are not affected INTREQ00 is a 32 bit read only register Bit 31 30 29 11 10 9 8 Initial value 0 0 0 0 0 0 0 R W R R R R R R R Bit 7 6 5 4 3 2 1 0 Initial value 0 0 0 0 0 0 0 0 R W R R R R R R R R Bits 31 to 0 Interrupt Request These bits indicate the existence of an interrupt request corresponding to each bit For the correspondence between bits and interrupt source...

Page 839: ...rupt Masks These bits indicate the existence of an interrupt request corresponding to each bit For the correspondence between bits and interrupt sources see section 19 3 7 INTREQ00 INTMSK00 and INTMSKCLR00 Bit Allocation Bits 31 to 0 Description 0 Accept corresponding interrupt request 1 Mask corresponding interrupt request 19 3 6 Interrupt Mask Clear Register 00 INTMSKCLR00 The interrupt mask cle...

Page 840: ...EQ00 INTMSK00 and INTMSKCLR00 Bit Allocation Bits 31 to 0 Description 0 Do not change corresponding interrupt mask 1 Clear corresponding interrupt mask 19 3 7 INTREQ00 INTMSK00 and INTMSKCLR00 Bit Allocation The following shows the relationship between individual bits in the register and interrupt factors Table 19 7 Bit Allocation Bit No Module Interrupt 31 to 10 Reserved Reserved 9 TMU TUNI4 8 TM...

Page 841: ...errupt and sends an interrupt request signal to the CPU 4 The CPU accepts an interrupt at a break between instructions 5 The interrupt source code is set in the interrupt event register INTEVT 6 The status register SR and program counter PC are saved to SSR and SPC respectively 7 The block bit BL mode bit MD and register bank bit RB in SR are set to 1 8 The CPU jumps to the start address of the in...

Page 842: ... Yes No No Yes Yes No Yes No No Yes No Yes Save SR to SSR save PC to SPC Set interrupt source in INTEVT Set BL MD RB bits in SR to 1 Branch to exception handler Interrupt generated BL bit in SR 0 or sleep or standby mode NMI Level 14 interrupt Level 1 interrupt IMASK level 13 or lower IMASK level 0 Yes Level 15 interrupt IMASK level 14 or lower Note IMASK Interrupt mask bits in status register SR ...

Page 843: ...store SSR and SPC from memory 8 Execute the RTE instruction When these procedures are followed in order an interrupt of higher priority than the one being handled can be accepted after clearing BL in step 4 This enables the interrupt response time to be shortened for urgent processing 19 4 3 Interrupt Masking with MAI Bit By setting the MAI bit to 1 in the ICR register it is possible to mask inter...

Page 844: ...bit comparison 1Icyc 4Bcyc 1Icyc 7Bcyc 1Icyc 2Bcyc Wait time until end of sequence being executed by CPU S 1 0 Icyc S 1 0 Icyc S 1 0 Icyc Time from interrupt exception handling save of SR and PC until fetch of first instruction of exception handler is started 4 Icyc 4 Icyc 4 Icyc Response time Total 5Icyc 4Bcyc S 1 Icyc 5Icyc 7Bcyc S 1 Icyc 5Icyc 2Bcyc S 1 Icyc Minimum case 13Icyc 19Icyc 9Icyc Whe...

Page 845: ...d that this may cause the device to malfunction Design the external circuits so that no hazard is input via NMI 2 2 Do not use NMI interrupts Use IRL interrupts instead 3 Workaround using software The above problem can be avoided by inserting the following lines of code 3 4 into the NMI exception handling routine Notes 1 If SR BL is cleared to 0 so that one or more instructions may be executed bet...

Page 846: ...s NMIH 1 Set SR IMASK H F stc SR R1 Store SR mov R1 R0 or H F0 R0 ldc R0 SR 2 Reverse ICR NMIE mov l ICR R3 mov w R3 R2 Store ICR mov w H 0100 R0 xor R2 R0 mov w R0 R3 Write ICR NMIE inverted dummy bra NMIH1 nop pool align 4 NMIH2 mov w R3 R0 dummy read mov w R2 R3 Write ICR NMIE stc SR R0 ldc R0 SR ldc R0 SR ldc R0 SR ldc R0 SR ldc R0 SR ldc R0 SR ldc R0 SR ldc R0 SR ...

Page 847: ...SH7751 Group SH7751R Group Section 19 Interrupt Controller INTC R01UH0457EJ0301 Rev 3 01 Page 793 of 1128 Sep 24 2013 ldc R1 SR Restore SR bra NMIH3 nop NMIH1 bra NMIH2 nop NMIH3 ...

Page 848: ...Section 19 Interrupt Controller INTC SH7751 Group SH7751R Group Page 794 of 1128 R01UH0457EJ0301 Rev 3 01 Sep 24 2013 ...

Page 849: ...r 20 1 1 Features The UBC has the following features Two break channels A and B User break interrupts can be generated on independent conditions for channels A and B or on sequential conditions sequential break setting channel A channel B The following can be set as break compare conditions Address selection of 32 bit virtual address and ASID for comparison Address All bits compared lower 10 bits ...

Page 850: ...ator Data comparator BBRA BARA BASRA BAMRA BBRB BARB BASRB BAMRB BDRB BDMRB BRCR Control User break trap request Legend BBRA Break bus cycle register A BARA Break address register A BASRA Break ASID register A BAMRA Break address mask register A BBRB Break bus cycle register B BARB Break address register B BASRB Break ASID register B BAMRB Break address mask register B BDRB Break data register B B...

Page 851: ... 1F200008 16 Break ASID register A BASRA R W Undefined H FF000014 H 1F000014 8 Break address register B BARB R W Undefined H FF20000C H 1F20000C 32 Break address mask register B BAMRB R W Undefined H FF200010 H 1F200010 8 Break bus cycle register B BBRB R W H 0000 H FF200014 H 1F200014 16 Break ASID register B BASRB R W Undefined H FF000018 H 1F000018 8 Break data register B BDRB R W Undefined H F...

Page 852: ...ster using a floating point memory load instruction When a UBC register is updated use either of the following methods to make the updated value valid 1 Execute an RTE instruction after the memory store instruction that updated the register The updated value will be valid from the RTE instruction jump destination onward 2 Execute instructions requiring 5 states for execution after the memory store...

Page 853: ... R W R W R W Bit 15 14 13 12 11 10 9 8 BAA15 BAA14 BAA13 BAA12 BAA11 BAA10 BAA9 BAA8 Initial value R W R W R W R W R W R W R W R W R W Bit 7 6 5 4 3 2 1 0 BAA7 BAA6 BAA5 BAA4 BAA3 BAA2 BAA1 BAA0 Initial value R W R W R W R W R W R W R W R W R W Note Undefined Break address register A BARA is a 32 bit readable writable register that specifies the virtual address used in the channel A break conditio...

Page 854: ...sed in the channel A break conditions 20 2 4 Break Address Mask Register A BAMRA Bit 7 6 5 4 3 2 1 0 BAMA2 BASMA BAMA1 BAMA0 Initial value 0 0 0 0 R W R R R R R W R W R W R W Note Undefined Break address mask register A BAMRA is an 8 bit readable writable register that specifies which bits are to be masked in the break ASID set in BASRA and the break address set in BARA BAMRA is not initialized by...

Page 855: ...r 16 bits of BARA are masked and not included in break conditions 1 Lower 20 bits of BARA are masked and not included in break conditions 1 Reserved cannot be set Legend Don t care 20 2 5 Break Bus Cycle Register A BBRA Bit 15 14 13 12 11 10 9 8 Initial value 0 0 0 0 0 0 0 0 R W R R R R R R R R Bit 7 6 5 4 3 2 1 0 SZA2 IDA1 IDA0 RWA1 RWA0 SZA1 SZA0 Initial value 0 0 0 0 0 0 0 0 R W R R W R W R W R...

Page 856: ...WA0 These bits specify whether a read cycle or write cycle is used as the bus cycle in the channel A break conditions Bit 3 RWA1 Bit 2 RWA0 Description 0 0 Condition comparison is not performed Initial value 1 Read cycle is used as break condition 1 0 Write cycle is used as break condition 1 Read cycle or write cycle is used as break condition Bits 6 1 and 0 Operand Size Select A SZA2 SZA0 These b...

Page 857: ...s the channel B break address mask register The bit configuration is the same as for BAMRA 20 2 9 Break Data Register B BDRB Bit 31 30 29 28 27 26 25 24 BDB31 BDB30 BDB29 BDB28 BDB27 BDB26 BDB25 BDB24 Initial value R W R W R W R W R W R W R W R W R W Bit 23 22 21 20 19 18 17 16 BDB23 BDB22 BDB21 BDB20 BDB19 BDB18 BDB17 BDB16 Initial value R W R W R W R W R W R W R W R W R W Bit 15 14 13 12 11 10 9...

Page 858: ...5 24 BDMB31 BDMB30 BDMB29 BDMB28 BDMB27 BDMB26 BDMB25 BDMB24 Initial value R W R W R W R W R W R W R W R W R W Bit 23 22 21 20 19 18 17 16 BDMB23 BDMB22 BDMB21 BDMB20 BDMB19 BDMB18 BDMB17 BDMB16 Initial value R W R W R W R W R W R W R W R W R W Bit 15 14 13 12 11 10 9 8 BDMB15 BDMB14 BDMB13 BDMB12 BDMB11 BDMB10 BDMB9 BDMB8 Initial value R W R W R W R W R W R W R W R W R W Bit 7 6 5 4 3 2 1 0 BDMB7...

Page 859: ...ame as for BBRA 20 2 12 Break Control Register BRCR Bit 15 14 13 12 11 10 9 8 CMFA CMFB PCBA Initial value 0 0 0 0 0 0 0 R W R W R W R R R R W R R Bit 7 6 5 4 3 2 1 0 DBEB PCBB SEQ UBDE Initial value 0 0 0 0 0 R W R W R W R R R W R R R W Note Undefined The break control register BRCR is a 16 bit readable writable register that specifies 1 whether channels A and B are to be used as two independent ...

Page 860: ...Bits 13 to 11 Reserved These bits are always read as 0 and should only be written with 0 Bit 10 Instruction Access Break Select A PCBA Specifies whether a channel A instruction access cycle break is to be effected before or after the instruction is executed This bit is not initialized by a power on reset or manual reset Bit 10 PCBA Description 0 Channel A PC break is effected before instruction ex...

Page 861: ...d only be written with 0 Bit 3 Sequence Condition Select SEQ Specifies whether the conditions for channels A and B are to be independent or sequential This bit is not initialized by a power on reset or manual reset Bit 3 SEQ Description 0 Channel A and B comparisons are performed as independent conditions 1 Channel A and B comparisons are performed as sequential conditions channel A channel B Bits...

Page 862: ...al attention PREF OCBP and OCBWB instructions Treated as read accesses MOVCA L and OCBI instructions Treated as write accesses TAS B instruction Treated as one read access and one write access The operand accesses for the PREF OCBP OCBWB and OCBI instructions are accesses with no access data This LSI handles all operand accesses as having a data size The data size can be byte word longword or quad...

Page 863: ...reak ASID registers BASRA BASRB and the address and ASID masking methods in the break address mask registers BAMRA BAMRB If the data bus value is to be included in the break conditions also set the break data in the break data register BDRB and the data mask in the break data mask register BDMRB 2 Set the break bus conditions in the break bus cycle registers BBRA BBRB If even one of the BBRA BBRB ...

Page 864: ... used as a break condition clear the LSB of the break address registers BARA BARB to 0 A break will not be generated if this bit is set to 1 2 When a pre execution break is specified the break is effected when it is confirmed that the instruction is to be fetched and executed Therefore overrun fetched instructions instructions that are fetched but not executed when a branch or exception occurs can...

Page 865: ... is included in break conditions in channel B When a data value is included in the break conditions set the DBEB bit in the break control register BRCR to 1 In this case break data register B BDRB and break data mask register B BDMRB settings are necessary in addition to the address condition A user break interrupt is generated when all three conditions address ASID and data are matched When a qua...

Page 866: ...ruction pre execution break on channel B instruction access TLB miss flag set 20 3 7 Program Counter PC Value Saved 1 When instruction access pre execution is set as a break condition the program counter PC value saved to SPC in user break interrupt handling is the address of the instruction at which the break condition match occurred In this case a user break interrupt is generated and the fetche...

Page 867: ...eak as exception 1 and the exception caused by an instruction between one instruction later and four instructions later as exception 2 memory updating and register updating that essentially cannot be performed by exception 2 cannot be performed is guaranteed irrespective of the existence of exception 1 The program counter value saved is the address of the first instruction for which execution is s...

Page 868: ...perand access will match the break conditions of both channel A and channel B There are no other restrictions For example sequential operation is guaranteed even if two accesses within a single instruction match channel A and channel B conditions in turn 20 3 9 Usage Notes 1 Do not execute a post execution instruction access break for the SLEEP instruction 2 Do not make an operand access break set...

Page 869: ...If channels A and B both match independently at virtually the same time and as a result the SPC value is the same for both user break interrupts only one user break interrupt is generated but both the CMFA bit and the CMFB bit are set For example 110 Instruction post execution instruction break on channel A SPC 112 CMFA 1 112 Instruction pre execution instruction break on channel B SPC 112 CMFB 1 ...

Page 870: ...ug Support Function The user break debug support function enables the processing used in the event of a user break exception to be changed When a user break exception occurs if the UBDE bit is set to 1 in the BRCR register the DBR register value will be used as the branch destination address instead of VBR offset The value of R15 is saved in the SGR register regardless of the value of the UBDE bit...

Page 871: ...terrupt trap Trap Interrupt PC H A0000000 PC VBR vector offset Exception handling routine Execute RTE instruction PC SPC SR SSR SGR R15 EXPEVT H 160 TRA TRAPA imm PC DBR Debug program R15 SGR STC instruction Reset exception BRCR UBDE 1 user break exception End of exception operations INTEVT interrupt code EXPEVT exception code Yes No No Yes Hardware operation Figure 20 2 User Break Debug Support F...

Page 872: ...fter execution of the instruction at address H 00000404 with ASID H 80 or before execution of an instruction at addresses H 00008000 H 000083FE with ASID H 70 Register settings BASRA H 80 BARA H 00037226 BAMRA H 00 BBRA H 0016 BASRB H 70 BARB H 0003722E BAMRB H 00 BBRB H 0016 BDRB H 00000000 BDMRB H 00000000 BRCR H 0008 Conditions set Channel A channel B sequential mode Channel A ASID H 80 address...

Page 873: ...on an even address Operand Access Cycle Break Condition Settings Register settings BASRA H 80 BARA H 00123456 BAMRA H 00 BBRA H 0024 BASRB H 70 BARB H 000ABCDE BAMRB H 02 BBRB H 002A BDRB H 0000A512 BDMRB H 00000000 BRCR H 0080 Conditions set Independent channel A channel B mode Channel A ASID H 80 address H 00123456 address mask H 00 Bus cycle operand access read operand size not included in cond...

Page 874: ...wo dummy reads of STBCR2 Make sure that if an exception or interrupt occurs while performing steps 1 to 5 you do not change the values of these registers in the exception handling routine Do not read or write the following registers while the user break controller clock is stopped BARA BAMRA BBRA BARB BAMRB BBRB BDRB BDMRB and BRCR If these registers are read or written the value cannot be guarant...

Page 875: ...BBRA R1 mov w R0 R1 mov l BBRB R1 mov w R0 R1 2 Initialize BRCR to 0 mov l BRCR R1 mov w R0 R1 3 Dummy read BRCR mov w R1 R0 4 Read STBCR2 then set MSTP5 bit in the read data to 1 and write it back mov l STBCR2 R1 mov b R1 R0 or H 1 R0 mov b R0 R1 5 Twice dummy read STBCR2 mov b R1 R0 mov b R1 R0 Canceling user break controller stopped state 6 Read STBCR2 then clear MSTP5 bit in the read data to 0...

Page 876: ...Section 20 User Break Controller UBC SH7751 Group SH7751R Group Page 822 of 1128 R01UH0457EJ0301 Rev 3 01 Sep 24 2013 ...

Page 877: ...K In this LSI six dedicated emulator pins have been added AUDSYNC AUDCK and AUDATA3 to AUDATA0 The pin functions and serial transfer protocol conform to the JTAG specifications 21 1 2 Block Diagram Figure 21 1 shows a block diagram of the H UDI The TAP test access port controller and control registers are reset independently of the chip reset pin by driving the TRST pin low or setting TMS to 1 and...

Page 878: ...of 1128 R01UH0457EJ0301 Rev 3 01 Sep 24 2013 SDIR SDDRH SDDRL SDBPR MUX TCK ASEBRK BRKACK TMS TRST TDI TDO AUDSYNC AUDCK AUDATA3 0 SDINT Interrupt reset etc TAP controller Break control Decoder Shift register SDBSR Peripheral module bus Trace control Figure 21 1 Block Diagram of H UDI Circuit ...

Page 879: ...fects a reset of the JTAG interface circuit when low TRST must be driven low for a certain period when powering on regardless of whether or not JTAG is used This differs from the IEEE specification 2 3 Data input pin TDI Input The data input pin Data is sent to the H UDI circuit by changing this signal in synchronization with TCK Open 1 Data output pin TDO Output The data output pin Data is sent t...

Page 880: ...eral module clock 21 1 4 Register Configuration Table 21 2 shows the H UDI registers Except for SDBPR and SDBSR these registers are mapped in the control register space and can be referenced by the CPU Table 21 2 H UDI Registers CPU Side H UDI Side Name Abbre viation R W P4 Address Area 7 Address Access Size Initial Value 1 R W Access Size Initial Value 1 Instruction register SDIR R H FFF00000 H 1...

Page 881: ...possible regardless of the CPU mode Operation is undefined if a reserved command is set in this register Bit 15 14 13 12 11 10 9 8 TI7 TI6 TI5 TI4 TI3 TI2 TI1 TI0 Initial value 1 1 1 1 1 1 1 1 R W R R R R R R R R Bit 7 6 5 4 3 2 1 0 Initial value 1 1 1 1 1 1 1 1 R W R R R R R R R R Bits 15 to 8 Test Instruction Bits TI7 TI0 Bit 15 TI7 Bit 14 TI6 Bit 13 TI5 Bit 12 TI4 Bit 11 TI3 Bit 10 TI2 Bit 9 TI...

Page 882: ...it 31 30 29 28 27 26 25 24 Initial value R W R W R W R W R W R W R W R W R W Bit 23 22 21 20 19 18 17 16 Initial value R W R W R W R W R W R W R W R W R W Bit 15 14 13 12 11 10 9 8 Initial value R W R W R W R W R W R W R W R W R W Bit 7 6 5 4 3 2 1 0 Initial value R W R W R W R W R W R W R W R W R W Note Undefined Bits 31 to 0 DR Data These bits store the SDDR value 21 2 3 Bypass Register SDBPR Th...

Page 883: ...pt handler This register is initialized by TRST or when in the Test Logic Reset state Bit 15 14 13 12 11 10 9 8 Initial value 0 0 0 0 0 0 0 0 R W R R R R R R R R Bit 7 6 5 4 3 2 1 0 INTREQ Initial value 0 0 0 0 0 0 0 0 R W R R R R R R R R W Bits 15 to 1 Reserved These bits always read as 0 and should only be written with 0 Bit 0 Interrupt Request Bit INTREQ Shows the existence of an interrupt requ...

Page 884: ...gister No Pin name Type to TDO 418 CS0 OUT 417 CS0 CTL 416 CS1 OUT 415 CS1 CTL 414 CS4 OUT 413 CS4 CTL 412 CS5 OUT 411 CS5 CTL 410 CS6 OUT 409 CS6 CTL 408 BS OUT 407 BS CTL 406 WE0 REG OUT 405 WE0 REG CTL 404 WE1 OUT 403 WE1 CTL 402 D0 OUT 401 D0 CTL 400 D0 IN 399 D1 OUT 398 D1 CTL 397 D1 IN 396 D2 OUT 395 D2 CTL 394 D2 IN 393 D3 OUT 392 D3 CTL 391 D3 IN 390 D4 OUT 389 D4 CTL ...

Page 885: ...IN 387 D5 OUT 386 D5 CTL 385 D5 IN 384 D6 OUT 383 D6 CTL 382 D6 IN 381 D7 OUT 380 D7 CTL 379 D7 IN 378 D8 OUT 377 D8 CTL 376 D8 IN 375 D9 OUT 374 D9 CTL 373 D9 IN 372 D10 OUT 371 D10 CTL 370 D10 IN 369 D11 OUT 368 D11 CTL 367 D11 IN 366 D12 OUT 365 D12 CTL 364 D12 IN 363 D13 OUT 362 D13 CTL 361 D13 IN 360 D14 OUT 359 D14 CTL 358 D14 IN 357 D15 OUT 356 D15 CTL ...

Page 886: ...0 DQM0 CTL 352 CAS1 DQM1 OUT 351 CAS1 DQM1 CTL 350 RD WR OUT 349 RD WR CTL 348 RD CASS FRAME OUT 347 RD CASS FRAME CTL 346 CKE OUT 345 CKE CTL 344 RAS OUT 343 RAS CTL 342 CS2 OUT 341 CS2 CTL 340 CS3 OUT 339 CS3 CTL 338 A0 OUT 337 A0 CTL 336 A1 OUT 335 A1 CTL 334 A2 OUT 333 A2 CTL 332 A3 OUT 331 A3 CTL 330 A4 OUT 329 A4 CTL 328 A5 OUT 327 A5 CTL 326 A6 OUT 325 A6 CTL 324 A7 OUT 323 A7 CTL ...

Page 887: ...OUT 319 A9 CTL 318 A10 OUT 317 A10 CTL 316 A11 OUT 315 A11 CTL 314 A12 OUT 313 A12 CTL 312 A13 OUT 311 A13 CTL 310 A14 OUT 309 A14 CTL 308 A15 OUT 307 A15 CTL 306 A16 OUT 305 A16 CTL 304 A17 OUT 303 A17 CTL 302 CAS2 DQM2 OUT 301 CAS2 DQM2 CTL 300 CAS3 DQM3 OUT 299 CAS3 DQM3 CTL 298 D16 OUT 297 D16 CTL 296 D16 IN 295 D17 OUT 294 D17 CTL 293 D17 IN 292 D18 OUT 291 D18 CTL 290 D18 IN ...

Page 888: ... D19 CTL 287 D19 IN 286 D20 OUT 285 D20 CTL 284 D20 IN 283 D21 OUT 282 D21 CTL 281 D21 IN 280 D22 OUT 279 D22 CTL 278 D22 IN 277 D23 OUT 276 D23 CTL 275 D23 IN 274 D24 OUT 273 D24 CTL 272 D24 IN 271 D25 OUT 270 D25 CTL 269 D25 IN 268 D26 OUT 267 D26 CTL 266 D26 IN 265 D27 OUT 264 D27 CTL 263 D27 IN 262 D28 OUT 261 D28 CTL 260 D28 IN 259 D29 OUT 258 D29 CTL 257 D29 IN ...

Page 889: ... 252 D31 CTL 251 D31 IN 250 A18 OUT 249 A18 CTL 248 A19 OUT 247 A19 CTL 246 A20 OUT 245 A20 CTL 244 A21 OUT 243 A21 CTL 242 A22 OUT 241 A22 CTL 240 A23 OUT 239 A23 CTL 238 A24 OUT 237 A24 CTL 236 A25 OUT 235 A25 CTL 234 WE2 ICIORD OUT 233 WE2 ICIORD CTL 232 WE3 ICIOWR OUT 231 WE3 ICIOWR CTL 230 SLEEP IN 229 PCIGNT4 OUT 228 PCIGNT4 CTL 227 PCIGNT3 OUT 226 PCIGNT3 CTL 225 PCIGNT2 OUT 224 PCIGNT2 CTL...

Page 890: ...TL 218 PCIREQ3 MD10 IN 217 PCIREQ2 MD9 OUT 216 PCIREQ2 MD9 CTL 215 PCIREQ2 MD9 IN 214 IDSEL IN 213 INTA OUT 212 INTA CTL 211 PCIRST OUT 210 PCIRST CTL 209 PCICLK IN 208 PCIGNT1 REQOUT OUT 207 PCIGNT1 REQOUT CTL 206 PCIREQ1 GNTIN OUT 205 PCIREQ1 GNTIN CTL 204 PCIREQ1 GNTIN IN 203 SERR OUT 202 SERR CTL 201 SERR IN 200 AD31 OUT 199 AD31 CTL 198 AD31 IN 197 AD30 OUT 196 AD30 CTL 195 AD30 IN 194 AD29 O...

Page 891: ... OUT 187 AD27 CTL 186 AD27 IN 185 AD26 OUT 184 AD26 CTL 183 AD26 IN 182 AD25 OUT 181 AD25 CTL 180 AD25 IN 179 AD24 OUT 178 AD24 CTL 177 AD24 IN 176 C BE3 OUT 175 C BE3 CTL 174 C BE3 IN 173 AD23 OUT 172 AD23 CTL 171 AD23 IN 170 AD22 OUT 169 AD22 CTL 168 AD22 IN 167 AD21 OUT 166 AD21 CTL 165 AD21 IN 164 AD20 OUT 163 AD20 CTL 162 AD20 IN 161 AD19 OUT 160 AD19 CTL 159 AD19 IN 158 AD18 OUT ...

Page 892: ... 153 AD17 IN 152 AD16 OUT 151 AD16 CTL 150 AD16 IN 149 C BE2 OUT 148 C BE2 CTL 147 C BE2 IN 146 PCIFRAME OUT 145 PCIFRAME CTL 144 PCIFRAME IN 143 IRDY OUT 142 IRDY CTL 141 IRDY IN 140 TRDY OUT 139 TRDY CTL 138 TRDY IN 137 DEVSEL OUT 136 DEVSEL CTL 135 DEVSEL IN 134 PCISTOP OUT 133 PCISTOP CTL 132 PCISTOP IN 131 PCILOCK OUT 130 PCILOCK CTL 129 PCILOCK IN 128 PERR OUT 127 PERR CTL 126 PERR IN 125 PA...

Page 893: ... C BE1 OUT 121 C BE1 CTL 120 C BE1 IN 119 AD15 OUT 118 AD15 CTL 117 AD15 IN 116 AD14 OUT 115 AD14 CTL 114 AD14 IN 113 AD13 OUT 112 AD13 CTL 111 AD13 IN 110 AD12 OUT 109 AD12 CTL 108 AD12 IN 107 AD11 OUT 106 AD11 CTL 105 AD11 IN 104 AD10 OUT 103 AD10 CTL 102 AD10 IN 101 AD9 OUT 100 AD9 CTL 99 AD9 IN 98 AD8 OUT 97 AD8 CTL 96 AD8 IN 95 C BE0 OUT 94 C BE0 CTL 93 C BE0 IN 92 AD7 OUT ...

Page 894: ...0 AD7 IN 89 AD6 OUT 88 AD6 CTL 87 AD6 IN 86 AD5 OUT 85 AD5 CTL 84 AD5 IN 83 AD4 OUT 82 AD4 CTL 81 AD4 IN 80 AD3 OUT 79 AD3 CTL 78 AD3 IN 77 AD2 OUT 76 AD2 CTL 75 AD2 IN 74 AD1 OUT 73 AD1 CTL 72 AD1 IN 71 AD0 OUT 70 AD0 CTL 69 AD0 IN 68 IRL0 IN 67 IRL1 IN 66 IRL2 IN 65 IRL3 IN 64 NMI IN 63 BACK BSREQ OUT 62 BACK BSREQ CTL 61 BREQ BSACK IN 60 MD6 IOIS16 IN 59 RDY IN ...

Page 895: ...XD IN 53 TCLK OUT 52 TCLK CTL 51 TCLK IN 50 RTS2 MD8 OUT 49 RTS2 MD8 CTL 48 RTS2 MD8 IN 47 SCK OUT 46 SCK CTL 45 SCK IN 44 MD1 TXD2 OUT 43 MD1 TXD2 CTL 42 MD1 TXD2 IN 41 MD0 SCK2 OUT 40 MD0 SCK2 CTL 39 MD0 SCK2 IN 38 MD7 CTS2 OUT 37 MD7 CTS2 CTL 36 MD7 CTS2 IN 35 AUDSYNC OUT 34 AUDSYNC CTL 33 AUDCK OUT 32 AUDCK CTL 31 AUDATA0 OUT 30 AUDATA0 CTL 29 AUDATA1 OUT 28 AUDATA1 CTL 27 AUDATA2 OUT 26 AUDAT...

Page 896: ...OUT 22 MD3 CE2A CTL 21 MD3 CE2A IN 20 MD4 CE2B OUT 19 MD4 CE2B CTL 18 MD4 CE2B IN 17 MD5 OUT 16 MD5 CTL 15 MD5 IN 14 DACK0 OUT 13 DACK0 CTL 12 DACK1 OUT 11 DACK1 CTL 10 DRAK0 OUT 9 DRAK0 CTL 8 DRAK1 OUT 7 DRAK1 CTL 6 STATUS0 OUT 5 STATUS0 CTL 4 STATUS1 OUT 3 STATUS1 CTL 2 DREQ0 IN 1 DREQ1 IN from TDI Note CTL is a low active signal The relevant pin is driven to the OUT state when CTL is set LOW ...

Page 897: ... at the rising edge of TCK and shifted at the falling edge The TDO value changes at the falling edge of TCK When not in the Shift DR or Shift IR state TDO is in the high impedance state In a transition to TRST 0 a transition is made to the Test Logic Reset state asynchronously with respect to TCK 1 0 0 0 Run Test Idle Select DR Scan Capture DR Shift DR Exit1 DR Pause DR Exit2 DR Update DR Test Log...

Page 898: ... 21 3 3 H UDI Interrupt The H UDI interrupt function generates an interrupt by setting a command value in SDIR from the H UDI The H UDI interrupt is of general exception interrupt operation type with a branch to an address based on VBR and return effected by means of an RTE instruction The exception code stored in control register INTEVT in this case is H 600 The priority of the H UDI interrupt ca...

Page 899: ...er tOSC1 the power on oscillation stabilization time has elapsed The clock signal need not be supplied to the EXTAL pin after tOSC1 has elapsed For details on tOSC1 the power on oscillation stabilization time see section 23 Electrical Characteristics 21 4 Usage Notes 1 SDIR Command Once an SDIR command is set it does not change until another command is written from the H UDI unless initialized by ...

Page 900: ...Section 21 High performance User Debug Interface H UDI SH7751 Group SH7751R Group Page 846 of 1128 R01UH0457EJ0301 Rev 3 01 Sep 24 2013 ...

Page 901: ... PCI master devices running at 33 MHz or one PCI master device at 66 MHz can be connected Arbitration control is available as a PCI host function Can operate as master or target When operating as master PIO and DMA transfer are available Four DMA transfer channels Six 32 bit x 16 longword internal FIFO one for target reading one for target writing and four for DMA transfer Asynchronous operation o...

Page 902: ...s PCI configuration register PCI bus interface Internal peripheral module bus interface Local register FIFO 32B 2 sides 6 Data transfer control Local register Bus request Acknowledge Local register PCIC bus controller PCI clock 33 66 MHz PCICLK Local bus Feedback input clock from CKIO Local bus clock Bck cycle Bcyc Interrupts PCIC module Internal peripheral module bus Peripheral bus Figure 22 1 PC...

Page 903: ...eset 4 C BE3 to C BE0 C BE 3 0 Command byte enable t s O I O I Low level output at reset 5 PAR PAR Parity t s I O I O I O I O Low level output at reset 6 PCIFRAME FRAME Bus cycle s t s Yes O I O I 7 IRDY IRDY Initiator ready s t s Yes O I O I 8 TRDY TRDY Target ready s t s Yes I O I O 9 PCISTOP STOP Transaction stop s t s Yes I O I O 10 PCILOCK LOCK Exclusive access control s t s Yes O I O I 11 DE...

Page 904: ...e o d Open drain t s Try state Notes 1 Terminal provided with a pull up resistor 2 The values of external pins are sampled in a power on reset by means of the RESET pin 3 Pull down this pin to low level when IDSEL is not in use If a configuration access to an external PCI device occurs while IDSEL is high level the PCIC itself may respond 22 1 4 Register Configuration The PCIC has the PCI configur...

Page 905: ...H FE20001C H 1E20001C 32 PCI configuration register 8 PCICONF8 R R H 00000000 H 20 H FE200020 H 1E200020 32 PCI configuration register 9 PCICONF9 R R H 00000000 H 24 H FE200024 H 1E200024 32 PCI configuration register 10 PCICONF10 R R H 00000000 H 28 H FE200028 H 1E200028 32 PCI configuration register 11 PCICONF11 R R W H xxxxxxxx H 2C H FE20002C H 1E20002C 32 PCI configuration register 12 PCICONF...

Page 906: ...ress local address area 1 Base address local address area 1 Base address local address area 1 R W R W H 1C H FE20001C H 1E20001C Reserved Reserved Reserved Reserved R R H 20 H FE200020 H 1E200020 Reserved Reserved Reserved Reserved R R H 24 H FE200024 H 1E200024 Reserved Reserved Reserved Reserved R R H 28 H FE200028 H 1E200028 Reserved Reserved Reserved Reserved R R H 2C H FE20002C H 1E20002C Sub...

Page 907: ...18 H 1E200118 32 Error address data register for PCI PCIALR R R H xxxxxxxx H 11C H 1C H FE20011C H 1E20011C 32 Error command data register for PCI PCICLR R R H 0000000x H 120 H 20 H FE200120 H 1E200120 32 Reserved H 00000000 H 124 to H 12C H 24 to H 2C H FE200124 to H FE20012C H 1E200124 to H 1E20012C 32 PCI arbiter interrupt register PCIAINT R W R W H 00000000 H 130 H 30 H FE200130 H 1E200130 32 ...

Page 908: ...g address register 2 for PCI PCIDLA2 R W R W H 00000000 H 1A4 H A4 H FE2001A4 H 1E2001A4 32 DMA transfer count register 2 for PCI PCIDTC2 R W R W H 00000000 H 1A8 H A8 H FE2001A8 H 1E2001A8 32 DMA control register 2 for PCI PCIDCR2 R W R W H 00000000 H 1AC H AC H FE2001AC H 1E2001AC 32 DMA transfer PCI address register 3 for PCI PCIDPA3 R W R W H 00000000 H 1B0 H B0 H FE2001B0 H 1E2001B0 32 DMA tr...

Page 909: ...001EC 32 PCI wait control register 3 PCIWCR3 R W H 07777777 H FE2001F0 H 1E2001F0 32 PCIC discrete memory control register PCIMCR R W H 00000000 H FE2001F4 H 1E2001F4 32 PCIC bus control register 3 1 PCIBCR3 R W H 00000001 H FE2001F8 H 1E2001F8 32 Reserved H 00000000 H FE2001FC H 1E2001FC 32 Port control register PCIPCTR R W H 00000000 H FE200200 H 1E200200 32 Port data register PCIPDTR R W H 0000...

Page 910: ... Bit 15 14 13 12 11 10 9 8 VNDID15 VNDID14 VNDID13 VNDID12 VNDID11 VNDID10 VNDID9 VNDID8 Initial value 0 0 0 1 0 0 0 0 PCI R W R R R R R R R R PP Bus R W R R R R R R R R Bit 7 6 5 4 3 2 1 0 VNDID7 VNDID6 VNDID5 VNDID4 VNDID3 VNDID2 VNDID1 VNDID0 Initial value 0 1 0 1 0 1 0 0 PCI R W R R R R R R R R PP Bus R W R R R R R R R R Note These values differ between SH7751 and SH7751R PCI configuration reg...

Page 911: ... information on these products contact Renesas Electronics Corp 22 2 2 PCI Configuration Register 1 PCICONF1 Bit 31 30 29 28 27 26 25 24 DPE SSE RMA RTA STA DEV1 DEV0 DPD Initial value 0 0 0 0 0 0 1 0 PCI R W R WC R WC R WC R WC R WC R R R WC PP Bus R W R WC R WC R WC R WC R WC R R R WC Bit 23 22 21 20 19 18 17 16 FBBC UDF 66M PM Initial value 1 0 0 1 0 0 0 0 PCI R W R R R R R R R R PP Bus R W R R...

Page 912: ...e to this register before initiating transfers on the PCI bus Bit 31 Parity Error Detection Status DPE Indicates the detection of a parity error in read data when the PCIC is operating as the master or a party error in write data when the PCIC is operating as a target Bit 31 DPE Description 0 No parity error detected by device Initial value 1 Parity error detected by device Set this bit regardless...

Page 913: ... Bit 27 STA Description 0 No transaction termination using target abort by target device Initial value 1 Transaction termination by target abort by target device Notification by target device Bits 26 and 25 DEVSEL Timing Status DEV1 and 0 These bits indicate the DEVSEL response timing when the PCIC is operating as a target Bit 26 DEV1 Bit 25 DEV0 Description 0 0 High speed not supported 1 Medium s...

Page 914: ...unctions Initial value 1 This device supports user functions Bit 21 66 MHz Operating Status 66M Shows whether 66 MHz operation is supported Bit 21 66M Description 0 This device supports 33 MHz operation Initial value 1 This device supports 66 MHz operation Bit 20 PCI Power Management PM Shows whether the PCI power management is supported Bit 20 PM Description 0 Power management not supported 1 Pow...

Page 915: ... Enable address data stepping control Initial value Bit 6 Parity Error Response PER Controls the device response when a parity error is detected or a parity error report is received PERR is asserted only when PER 1 Bit 6 PER Description 0 Ignore detected parity errors Initial value 1 Respond to detected parity error Bit 5 VGA Pallet Snoop Control VPS Bit 5 VPS Description 0 VGA compatible device I...

Page 916: ...ter operation Initial value 1 Enable bus master operation Bit 1 Memory Space Control MES Controls the access to the memory space when the PCIC is operating as a target When this bit is 0 all memory transfers to the PCIC are terminated by master abort Bit 1 MES Description 0 Disable access to memory space Initial value 1 Enable access to memory space Bit 0 I O Space Control IOS Controls the access ...

Page 917: ... R R R R R R R PP Bus R W R W R W R W R W R W R W R W R W Bit 7 6 5 4 3 2 1 0 REVID7 REVID6 REVID5 REVID4 REVID3 REVID2 REVID1 REVID0 Initial value PCI R W R R R R R R R R PP Bus R W R R R R R R R R Note Initial values vary with the logic versions of the chip The PCI configuration register 2 PCICONF2 is a 32 bit read partial write register that includes the class code and revision ID PCI configura...

Page 918: ...r H 06 Bridge device H 07 Simple communication device H 08 Basic peripheral device H 09 Input device H 0A Docking station H 0B Processor H 0C Serial bus controller H 0D to H FE Reserved H FF Device not categorized in defined class Bits 23 to 16 Sub Class Codes CLASS15 to 8 Shows the subclass code For details please see appendix D Pin Functions of the PCI Local Bus Specifications Revision 2 1 Bits ...

Page 919: ...us R W R W R W R W R W R W R W R W R W Bit 7 6 5 4 3 2 1 0 CACHE7 CACHE6 CACHE5 CACHE4 CACHE3 CACHE2 CACHE1 CACHE0 Initial value 0 0 0 0 0 0 0 0 PCI R W R R R R R R R R PP Bus R W R R R R R R R R The PCI configuration register 3 PCICONF3 is a 32 bit read partial write register that includes the BIST function header type latency timer and cache line size PCI configuration registers stipulated in th...

Page 920: ... to 24 BIST3 to 0 BIST status on completion of operation Bits 27 to 24 BIST3 to 0 Description H 0 Passed test Initial value H 1 to H F Test failed not supported Bit 23 Multifunction Status HEAD7 Shows whether the device is a multi function unit or a single function unit Bit 23 HEAD7 Description 0 Single function device Initial value 1 Device has between 2 and 8 functions not supported Bits 22 to 1...

Page 921: ...Bit 23 22 21 20 19 18 17 16 BASE23 BASE22 BASE21 BASE20 BASE19 BASE18 BASE17 BASE16 Initial value 0 0 0 0 0 0 0 0 PCI R W R W R W R W R W R W R W R W R W PP Bus R W R W R W R W R W R W R W R W R W Bit 15 14 13 12 11 10 9 8 BASE15 BASE14 BASE13 BASE12 BASE11 BASE10 BASE9 BASE8 Initial value 0 0 0 0 0 0 0 0 PCI R W R W R W R W R W R W R W R W R W PP Bus R W R W R W R W R W R W R W R W R W Bit 7 6 5 ...

Page 922: ...751R bits 31 to 8 are writable and bits 7 to 2 and 0 are fixed by the hardware The PCICONF4 register is initialized to H 00000001 at a power on reset and software reset Always write to this register prior to executing I O transfers accessing the local registers in the PCIC to or from the PCIC from the PCI bus Bits 31 to 8 Base Address of the I O Space BASE 31 to 8 Sets the base address of the loca...

Page 923: ...alue 0 0 0 0 0 0 0 0 PCI R W R R R R R R R R PP Bus R W R R R R R R R R Bit 7 6 5 4 3 2 1 0 BASE07 BASE06 BASE05 BASE04 LA0PREF LA0TYPE1 LA0TYPE0 LA0ASI Initial value 0 0 0 0 0 0 0 0 PCI R W R R R R R R R R PP Bus R W R R R R R R R R The PCI configuration register 5 PCICONF5 is a 32 bit read partial write register that accommodates the memory space base address PCI configuration register stipulate...

Page 924: ... 31 to 20 Base Address of the Memory Space 0 BASE0 31 to 20 These bits specify the base address of the local address space 0 this LSI external bus space Bits 19 to 4 Base Address of the Memory Space 0 BASE0 19 to 4 Fixed at H 0000 in hardware Bit 3 Pre fetch Control LA0PREF Shows availability of prefetching of the local address space 0 Bit 3 LA0PREF Description 0 Prefetch disabled Initial value 1 ...

Page 925: ... R W R W R W R W Bit 23 22 21 20 19 18 17 16 BASE123 BASE122 BASE121 BASE120 BASE119 BASE118 BASE117 BASE116 Initial value 0 0 0 0 0 0 0 0 PCI R W R W R W R W R W R R R R PP Bus R W R W R W R W R W R R R R Bit 15 14 13 12 11 10 9 8 BASE115 BASE114 BASE113 BASE112 BASE111 BASE110 BASE19 BASE18 Initial value 0 0 0 0 0 0 0 0 PCI R W R R R R R R R R PP Bus R W R R R R R R R R Bit 7 6 5 4 3 2 1 0 BASE1...

Page 926: ...0 Register Value Required Address Space Valid BASE1 31 20 Write Bits B 0_0000_0000 1 MB Bits 31 to 20 B 0_0000_0001 2 MB Bits 31 to 21 B 0_0000_0011 4 MB Bits 31 to 22 B 0_1111_1111 256 MB Bits 31 to 28 B 1_1111_1111 512 MB Bits 31 to 29 The PCICONF6 register is initialized to H 00000000 at a power on reset and software reset Always write to this register prior to transferring data to or from the ...

Page 927: ...pported 1 0 The base address has 64 bit width not supported 1 Reserved Bit 0 Address Space Indicator LA1ASI Shows whether the base address specified by this register is an I O space or memory space Bit 0 LA1ASI Description 0 Memory space Initial value 1 I O space 22 2 8 PCI Configuration Register 7 PCICONF7 to PCI Configuration Register 10 PCICONF10 Bit 31 30 29 11 10 9 8 Initial value 0 0 0 0 0 0...

Page 928: ... PP Bus R W R W R W R W R W R W R W R W R W Bit 7 6 5 4 3 2 1 0 SVID7 SVID6 SVID5 SVID4 SVID3 SVID2 SVID1 SVID0 Initial value PCI R W R R R R R R R R PP Bus R W R W R W R W R W R W R W R W R W The PCI configuration register 11 PCICONF11 is a 32 bit read write register that accommodates the subsystem ID and subsystem vendor ID PCI configuration registers stipulated in the PCI local bus specificatio...

Page 929: ... to 0 Reserved These bits are always read as 0 22 2 11 PCI Configuration Register 13 PCICONF13 Bit 31 30 29 11 10 9 8 Initial value 0 0 0 0 0 0 0 PCI R W R R R R R R R PP Bus R W R R R R R R R Bit 7 6 5 4 3 2 1 0 CAPPTR7 CAPPTR6 CAPPTR5 CAPPTR4 CAPPTR3 CAPPTR2 CAPPTR1 CAPPTR0 Initial value 0 1 0 0 0 0 0 0 PCI R W R R R R R R R R PP Bus R W R R R R R R R R The PCI configuration register 13 PCICONF1...

Page 930: ...to 0 These bits specify the address offset of the extended functions power management The initial value is H 40 fixed 22 2 12 PCI Configuration Register 14 PCICONF14 Bit 31 30 29 11 10 9 8 Initial value 0 0 0 0 0 0 0 PCI R W R R R R R R R PP Bus R W R R R R R R R Bit 7 6 5 4 3 2 1 0 Initial value 0 0 0 0 0 0 0 0 PCI R W R R R R R R R R PP Bus R W R R R R R R R R Bits 31 to 0 Reserved These bits ar...

Page 931: ...R R R R R R R Bit 7 6 5 4 3 2 1 0 ILIN7 ILIN6 ILIN5 ILIN4 ILIN3 ILIN2 ILIN1 ILIN0 Initial value 0 0 0 0 0 0 0 0 PCI R W R W R W R W R W R W R W R W R W PP Bus R W R W R W R W R W R W R W R W R W The PCI configuration register 15 PCICONF15 is a 32 bit read partial write register that accommodates the maximum latency minimum grant interrupt pin and interrupt line PCI configuration registers stipulat...

Page 932: ... the privileges not supported Bits 23 to 16 Minimum Latency Specification MGNT 7 to 0 Specify the burst interval required by the PCI device not supported Bits 15 to 8 Interrupt Pin Specification IPIN7 to 0 Bits 15 to 8 IPIN7 to 0 Description H 01 INTA used Initial value H 02 INTB used H 03 INTC used H 04 INTD used H 05 to H FF Reserved bits Bits 7 to 0 Interrupt Line Specification ILIN7 to 0 Speci...

Page 933: ...D2 CAPID1 CAPID0 Initial value 0 0 0 0 0 0 0 1 PCI R W R R R R R R R R PP Bus R W R R R R R R R R The PCI configuration register 16 PCICONF16 is a 32 bit read partial write register than accommodates the power management function PMC next item pointer and extended function ID power management registers stipulated in the PCI power management specifications PCICONF16 is valid only when the PCIC is f...

Page 934: ...s return 0 when read Always write 0 to these bits Bit 21 DSI Specifies whether bit device specific initialization is required Bit 20 Reserved This bit always returns 0 when read Always write 0 to this bit Bit 19 PME Clock PMECLK Not supported Specifies whether a clock is required for PME support Bits 18 to 16 Version VER2 to 0 Specify the version of power management specifications Bits 15 to 8 Nex...

Page 935: ... R R R R R R Bit 7 6 5 4 3 2 1 0 PWRST1 PWRST0 Initial value 0 0 0 0 0 0 0 0 PCI R W R R R R R R R W R W PP Bus R W R R R R R R R W R W The PCI configuration register 17 PCICONF17 is a 32 bit read partial write register that accommodates the power management control status PMCSR bridge compatible PMCSR extended PMCSR_BSE and data power management registers stipulated in the PCI power management sp...

Page 936: ...ead Always write 0 to these bits Bit 15 PME Status PMEST Not supported Shows the status of the PME bit This bit is set when the signal is output Bits 14 and 13 Data Scale DTATSCL1 to 0 Not supported These bits specify the scaling value for the data field value Bits 12 to 9 Data Select DATASEL3 to 0 Not supported Select the value to be output to the data field Bit 8 PME Enable PMEEN Not supported C...

Page 937: ...ea Reserved area Bit 31 30 29 11 10 9 8 Initial value 0 0 0 0 0 0 0 PCI R W R R R R R R R PP Bus R W R R R R R R R Bit 7 6 5 4 3 2 1 0 Initial value 0 0 0 0 0 0 0 0 PCI R W R R R R R R R R PP Bus R W R R R R R R R R Note PCI configuration addresses H 48 to H FC are reserved Bits 31 to 0 Reserved These bits always return 0 when read ...

Page 938: ...STCTL CFINIT Initial value 0 0 0 1 0 1 0 0 0 0 PCI R W R R R R R R R R PP Bus R W R W R W R R R W R W R W R W Note The value of the external pin is sampled in a power on reset by means of the RESET pin The PCI control register PCICR is a 32 bit register that monitors the status of the mode pin at initialization and controls the basic operation of the PCIC Bits 5 MD10 and 4 MD9 are read only bits f...

Page 939: ...ead buffer 32 bytes or two target read buffers 64 bytes are used for target memory read access to the PCIC When two target read buffers faces are used the data from two buffers are read via the local bus in advanced Bit 9 TRDSGL Description 0 Use 2 target read buffers Initial value 1 Use 1 target read buffer only Bit 8 Data Byte Swap BYTESWAP Specifies whether the data byte is swapped when the PCI...

Page 940: ...on reset by means of the RESET pin Bit 5 MD10 Description 0 Host bridge function arbitration enabled 1 Host bridge function disabled Bit 4 Mode 9 Pin Monitor MD9 Monitors the PCIREQ2 MD9 pin value in a power on reset by means of the RESET pin Bit 4 MD9 Description 0 PCICLK used as PCI clock 1 Feedback input clock from CKIO used as PCI clock Bit 3 SERR Output SERR Software control of SERR output Th...

Page 941: ...r on reset Do not use the field when the PCIC is non host Bit 1 PCIRST Description 0 Negate PCIRST High output Initial value 1 Assert PCIRST Low output Bit 0 PCIC Internal Register Initialization Control Bit CFINIT After the SH initializes the PCI registers setting this bit enables access from the PCI bus During initialization no bus privileges are granted to other devices on the PCI bus while ope...

Page 942: ... 7 6 5 4 3 2 1 0 Initial value 0 0 0 0 0 0 0 0 PCI R W R R R R R R R R PP Bus R W R R R R R R R R The PCI local space register 1 0 PCILSR 1 0 specifies the capacities of the two local address spaces address space 0 and address space 1 supported when a device on the PCI bus performs a memory read memory write of the PCIC using target transfers This is a 32 bit register that can be read and written ...

Page 943: ...iguration Register 5 PCICONF5 Bits 31 to 29 Reserved These bits always return 0 when read Always write 0 to these bits when writing Bits 28 to 20 Capacities of the Local Address Spaces 0 1 PLSR28 to 20 These bits specify the capacities of the address space 0 and address space 1 in bytes Specifying capacity 1 bytes A 1MB space is secured if all zeros are specified Bits 19 to 0 Reserved These bits a...

Page 944: ...CI R W R R R R R R R R PP Bus R W R R R R R R R R The PCI local address register 1 0 PCILAR 1 0 specifies the starting address external address of local bus of the two local address spaces address space 0 and address space 1 supported when performing memory read memory write operations due to target transfers to the PCIC It is a 32 bit register that can be read and written from the PP bus and is r...

Page 945: ...to this register prior to target transfers Specify the starting address physical address of the memory installed on the local bus according to the address space being used Bits 28 to 26 of the PCI local address register 0 select the local address area Bits 25 to 20 show the address within that area Bits 31 to 29 Reserved These bits always return 0 when read Always write 0 to these bits Bits 28 to ...

Page 946: ...T_DPER R_WT T_PERR_ DET M_TGT_A BORT M_MST_ ABORT M_DPER R_WT M_DPER R_RD Initial value 0 0 0 0 0 0 0 0 PCI R W R WC R WC R WC R WC R WC R WC R WC R WC PP Bus R W R WC R WC R WC R WC R WC R WC R WC R WC Note WC Cleared by writing 1 Writing of 0 is ignored The PCI interrupt register PCIINT is a 32 bit register that saves the error source when an error occurs on the PCI bus as a result of the PCIC a...

Page 947: ... combination illegal byte enable during I O transfer Bits 13 to 10 Reserved These bits always return 0 when read Always write 0 to these bits Bit 9 Target Memory Read Retry Timeout Interrupt TGT_RETRY When the PCIC is target the master did not attempt a retry within the prescribed number of PCI bus clocks 215 detected only in the case of memory read operations Bit 8 Master Function Disable Error I...

Page 948: ... M_MST_ABORT When the PCIC is master Indicates the termination of transaction by master abort Bit 1 Master Write PERR Detection Interrupt M_DPERR_WT When the PCIC is master PERR received from the target while writing data to the target Detects only when bit 6 PER of the PCICONF1 is 1 Bit 0 Master Read Data Parity Error Interrupt M_DPERR_RD When the PCIC is master a parity error was detected during...

Page 949: ... R W R W R R R R R W R W PP Bus R W R W R W R R R R R W R W Bit 7 6 5 4 3 2 1 0 ADRPER R SERR_D ET T_DPER R_WT T_PERR_ DET M_TGT_A BORT M_MST_ ABORT M_DPER R_WT M_DPER R_RD Initial value 0 0 0 0 0 0 0 0 PCI R W R W R W R W R W R W R W R W R W PP Bus R W R W R W R W R W R W R W R W R W The PCI interrupt mask register PCIINTM sets the respective interrupt masks for the interrupts generated when erro...

Page 950: ...e 0 to these bits Bit 9 Target Retry Timeout Interrupt Mask TGT_RETRY Bit 8 Master Function Disable Error Interrupt Mask MST_DIS Bit 7 Address Parity Error Detection Interrupt Mask ADRPERR Bit 6 SERR Detection Interrupt Mask SERR_DET Bit 5 Target Write Data Parity Error Interrupt Mask T_DPERR_WT Bit 4 Target Read PERR Detection Interrupt Mask T_PERR_DET Bit 3 Master Target Abort Interrupt Mask M_T...

Page 951: ...nitial value PCI R W R R R R R R R R PP Bus R W R R R R R R R R Bit 7 6 5 4 3 2 1 0 ALOG7 ALOG6 ALOG5 ALOG4 ALOG3 ALOG2 ALOG1 ALOG0 Initial value PCI R W R R R R R R R R PP Bus R W R R R R R R R R The PCI address data register at error PCIALR stores the PCI address data ALOG 31 0 of errors that occur on the PCI bus It is a 32 bit register that can be read from both the PP bus and PCI bus The PCIAL...

Page 952: ...15 14 13 12 11 10 9 8 Initial value 0 0 0 0 0 0 0 0 PCI R W R R R R R R R R PP Bus R W R R R R R R R R Bit 7 6 5 4 3 2 1 0 CMDLOG3 CMDLOG2 CMDLOG1 CMDLOG0 Initial value 0 0 0 0 PCI R W R R R R R R R R PP Bus R W R R R R R R R R The PCI command data register at error PCICLR stores the type of transfer MSTPIO MSTDMA0 MSTDMA1 MSTDMA2 MSTDMA3 or TGT when an error occurs on the PCI bus and the PCI comm...

Page 953: ...ccurred in PIO transfer Bit 30 DMA0 Error MSTDMA0 Error occurred in DMA channel 0 transfer Bit 29 DMA1 Error MSTDMA1 Error occurred in DMA channel 1 transfer Bit 28 DMA2 Error MSTDMA2 Error occurred in DMA channel 2 transfer Bit 27 DMA3 Error MSTDMA3 Error occurred in DMA channel 3 transfer Bit 26 Target Error TGT Error occurred in target read or target write transfer Bits 25 to 4 Reserved These b...

Page 954: ... 7 6 5 4 3 2 1 0 TGT_ABORT MST_ABORT DPERR_WT DPERR_RD Initial value 0 0 0 0 0 0 0 0 PCI R W R R R R R WC R WC R WC R WC PP Bus R W R R R R R WC R WC R WC R WC Note Cleared by writing WC 1 Writing of 0 is ignored The PCI arbiter interrupt register PCIAINT is a 32 bit register that stores the sources of PCI bus errors occurring during transfers by another PCI master device when the PCIC is operatin...

Page 955: ...and subsequent data transfers For the SH7751 see 22 12 Usage Notes Bit 11 Master Bus Timeout Interrupt MST_BUSTO Indicates the detection that IRDY was not asserted within 8 clock cycles in a transaction initiated by a device including PCIC Bits 10 to 4 Reserved These bits always return 0 when read Always write 0 to these bits when writing Bit 3 Target Abort Interrupt TGT_ABORT Indicates the termin...

Page 956: ...RT MST_ABORT DPERR_WT DPERR_RD Initial value 0 0 0 0 0 0 0 0 PCI R W R R R R R W R W R W R W PP Bus R W R R R R R W R W R W R W The PCI arbiter interrupt mask register PCIAINTM sets interrupt masks for the individual interrupts that occur due to errors generated during PCI transfers performed by other PCI devices when the PCIC is operating as the host with the arbitration function It is a 32 bit r...

Page 957: ...RR_RD 22 2 26 PCI Error Bus Master Data Register PCIBMLR Bit 31 30 29 11 10 9 8 Initial value 0 0 0 0 0 0 0 PCI R W R R R R R R R PP Bus R W R R R R R R R Bit 7 6 5 4 3 2 1 0 REQ4ID REQ3ID REQ2ID REQ1ID REQ0ID Initial value 0 0 0 PCI R W R R R R R R R R PP Bus R W R R R R R R R R The PCI error bus master data register PCIBMLR stores the device number of the bus master at the time an error occurred...

Page 958: ...device 1 REQ1 was bus master Bit 0 REQ0 Error REQ0ID Error occurred when device 0 REQ0 was bus master 22 2 27 PCI DMA Transfer Arbitration Register PCIDMABT Bit 31 30 29 11 10 9 8 Initial value 0 0 0 0 0 0 0 PCI R W R R R R R R R PP Bus R W R R R R R R R Bit 7 6 5 4 3 2 1 0 DMABT Initial value 0 0 0 0 0 0 0 0 PCI R W R R R R R R R R W PP Bus R W R R R R R R R R W The PCI DMA transfer arbitration r...

Page 959: ...8 PDPA27 PDPA26 PDPA25 PDPA24 Initial value 0 0 0 0 0 0 0 0 PCI R W R W R W R W R W R W R W R W R W PP Bus R W R W R W R W R W R W R W R W R W Bit 23 22 21 20 19 18 17 16 PDPA23 PDPA22 PDPA21 PDPA20 PDPA19 PDPA18 PDPA17 PDPA16 Initial value 0 0 0 0 0 0 0 0 PCI R W R W R W R W R W R W R W R W R W PP Bus R W R W R W R W R W R W R W R W R W Bit 15 14 13 12 11 10 9 8 PDPA15 PDPA14 PDPA13 PDPA12 PDPA11...

Page 960: ... power on reset and a software reset The transfer address of a byte boundary or character boundary can be set but the 2 least significant bits of this register are ignored and the data of the longword boundary is transferred Before starting a DMA transfer be sure to write to this register After a DMA transfer starts the value in the register is not retained Always re set the register value before ...

Page 961: ... R W R W R W R W R W R W R W R W R W PP Bus R W R W R W R W R W R W R W R W R W Bit 7 6 5 4 3 2 1 0 PDLA7 PDLA6 PDLA5 PDLA4 PDLA3 PDLA2 PDLA1 PDLA0 Initial value 0 0 0 0 0 0 0 0 PCI R W R W R W R W R W R W R W R W R W PP Bus R W R W R W R W R W R W R W R W R W The DMA transfer local bus start address register 3 0 PCIDLA 3 0 specifies the starting address at the local bus when performing DMA transf...

Page 962: ...ansfer Bits 28 to 26 indicate the local bus area 22 2 30 PCI DMA Transfer Counter Register 3 0 PCIDTC 3 0 Bit 31 30 29 28 27 26 25 24 PTC25 PTC24 Initial value 0 0 0 0 0 0 0 0 PCI R W R R R R R R R W R W PP Bus R W R R R R R R R W R W Bit 23 22 21 20 19 18 17 16 PTC23 PTC22 PTC21 PTC20 PTC19 PTC18 PTC17 PTC16 Initial value 0 0 0 0 0 0 0 0 PCI R W R W R W R W R W R W R W R W R W PP Bus R W R W R W ...

Page 963: ...and a software reset Bits 25 to 0 are used to specify the number of transfer bytes When set to H 00000000 the maximum 64MB transfer is performed Since the transfer data size corresponds only to longword data the 2 least significant bits are ignored Always write to this register prior to starting a DMA transfer Please re set this register when starting a new DMA transfer after a DMA transfer comple...

Page 964: ...transfer control register 3 0 PCIDCR 3 0 specifies the operating mode of the respective channels and the method of transfer etc This 32 bit read write register can be accessed from the PP bus and PCI bus The PCIDCR register is initialized to H 00000000 at a power on reset and software reset Writing 1 to bit 0 DMASTRT starts DMA transfer Always re set the value in this register before starting a ne...

Page 965: ...e For details refer to section 22 4 Endians Bit 8 DMA Transfer End Status DMAST Indicates the DMA transfer end status Bit 8 DMAST Description 0 Normal termination Initial value 1 Abnormal termination Error detection or forced DMA transfer termination Bit 7 DMA Transfer Termination Interrupt Mask DMAIM Specifies the DMA transfer termination interrupt mask Bit 7 DMAIM Description 0 Interrupt disable...

Page 966: ... Initial value 1 I O space Bit 2 Transfer Direction DIR Transfer direction during DMA transfer Bit 2 DIR Description 0 Transfer from PCI bus to local bus SH bus Initial value 1 Transfer from local bus SH bus to PCI bus Bit 1 Forced DMA Transfer Termination DMASTOP Forced termination of DMA transfer Bit 1 DMASTOP Description When writing 0 Writing of 0 is ignored 1 Forced termination of DMA transfe...

Page 967: ... 0 REGADR7 REGADR6 REGADR5 REGADR4 REGADR3 REGADR2 Initial value 0 0 PCI R W PP Bus R W R W R W R W R W R W R W R R The PIO address register PCIPAR is used when issuing configuration cycles on the PCI bus when the PCIC is host The PCIC supports the configuration mechanism 1 stipulated in the PCI local bus specifications This register is equivalent to the configuration register of configuration mec...

Page 968: ... 8 bits and its maximum value is 255 Bits 15 to 11 Device No DEVNO These bits specify the No of the device subject to configuration access The device No is expressed with 5 bits and takes a value from bits 0 to 31 In place of IDSEL one of bits 31 to 16 of the A D line corresponding to the device No set in this field is driven to 1 The following table shows the relationship between the device No an...

Page 969: ...ial value 0 0 0 0 0 0 0 0 PCI R W PP Bus R W R R R R R R R R W The memory space base register PCIMBR specifies the most significant 8 bits of the address of the PCI memory space when performing a memory read write operation using PIO transfers It also specifies locked transfers This 32 bit read write register can be accessed from the PP bus All bits of the PCIMBR register are initialized to 0 at a...

Page 970: ... transfer Bits 31 to 24 Memory Space Base Address MBR31 to 24 Sets the base address for the PCI memory space in PIO transfers Initial value is undefined Bits 23 to 1 Reserved These bits always return 0 when read Always write 0 to these bits when writing Bit 0 Lock Transfer LOCK Specifies the locking of the memory space during PIO transfer Bit 0 LOCK Description 0 Not locked Initial value 1 Locked ...

Page 971: ... R R Bit 7 6 5 4 3 2 1 0 LOCK Initial value 0 0 0 0 0 0 0 0 PCI R W PP Bus R W R R R R R R R R W The I O space base register PCIIOBR species the most significant 14 bits of the address of the PCI I O space when performing I O read and I O write operations by PIO transfer It also specifies locked transfers This 32 bit read write register can be accessed from the PP bus All bits of the PCII0BR regis...

Page 972: ... O space during PIO transfer Bit 0 LOCK Description 0 Not locked Initial value 1 Locked 22 2 35 PCI Power Management Interrupt Register PCIPINT Bit 31 30 29 11 10 9 8 Initial value 0 0 0 0 0 0 0 PCI R W PP Bus R W R R R R R R R Bit 7 6 5 4 3 2 1 0 PWRST_ D3 PWRST_ D0 Initial value 0 0 0 0 0 0 0 0 PCI R W PP Bus R W R R R R R R R WC R WC Note Cleared by setting WC 1 Writing of 0 is ignored The PCI ...

Page 973: ...mode interrupt for this LSI Note The power states D3 D0 are not masked even when the interrupt mask bit is set ON 22 2 36 PCI Power Management Interrupt Mask Register PCIPINTM Bit 31 30 29 11 10 9 8 Initial value 0 0 0 0 0 0 0 PCI R W PP Bus R W R R R R R R R Bit 7 6 5 4 3 2 1 0 DPERR_ WT DPERR_ RD Initial value 0 0 0 0 0 0 0 0 PCI R W PP Bus R W R R R R R R R W R W The PCI power management interr...

Page 974: ...lue 0 0 0 0 0 0 0 0 PCI R W PP Bus R W R R R R R R R W R W The PCI clock control register PCICLKR controls the stopping of the local bus clock BCLK in the PCIC and the PCI bus clock This 32 bit read write register can be accessed from the PP bus The PCICLKR register is initialized to H 00000000 at a power on reset It is not initialized at a software reset When the PCI bus clock is input from the e...

Page 975: ... PCIWCR2 PCIC Wait Control register 3 PCIWCR3 PCIC Discrete Memory Control Register PCIMCR Because PCI bus data is stored in the PCIC in memory on the local bus the PCIC is equipped with an internal bus controller PCIC BSC The PCIC BSC performs the same type of control as the slave function of the bus controller BSC However the PCIC BSC returns bus rights to the BSC after each data transfer of up ...

Page 976: ...de of DRAM and SDRAM is not available The local bus supports both big and little endian However the PCI bus supports only little endian The PCI BSC does not support mode register setting of synchronous DRAM nor refreshing of synchronous DRAM or DRAM These must be executed by the BSC Also do not implement any settings that are not allowed in slave mode in the PCIC BSC registers This is because bit ...

Page 977: ... 1 0 PB2PUP PB2IO PB1PUP PB1IO PB0PUP PB0IO Initial value 0 0 0 0 0 0 0 0 PCI R W PP Bus R W R R R W R W R W R W R W R W The port control register PCIPCTR selects whether to enable or disable port function allocation for pins for unwanted PCI bus arbitration when the PCIC is used in non host mode It also specifies the swithing ON OFF of pin pull up resistances and between input and output This 32 ...

Page 978: ...as ports Initial value 1 Use pins PCIGNT3 or PCIREQ3 as ports Bit 16 Port 0 Enable PORT0EN Provides the enable control for the port 0 Bit 16 PORT0EN Description 0 Do not use pins PCIGNT2 or PCIREQ2 as ports Initial value 1 Use pins PCIGNT2 or PCIREQ2 as ports Bits 15 to 6 Reserved These bits always return 0 when read Always write 0 to these bits when writing Bit 5 Port 2 Pull up Resistance Control...

Page 979: ...PB1IO Controls input or output when PCIREQ3 is used as a port Bit 2 PB1IO Description 0 Set PCIREQ3 pin for input Initial value 1 Set PCIREQ3 pin for output Bit 1 Port 0 Pull up Resistance Control PB0PUP Controls pull up resistance when PCIREQ2 pin is used as port Bit 1 PB0PUP Description 0 Pull up PCIREQ2 pin Initial value 1 Do not pull up PCIREQ2 pin Bit 0 Port 0 Input Output Control PB0IO Contr...

Page 980: ...can be accessed from the PP bus The PCIPDTR register is intialized to H 00000000 at a power on reset It is not initialized at a software reset Data is output in sync with the local bus clock Input data is fetched at the rising edge of the local bus clock Bits 31 to 6 Reserved These bits always return 0 when read Always write 0 to these bits when writing Bit 5 Port 2 Output Data PB5DT Output data w...

Page 981: ...W R W R W R W Bit 23 22 21 20 19 18 17 16 PPDA23 PPDA22 PPDA21 PPDA20 PPDA19 PPDA18 PPDA17 PPDA16 Initial value PCI R W PP Bus R W R W R W R W R W R W R W R W R W Bit 15 14 13 12 11 10 9 8 PPDA15 PPDA14 PPDA13 PPDA12 PPDA11 PPDA10 PPDA9 PPDA8 Initial value PCI R W PP Bus R W R W R W R W R W R W R W R W R W Bit 7 6 5 4 3 2 1 0 PPDA7 PPDA6 PPDA5 PPDA4 PPDA3 PPDA2 PPDA1 PPDA0 Initial value PCI R W PP...

Page 982: ...ether the PCIC operates as the host on the PCI bus and also select the bus clock for the PCI bus The mode selection signals input via the external mode pins are fetched on negation of a power on reset Table 22 8 Operating Modes MD9 MD10 Operating Modes 0 The PCIC host functions are enabled and the external input via the PCICLK pin is the operating clock for the PCI bus 0 1 The PCIC host functions ...

Page 983: ...guration read O O Configuration write O O Interrupt acknowledge cycle X X X X Special cycle O X Dual address cycle X X X X Legend O Supported Δ Limited support X Not issued by PCIC or no response from PCIC When PCIC Operates as Master The PCIC supports the memory read command memory write command I O read command and I O write command When the host functions are enabled the configuration command a...

Page 984: ...IC is operating as the host arbitration is enabled When operating as non host the PCIC can be accessed from the PCI bus Regardless of whether the PCIC is operating as the host or non host external PCI devices cannot be accessed from the PCIC while the CFINT bit is being cleared Set the CFINIT bit to 1 before accessing an external PCIC device Be sure to initialize the following 13 registers while t...

Page 985: ...the internal bus cycle for the peripheral module is made to wait until the data is actually ready In the write bus cycle the bus cycle of the internal bus for peripheral modules ends with the data having been written to the interface register located immediately after the PCIC input register on the internal bus for peripheral modules but the data is not actually written to the local register s or ...

Page 986: ...quests occur simultaneously the device with the highest order of priority takes precedence Here device 1 is the PCI device using bus privilege request pins PCIREQ1 and PCIGNT1 device 2 uses PCIREQ2 and PCIGNT2 device 3 uses PCIREQ3 and PCIGNT3 and device 4 uses PCIREQ4 and PCIGNT4 When the PCIC is operating as the host device no bus privilege request signals are output from the PCIC to the PCI bus...

Page 987: ...ed when the PCIC is operating as the host device The PIO address register PCIPAR and PIO data register PCIPDR are used to generate a configuration read write transfer for accessing the configuration register The PCIC supports the configuration mechanism stipulated in the PCI local bus spec First specify in the PCIPAR the address of the configuration register of the external PCI device to be access...

Page 988: ...ed for the bus grant signals When the bus grant signals are asserted when the bus request signals are not asserted the PCIC performs bus parking Also when the PCIC is used as a target device that does not request bus privileges the PCIREQ1 GNTIN pins must be fixed at the high level 22 3 7 PIO Transfers PIO transfer is a data transfer mode in which a peripheral bus is used to access the memory spac...

Page 989: ...an address space over the 16MB set PCIMBR again When performing locked transfers in memory transfer mode set the PCIMBR memory space lock specification bit LOCK While the LOCK bit is set the memory space is locked Note the following when performing LOCK transfers A LOCK transfer consists of one read transfer and one write transfer Always start with the read transfer The system will operate correct...

Page 990: ...e most significant 14 bits IOBR 31 18 of the I O space base register PCIIOBR are used as the most significant 14 bits of the PCI address These two addresses are combined to specify the 32 bit PCI address For transfers to the I O space first specify the most significant 14 bits of the PCI address in PCIIOBR then access the PCI I O address space If within the 256KB space you can access the PCI I O a...

Page 991: ...er However accuracy of the read data is not guaranteed 22 3 8 Target Transfers The following commands are available for transferring data in target transfers Memory read and memory write I O read and I O write access to PCIC local registers Configuration read configuration write Locked transfer is supported High speed back to back is not supported When the PCIC is operating in non host mode no res...

Page 992: ...orming target transfers using memory read or memory write commands PCI configuration register 5 PCICNF5 PCI configuration register 6 PCICNF6 PCI local space register 0 PCILSR 0 PCI local space register 1 PCILSR 1 PCI local address register 0 PCILAR 0 and PCI local address register 1 PCILAR 1 PCICONF5 PCICONF6 PCILSR0 PCILSR1 PCILAR0 PCILAR1 31 20 19 0 31 0 31 28 20 19 0 31 28 20 19 0 31 28 0 00000...

Page 993: ... is like address space 0 controlled by the PCICONF6 PCILSR1 and PCILAR1 In this way it is possible to set two address spaces In systems with two or less local bus areas that can be accessed from the PCI bus separate address spaces can be allocated to each of them To make it possible to access two or more areas from the PCI bus set the address spaces so that multiple areas are covered In this case ...

Page 994: ...a configuration access As a result when byte or word access is specified by the combination of BE 3 0 the remaining portion of the data in the longword unit is also overwritten by the write operation Locked Transfer Locked transfers are supported but the locked space becomes the whole memory of the PCIC in the case of memory transfers and becomes the whole register space in the case of I O transfe...

Page 995: ...s in the transfer in PCIDTC set the DMA transfer mode in the PCIDCR and specify a transfer start request The transfer starting address and the number of bytes in the transfer can be set on byte or word boundaries but because the least significant two bits of these registers are ignored the transfer is performed in longword units Also note that the local bus starting address set in PCIDLA is the ph...

Page 996: ...transfer 32 bits 0 Fixed priority 1 Pseudo round robin 0 1 31 28 PCIDLA 0 31 26 25 PCIDTC 0 31 PCIDPA 0 31 11 10 PCIDCR 0 Transfer control PCI address Transfer count Local address Area 0 H 00000000 to H 03FFFFFF Area 1 H 04000000 to H 07FFFFFF Area 2 H 0800 0000 to H 0BFFFFFF Area 3 H 0C000000 to H 0FFFFFFF Area 4 H 10000000 to H 13FFFFFF Area 5 H 14000000 to H 17FFFFFF Area 6 H 18000000 to H 1BFF...

Page 997: ...s forcibly terminated Error in data transfer When an error occurs during DMA transfer the DMA transfer is forcibly terminated on the channel in which the error occurred There is no effect on data transfers on other channels Forced termination of DMA transfer When the PCIDCR and DMASTOP bits for a channel are set data transfer on that channel is forcibly terminated However when the DMASTOP bit is s...

Page 998: ...t in the DMASTRT bit of the PCIDCR register The PCIDPA and PCIDLA registers are updated increment fixed by the LAHOLD bit of the PCIDCR register The PCIDTC decrements at a rate equaling the number of transfer bytes 4 bytes After DMA transfer completion the DMASTRT bit of the PCIDCR register is cleared to 0 and the DMAIS bit of the PCIDCR register is set to 1 DMA transfer is forcibly stopped when 1...

Page 999: ...rs are possible in both directions between the local bus and PCI bus by selecting the transfer direction The arbitration circuit monitors the data transfer requests data write requests to the FIFO when the FIFO is empty and read requests from the FIFO when it is full 4 DMA transfer channels to control the data transfers For each transfer request a transfer of up to 32 bytes of data is performed If...

Page 1000: ...ultaneously on 4 channels the data transfers start with alternation between channels 1 and 2 and then move to alternating between 2 and 3 when all the data in channel 1 has been transferred Likewise execution moves to alternation between channels 3 and 4 on completion of channel 2 This pattern is the same when data is transferred from the PCI bus to the local bus Pseudo round robin mode DMABT 1 In...

Page 1001: ...a high impedance state of at least one clock is generated prior to the address phase In host mode the arbiters in the PCICs and the REQ and GNT between PCICs are connected internally Here pins PCIREQ1 GNTIN PCIREQ2 MD9 PCIREQ3 MD10 and PCIREQ4 function as the REQ inputs from the external masters 1 to 4 Similarly PCIGNT1 REQOUT PCIGNT2 PCIGNT3 and PCIGNT4 function as the GNT outputs to external mas...

Page 1002: ...D31 AD0 PAR C BE3 C BE0 PCIFRAME IRDY DEVSEL TRDY PCILOCK IDSEL PCIREQ1 GNTIN PCIREQ2 PCIREQ4 Legend Addr PCI space address Dn nth data AP Address parity DPn nth data parity Com Command BEn nth data byte enable PCIGNT1 REQOUT PCIGNT2 PCIGNT4 Addr D0 Com BE0 AP DP0 LOCKed Figure 22 7 Master Write Cycle in Host Mode Single ...

Page 1003: ...D31 AD0 PAR C BE3 C BE0 PCIFRAME IRDY DEVSEL TRDY PCILOCK IDSEL PCIREQ1 GNTIN PCIREQ2 PCIREQ4 Legend Addr PCI space address Dn nth data AP Address parity DPn nth data parity Com Command BEn nth data byte enable PCIGNT1 REQOUT PCIGNT2 PCIGNT4 Addr D0 Com BE0 AP DPn LOCKed Figure 22 8 Master Read Cycle in Host Mode Single ...

Page 1004: ... AD31 AD0 PAR C BE3 C BE0 PCIFRAME IRDY DEVSEL TRDY PCILOCK IDSEL PCIREQ1 GNTIN Legend Addr PCI space address Dn nth data AP Address parity DPn nth data parity Com Command BEn nth data byte enable PCIGNT1 REQOUT Addr D0 D1 Dn Com BE0 BE1 BEn AP DP0 DPn 1 APn Figure 22 9 Master Memory Write Cycle in Non Host Mode Burst ...

Page 1005: ... AD31 AD0 PAR C BE3 C BE0 PCIFRAME IRDY DEVSEL TRDY PCILOCK IDSEL PCIREQ1 GNTIN Legend Addr PCI space address Dn nth data AP Address parity DPn nth data parity Com Command BEn nth data byte enable PCIGNT1 REQOUT Addr D0 D1 Dn Com BE0 BE1 BEn AP DP0 DPn 1 DPn Figure 22 10 Master Memory Read Cycle in Non Host Mode Burst ...

Page 1006: ...es the data cannot be guaranteed when a target read is performed immediately after a target write The possibility of an error occurs when the target read immediately after the target write gets bus privileges at the point the data is ready for a target read by a different PCI device prior to the target write In this case the data prior to the target write is read If such transfers are likely to oc...

Page 1007: ... 13 is an example of a target burst read cycle in host mode And Figure 22 14 is an example target burst write cycle in host mode PCICLK AD31 AD0 PAR C BE3 C BE0 PCIFRAME IRDY DEVSEL TRDY PCILOCK IDSEL PCIREQ1 GNTIN PCIGNT1 REQOUT Addr D0 BE0 DP0 AP PCISTOP Com LOCKed At Config Access Legend Addr PCI space address Dn nth data AP Address parity DPn nth data parity Com Command BEn nth data byte enabl...

Page 1008: ...D0 PAR C BE3 C BE0 PCIFRAME IRDY DEVSEL TRDY PCILOCK IDSEL PCIREQ1 GNTIN PCIGNT1 REQOUT Addr BE0 AP PCISTOP Com D0 DP0 LOCKed At Config Access Legend Addr PCI space address Dn nth data AP Address parity DPn nth data parity Com Command BEn nth data byte enable Disconnect Figure 22 12 Target Write Cycle in Non Host Mode Single ...

Page 1009: ...1 AD0 PAR C BE3 C BE0 PCIFRAME IRDY DEVSEL PCISTOP IDSEL PCIREQn PCIGNTn Addr D0 BE0 DP0 AP PCILOCK Com BE1 BEn D1 Dn DPn 1 DPn TRDY Legend Addr PCI space address Dn nth data AP Address parity DPn nth data parity Com Command BEn nth data byte enable LOCKed Disconnect Figure 22 13 Target Memory Read Cycle in Host Mode Burst ...

Page 1010: ... AD0 PAR C BE3 C BE0 PCIFRAME IRDY DEVSEL TRDY PCILOCK IDSEL PCIREQn PCIGNTn Addr Dn D1 D0 BE0 DP0 AP DPn 1 DPn PCISTOP Com BE1 BEn Legend Addr PCI space address Dn nth data AP Address parity DPn nth data parity Com Command BEn nth data byte enable LOCKed Disconnect Figure 22 14 Target Memory Write Cycle in Host Mode Burst ...

Page 1011: ...D bus does not achieve the stipulated logic level in one clock When the PCIC operates as the host it is recommended to use this function for the issuance of configuration transfers Figure 22 15 is an example of burst memory write cycle with stepping Figure 22 16 is an example of target burst read cycle with stepping PCICLK AD31 AD0 PAR C BE3 C BE0 PCIFRAME IRDY DEVSEL TRDY Com BE0 BEn AP DP0 DPn 1...

Page 1012: ...1 Sep 24 2013 PCICLK AD31 AD0 PAR PCIFRAME IRDY DEVSEL TRDY Legend Addr PCI space address Dn nth data AP Address parity DPn nth data parity Com Command BEn nth data byte enable Addr BEn AP DP0 DPn 1 DPn Com D0 Dn BE0 C BE3 C BE0 Figure 22 16 Target Memory Read Cycle in Host Mode Burst With Stepping ...

Page 1013: ...ching between these modes Peripheral bus Big endian 32 bits 32 bits 32 bits 32 bits Little endian PCI bus Big little Little big Figure 22 17 Endian Conversion Modes for Peripheral Bus 1 Byte data boundary mode Big little endian conversion is performed on the assumption that all data is on byte boundaries BYTESWAP 1 2 Word longword W LW boundary mode Big little endian conversion is performed accord...

Page 1014: ... W LW boundary mode Legend B Byte W Word LW Longword Size Address Data Data W LW boundary mode Address memory I O BE 3 0 Data Byte data boundary mode Long Word B0 B0 B0 4n 0 4n 0 1110 4n 0 Byte B1 B1 B1 4n 0 4n 1 1101 4n 1 B2 B2 B2 4n 0 4n 2 1011 4n 2 B3 B3 B3 4n 0 4n 3 0111 4n 3 B0 B1 B0 B1 B1 B0 4n 0 4n 0 1100 4n 0 B2 B3 B2 B3 B3 B2 4n 0 4n 2 0011 4n 2 B0 B1 B2 B3 B0 B1 B2 B3 B3 B2 B1 B0 4n 0 4n...

Page 1015: ...e Local bus PCI bus Little endian Big little endian Big little little Little big little 32 bits 32 bits 32 bits 32 bits LW LW LW B W LW FIFO DMA Target RD DMA Targer WT FIFO Figure 22 19 Endian Control for Local Bus 22 4 3 Endian Control in DMA Transfers Although only the longword access size is supported in DMA transfers see table 22 11 the endian conversion mode can be selected from the followin...

Page 1016: ...e Endian Conversion Mode Local Bus Endian Data Transfer Direction Access Size W LW Boundary Mode 1 to 3 Byte Data Boundary Mode Big endian Local bus PCI bus LW Yes Yes Little endian Local bus PCI bus LW Conversion not required Conversion not required B0 BE 0000 B1 B2 B3 Size LW B3 B2 B1 B0 B3 B2 B1 B0 B2 B3 B0 B1 B0 B1 B2 B3 When local bus is big endian Local bus PCI bus Byte data boundary mode W ...

Page 1017: ...nsfers are as follows For target reads local bus to PCI bus longword only For target writes PCI bus to local bus longword word byte In target write operations the byte word and longword data in the PCIC are transferred to the local bus in one or two transfer operations depending on the type of the byte enable signal of the PCI bus For example when C BE B 1010 byte access to the local bus is genera...

Page 1018: ...100 0011 1010 0101 0110 1001 1000 0100 0010 0001 1111 0000 B1 B2 B3 B1 B0 B3 B2 B2 B0 B3 B1 B3 B0 B2 B1 B2 B1 B0 B3 B1 B0 B3 B2 B0 B3 B2 B1 B3 B2 B1 B0 Local bus PCI bus 31 0 31 0 Target memory write transfers local bus PCI bus when local bus is big endian BE Size LW B0 B1 B2 B3 B3 B2 B1 B0 H 0 to H F Local bus PCI bus 31 0 31 0 Target memory read transfers local bus PCI bus when local bus is big ...

Page 1019: ...011 1010 0101 0110 1001 1000 0100 0010 0001 1111 0000 B1 B2 B3 B1 B0 B3 B2 B2 B0 B3 B1 B3 B0 B2 B1 B2 B1 B0 B3 B1 B0 B3 B2 B0 B3 B2 B1 B3 B2 B1 B0 Local bus PCI bus 31 0 31 0 Target memory write transfers local bus PCI bus when local bus is little endian BE Size LW B3 B2 B1 B0 B3 B2 B1 B0 H 0 to H F Local bus PCI bus 31 0 31 0 Target memory read transfers local bus PCI bus when local bus is little...

Page 1020: ...31 0 BE Local register B3 B2 B1 B0 31 0 Size LW Address 4n H 0000 PCI bus B3 B2 B1 B0 31 0 BE Local register B3 B2 B1 B0 31 0 Target I O read transfer data alignment local register PCI bus Target I O write transfer data alignment PCI bus local register Figure 22 22 Data Alignment at Target I O Transfer Both Big Endian and Little Endian 22 4 6 Endian Control in Target Transfers Configuration Read C...

Page 1021: ...1 0 B1 31 0 B3 B2 B1 B0 31 0 31 0 H 0 to H F PCI bus B3 B2 B1 B0 31 0 BE Configuration register B3 B2 B1 B0 31 0 B0 31 0 B3 B2 B1 31 0 B3 B2 B0 31 0 B3 B2 31 0 B3 B1 B0 31 0 B3 B1 B0 31 0 B3 B1 31 0 B3 B0 31 0 B3 31 0 B2 B1 B0 31 0 B2 B1 31 0 B2 B0 31 0 B2 31 0 B1 B0 31 0 B1 31 0 B3 B2 B1 B0 31 0 31 0 B0 31 0 Target configuration read transfer data alignment configuration register PCI bus SH7751 t...

Page 1022: ...h Manual Reset The PCIC does not support the input of manual reset signals via the MRESET pin No initialization therefore occurs by manual resets Software Reset Software resets are generated by setting 1 in the PCIRST output control bit RSTCTL of the PCI control register PCICR The PCIRST pin is asserted at the same time as the PCIC is reset While a software reset is asserted the PCIC registers can...

Page 1023: ...interrupt PCIDMA2 DMA2 transfer end interrupt PCIDMA3 DMA3 transfer end interrupt Low Low System Error SERR Interrupt PCISERR This interrupt shows detection of the SERR pin being asserted This interrupt is generated only when the PCIC is operating as host When the PCIC is operating as non host the SERR bit in the PCI control register PCICR is used to notify the host device of the system error asse...

Page 1024: ...mask DMAIM bit of the same register DMA Channel 2 Transfer Termination Interrupt PCIDMA2 The DMA termination interrupt status DMAIS bit of the DMA control register 2 PCIDCR2 is set The interrupt mask is set by the DMA termination interrupt mask DMAIM bit of the same register DMA Channel 3 Transfer Termination Interrupt PCIDMA3 The DMA termination interrupt status DMAIS bit of the DMA control regis...

Page 1025: ... can only store information for one error Therefore when errors occur consecutively no information is stored for the second or subsequent errors Error information is cleared by resets 22 8 PCIC Clock Three clocks are used with the PCIC The peripheral module clock Pck is used for PCIC register access and PIO transfers The bus clock Bck is used for local bus control The PCI bus clock is used for PCI...

Page 1026: ...s 66 MHz When not using the PCICLK pin fix the pin level high 66 MHz Compatibility The PCIC is not necessarily fully compatible with the 66 MHz bus standard of the PCI For details see section 23 Electrical Characteristics In the electrical characteristics of the PCI bus related pins the permissible delay on the board is extremely short For this reason the on board load capacitance and impedance ma...

Page 1027: ...detects a transition from the power state D0 to D3 while power state D0 PWRST_D0 interrupt detects a transition from the power state D3 to D0 Interrupt masks can be set for each interrupt No power state D0 interrupt is generated at a power on reset The following cautions should be noted when the PCIC is operating in non host mode and a power down interrupt is received from the host In PCI power ma...

Page 1028: ...ation Deep sleep PCICLK Not used Normal operation Not used Normal operation Bck Stopped Stopped Stopped Stopped Pck Stopped Stopped Stopped Stopped Clock operating status Standby PCICLK Not used Stopped Not used Stopped Transition Sleep command Bck stopped from LSI Bck and PCICLK stopped from LSI PCI command interrupt PCIC LSI Bck restarted from LSI Transition Recovery Deep sleep Recovery 1 Not us...

Page 1029: ... The PCI bus clock can be stopped by writing 1 to the PCICLKSTOP bit The bus clock can be stopped by writing 1 to the BCLKSTOP bit It requires a minimum of 2 clocks of the PCI bus clock for the clock to actually stop after writing to PCICLKR setting the PCICLKSTOP bit to 1 It takes a similar time for the clock to restart Bus Clock CKIO Operating Mode Both the PCI bus clock and bus clock can be sto...

Page 1030: ...Sleep To stop all the PCIC s internal clocks the SLEEP command must be used to transit to standby mode When operating in external input pin PCICLK operating mode set the PCICLKSTOP bit to 1 to stop the PCI bus clock transit to standby then after recovering from standby clear the PCICLKSTOP bit to 0 to prevent hazards occuring in the PCI bus clock When using the standby command in systems using the...

Page 1031: ...ck rule according to the PCI 2 1 specification the SH7751 judges that a 16 clock rule or 8 clock rule violation has occurred and sets to 1 bit 12 target bus timeout interrupt or bit 11 master bus timeout interrupt in the PCI arbiter interrupt register PCIAINT 1 Target latency A target bus timeout interrupt occurs see figures 22 24 and 22 25 During the first data transfer the external PCI device fu...

Page 1032: ...bus timeout interrupt mask in the PCI arbiter interrupt mask register PCIAINTM to mask the master bus timeout interrupt Note that if the above interrupts are masked no interrupt will occur when the 16 clock rule or 8 clock rule of PCI 2 1 specification is violated even if the violation is detected A 0 PCICLK AD 31 0 C BE 3 0 FRAME IRDY DEVSEL TRDY STOP 1 2 3 4 11 12 13 14 15 16 C PCIAINT Bit 12 as...

Page 1033: ...5 Target Bus Timeout Interrupt Generation Example 2 Example in which the Target Device Takes 8 Clock Cycles to Prepare for the Third Data Transfer A 0 PCICLK AD 31 0 C BE 3 0 FRAME IRDY DEVSEL TRDY STOP 1 2 3 4 5 6 7 8 C D D D D D D BE BE BE D BE BE BE BE High PCIAINT Bit 11 asserted Figure 22 26 Master Bus Timeout Interrupt Generation Example 1 Example in which the Master Device Prepares the Data...

Page 1034: ... SH7751 Only See I O Read and I O Write Commands in 22 3 8 22 12 3 Notes on Configuration Read and Configuration Write Commands SH7751 Only See Configuration Read and Configuration Write Commands in 22 3 8 22 12 4 Notes on Target Read Write Cycle Timing SH7751 Only See Target Read Write Cycle Timing in 22 3 11 22 12 5 Notes on Parity Error Detection during Master Access Data error may not be detec...

Page 1035: ...rget initiated disconnect with data STOP asserted Influence on System When a target initiated disconnect with data occurs a parity error is not detected in the data phase in which disconnection has occurred and PERR is not asserted If not all the above conditions are satisfied a parity error can be properly determined This phenomenon may be inconvenient during master read access target data parity...

Page 1036: ...Section 22 PCI Controller PCIC SH7751 Group SH7751R Group Page 982 of 1128 R01UH0457EJ0301 Rev 3 01 Sep 24 2013 ...

Page 1037: ... 2 0 3 to 4 6 1 V Internal power supply voltage VDD VDD PLL1 2 0 3 to 2 5 0 3 to 2 1 1 V Input voltage Vin 0 3 to VDDQ 0 3 V Operating temperature Topr 20 to 75 40 to 85 2 C Storage temperature Tstg 55 to 125 C Notes The LSI may be permanently damaged if the maximum ratings are exceeded The LSI may be permanently damaged if any of the VSS pins are not connected to GND For the powering on and power...

Page 1038: ...oltage VDD VDD PLL1 2 1 4 1 5 1 6 V Normal mode sleep mode deep sleep mode standby mode Current dissipation Normal operation IDD 255 660 Sleep mode 140 180 mA Ick 240 MHz Standby mode 400 μA Ta 25 C 1 800 Ta 50 C 1 Current dissipation Normal operation IDDQ 100 145 Sleep mode 60 115 mA Bck 120 MHz Standby mode 400 μA Ta 25 C 1 800 Ta 50 C 1 Standby mode 15 25 RTC on 2 Current dissipation IDD RTC 3 ...

Page 1039: ... 3 0 V IOL 4 mA Other output pins 0 55 VDDQ 3 0 V IOL 2 mA Pull up resistance All pins Rpull 20 60 180 kΩ Pin capacitance All pins CL 10 pF Notes Connect VDD RTC and VDD CPG to VDDQ VDD PLL1 2 to VDD and VSS CPG VSS PLL1 2 and VSS RTC to GND regardless of whether or not the PLL circuits and RTC are used The current dissipation values are for VIH min VDDQ 0 5 V and VIL max 0 5 V with all output pin...

Page 1040: ...1 6 V Normal mode sleep mode deep sleep mode standby mode Current dissipation Normal operation IDD 255 660 Sleep mode 140 180 mA Ick 240 MHz Standby mode 400 μA Ta 25 C 1 800 Ta 50 C 1 Current dissipation Normal operation IDDQ 70 100 Sleep mode 42 80 mA Bck 84 MHz Standby mode 400 μA Ta 25 C 1 800 Ta 50 C 1 Standby mode 15 25 RTC on 2 Current dissipation IDD RTC 3 5 μA RTC off Input voltage RESET ...

Page 1041: ...CI pins VOL 0 55 VDDQ 3 0 V IOL 4 mA Other output pins 0 55 VDDQ 3 0 V IOL 2 mA Pull up resistance All pins Rpull 20 60 180 kΩ Pin capacitance All pins CL 10 pF Notes Connect VDD RTC and VDD CPG to VDDQ VDD PLL1 2 to VDD and VSS CPG VSS PLL1 2 and VSS RTC to GND regardless of whether or not the PLL circuits and RTC are used The current dissipation values are for VIH min VDDQ 0 5 V and VIL max 0 5 ...

Page 1042: ...VDD PLL1 2 1 35 1 5 1 6 V Normal mode sleep mode deep sleep mode standby mode Current dissipation Normal operation IDD 210 550 Sleep mode 115 150 mA Ick 200 MHz Standby mode 400 μA Ta 25 C 1 800 Ta 50 C 1 Current dissipation Normal operation IDDQ 85 120 Sleep mode 50 95 mA Bck 100 MHz Standby mode 400 μA Ta 25 C 1 800 Ta 50 C 1 Standby mode 15 25 RTC on 2 Current dissipation IDD RTC 3 5 μA RTC off...

Page 1043: ... 3 0 V IOL 2 mA Pull up resistance All pins Rpull 20 60 180 kΩ Pin capacitance All pins CL 10 pF Notes Connect VDD RTC and VDD CPG to VDDQ VDD PLL1 2 to VDD and VSS CPG VSS PLL1 2 and VSS RTC to GND regardless of whether or not the PLL circuits and RTC are used The current dissipation values are for VIH min VDDQ 0 5 V and VIL max 0 5 V with all output pins unloaded IDD is the sum of the VDD and VD...

Page 1044: ...1 6 V Normal mode sleep mode deep sleep mode standby mode Current dissipation Normal operation IDD 210 550 Sleep mode 115 150 mA Ick 200 MHz Standby mode 400 μA Ta 25 C 1 800 Ta 50 C 1 Current dissipation Normal operation IDDQ 70 100 Sleep mode 42 80 mA Bck 84 MHz Standby mode 400 μA Ta 25 C 1 800 Ta 50 C 1 Standby mode 15 25 RTC on 2 Current dissipation IDD RTC 3 5 μA RTC off Input voltage RESET ...

Page 1045: ... 3 0 V IOL 4 mA Output voltage Other output pins VOL 0 55 V VDDQ 3 0 V IOL 2 mA Pull up resistance All pins Rpull 20 60 180 kΩ Pin capacitance All pins CL 10 pF Notes Connect VDD RTC and VDD CPG to VDDQ VDD PLL1 2 to VDD and VSS CPG VSS PLL1 2 and VSS RTC to GND regardless of whether or not the PLL circuits and RTC are used The current dissipation values are for VIH min VDDQ 0 5 V and VIL max 0 5 ...

Page 1046: ...mode sleep mode standby mode Current dissipation Normal operation IDD 420 750 Sleep mode 100 130 mA Ick 167 MHz Standby mode 400 μA Ta 25 C RTC on 800 Ta 50 C RTC on Current dissipation Normal operation IDDQ 70 100 Sleep mode 40 80 mA Ick 167 MHz Bck 84 MHz Standby mode 400 μA Ta 25 C RTC on 800 Ta 50 C RTC on Standby mode IDD RTC 25 μA RTC on Current dissipation 5 RTC off Input voltage RESET NMI ...

Page 1047: ... mA Other output pins 2 4 VDDQ 3 0 V IOH 2 mA PCI pins VOL 0 55 VDDQ 3 0 V IOL 4 mA Output voltage Other output pins 0 55 VDDQ 3 0 V IOL 2 mA Pull up resistance All pins Rpull 20 60 180 kΩ Pin capacitance All pins CL 10 pF Notes Connect VDD RTC and VDD CPG to VDDQ VDD PLL1 2 to VDD and VSS CPG VSS PLL1 2 and VSS RTC to GND regardless of whether or not the PLL circuits and RTC are used The current ...

Page 1048: ...mode sleep mode standby mode Current dissipation Normal operation IDD 420 750 Sleep mode 100 130 mA Ick 167 MHz Standby mode 400 μA Ta 25 C RTC on 800 Ta 50 C RTC on Current dissipation Normal operation IDDQ 70 100 Sleep mode 40 80 mA Ick 167 MHz Bck 84 MHz Standby mode 400 μA Ta 25 C RTC on 800 Ta 50 C RTC on Standby mode IDD RTC 25 μA RTC on Current dissipation 5 RTC off Input voltage RESET NMI ...

Page 1049: ... mA Other output pins 2 4 VDDQ 3 0 V IOH 2 mA PCI pins VOL 0 55 VDDQ 3 0 V IOL 4 mA Output voltage Other output pins 0 55 VDDQ 3 0 V IOL 2 mA Pull up resistance All pins Rpull 20 60 180 kΩ Pin capacitance All pins CL 10 pF Notes Connect VDD RTC and VDD CPG to VDDQ VDD PLL1 2 to VDD and VSS CPG VSS PLL1 2 and VSS RTC to GND regardless of whether or not the PLL circuits and RTC are used The current ...

Page 1050: ...issible output high current total Σ IOH 40 Note To protect chip reliability do not exceed the output current values in table 23 8 23 3 AC Characteristics In principle this LSI s input should be synchronous Unless specified otherwise ensure that the setup time and hold times for each input signal are observed Table 23 9 Clock Timing HD6417751RBP240 V HD6417751RBG240 V HD6417751RBA240HV Item Symbol ...

Page 1051: ...perating frequency Peripheral modules 1 50 Note This is the case when the device in use is an HD6417751RBA240HV running at 200 MHz Table 23 12 Clock Timing HD6417751RF200 V Item Symbol Min Typ Max Unit Notes CPU FPU cache TLB f 1 200 MHz External bus 1 84 Operating frequency Peripheral modules 1 50 Table 23 13 Clock Timing HD6417751BP167 V HD6417751F167 V Item Symbol Min Typ Max Unit Notes CPU FPU...

Page 1052: ... level pulse width tCKOL1 1 ns 23 2 1 CKIO clock output high level pulse width tCKOH1 1 ns 23 2 1 CKIO clock output rise time tCKOr 3 ns 23 2 1 CKIO clock output fall time tCKOf 3 ns 23 2 1 CKIO clock output low level pulse width tCKOL2 3 ns 23 2 2 CKIO clock output high level pulse width tCKOH2 3 ns 23 2 2 Power on oscillation settling time tOSC1 10 ms 23 3 23 5 Power on oscillation settling time...

Page 1053: ...XTAL the maximum frequency is 34 MHz When a 3rd overtone crystal resonator is used an external tank circuit is necessary As there is feedback from the CKIO pin when PLL2 is operating the load capacitance connected to the CKIO pin should be a maximum of 50 pF 1 When the oscillation settling time of the crystal resonator is 1 ms or less 2 Ta 40 to 85 C for the HD6417751RBA240HV ...

Page 1054: ...e tCKOr 3 ns 23 2 1 CKIO clock output fall time tCKOf 3 ns 23 2 1 CKIO clock output low level pulse width tCKOL2 3 ns 23 2 2 CKIO clock output high level pulse width tCKOH2 3 ns 23 2 2 Power on oscillation settling time tOSC1 10 ms 23 3 23 5 Power on oscillation settling time mode settling tOSCMD 10 ms 23 3 23 5 MD reset setup time tMDRS 3 tcyc MD reset hold time tMDRH 20 ns 23 3 23 5 RESET assert...

Page 1055: ...01UH0457EJ0301 Rev 3 01 Page 1001 of 1128 Sep 24 2013 As there is feedback from the CKIO pin when PLL2 is operating the load capacitance connected to the CKIO pin should be a maximum of 50 pF When the oscillation settling time of the crystal resonator is 1 ms or less ...

Page 1056: ...tCKOL1 1 ns 23 2 1 CKIO clock output high level pulse width tCKOH1 1 ns 23 2 1 CKIO clock output rise time tCKOr 3 ns 23 2 1 CKIO clock output fall time tCKOf 3 ns 23 2 1 CKIO clock output low level pulse width tCKOL2 3 ns 23 2 2 CKIO clock output high level pulse width tCKOH2 3 ns 23 2 2 Power on oscillation settling time tOSC1 10 ms 23 3 23 5 Power on oscillation settling time mode settling tOSC...

Page 1057: ...a 3rd overtone crystal resonator is used an external tank circuit is necessary As there is feedback from the CKIO pin when PLL2 is operating the load capacitance connected to the CKIO pin should be a maximum of 50 pF 1 When the oscillation settling time of the crystal resonator is 1 ms or less 2 This is the case when the device in use is an HD6417751RBA240HV running at 200 MHz 3 Ta 40 to 85 C for ...

Page 1058: ... tCKOr 3 ns 23 2 1 CKIO clock output fall time tCKOf 3 ns 23 2 1 CKIO clock output low level pulse width tCKOL2 3 ns 23 2 2 CKIO clock output high level pulse width tCKOH2 3 ns 23 2 2 Power on oscillation settling time tOSC1 10 ms 23 3 23 5 Power on oscillation settling time mode settling tOSCMD 10 ms 23 3 23 5 MD reset setup time tMDRS 3 tcyc MD reset hold time tMDRH 20 ns 23 3 23 5 RESET assert ...

Page 1059: ...01UH0457EJ0301 Rev 3 01 Page 1005 of 1128 Sep 24 2013 As there is feedback from the CKIO pin when PLL2 is operating the load capacitance connected to the CKIO pin should be a maximum of 50 pF When the oscillation settling time of the crystal resonator is 1 ms or less ...

Page 1060: ...lse width tCKOH1 1 ns 23 2 1 CKIO clock output rise time tCKOr 3 ns 23 2 1 CKIO clock output fall time tCKOf 3 ns 23 2 1 CKIO clock output low level pulse width tCKOL2 3 ns 23 2 2 CKIO clock output high level pulse width tCKOH2 3 ns 23 2 2 Power on oscillation settling time tOSC1 10 ms 23 3 23 5 Power on oscillation settling time mode settling tOSCMD 10 ms 23 3 23 5 MD reset setup time tMDRS 3 tcy...

Page 1061: ...EXcyc tEXH tEXL tEXr tEXf 1 2VDDQ VIH VIH VIL VIL VIH 1 2VDDQ Note When the clock is input from the EXTAL pin Figure 23 1 EXTAL Clock Input Timing tcyc tCKOH1 tCKOL1 tCKOr tCKOf 1 2VDDQ VOH VOH VOL VOL VOH 1 2VDDQ Figure 23 2 1 CKIO Clock Output Timing tCKOH2 1 5 V 1 5 V 1 5 V tCKOL2 Figure 23 2 2 CKIO Clock Output Timing ...

Page 1062: ...TRSTRH Stable oscillation tRESW Notes 1 Oscillation settling time when on chip resonator is used 2 PLL2 not operating Figure 23 3 Power On Oscillation Settling Time RESET or MRESET tRESW tOSC2 Standby Stable oscillation CKIO internal clock Notes 1 Oscillation settling time when on chip resonator is used 2 PLL2 not operating Figure 23 4 Standby Return Oscillation Settling Time Return by RESET or MR...

Page 1063: ...H Stable oscillation tRESW CKIO Notes 1 Oscillation settling time when on chip resonator is used 2 PLL2 operating Figure 23 5 Power On Oscillation Settling Time RESET or MRESET tRESW tOSC2 CKIO Stable oscillation Standby Internal clock Notes 1 Oscillation settling time when on chip resonator is used 2 PLL2 operating Figure 23 6 Standby Return Oscillation Settling Time Return by RESET or MRESET ...

Page 1064: ...oscillation Standby tOSC3 Note Oscillation settling time when on chip resonator is used Figure 23 7 Standby Return Oscillation Settling Time Return by NMI IRL3 IRL0 tOSC4 Standby Stable oscillation CKIO internal clock Note Oscillation settling time when on chip resonator is used Figure 23 8 Standby Return Oscillation Settling Time Return by IRL3 IRL0 ...

Page 1065: ...t clock Reset or NMI interrupt request PLL synchronization PLL synchronization Figure 23 9 PLL Synchronization Settling Time in Case of RESET MRESET or NMI Interrupt IRL3 IRL0 interrupt request tIRLSTB STATUS1 STATUS0 Note When an external clock is input from EXTAL Normal Standby Normal tPLL 2 EXTAL input PLL output CKIO output Internal clock Stable input clock Stable input clock PLL synchronizati...

Page 1066: ... 5 3 5 ns 23 11 BREQ hold time tBREQH 1 5 1 5 1 5 1 5 ns 23 11 BACK delay time tBACKD 5 3 5 3 6 6 ns 23 11 Bus tri state delay time tBOFF1 12 12 12 12 ns 23 11 Bus tri state delay time to standby mode tBOFF2 2 2 2 2 tcyc 23 12 2 Bus buffer on time tBON1 12 12 12 12 ns 23 11 Bus buffer on time from standby tBON2 2 2 2 2 tcyc 23 12 2 tSTD1 6 6 6 6 ns 23 12 1 STATUS 0 1 delay time tSTD2 2 2 2 2 tcyc ...

Page 1067: ... tBREQS 3 5 ns 23 11 BREQ hold time tBREQH 1 5 ns 23 11 BACK delay time tBACKD 8 ns 23 11 Bus tri state delay time tBOFF1 12 ns 23 11 Bus tri state delay time to standby mode tBOFF2 2 tcyc 23 12 2 Bus buffer on time tBON1 12 ns 23 11 Bus buffer on time from standby tBON2 2 tcyc 23 12 2 STATUS 0 1 delay time tSTD1 6 ns 23 12 1 tSTD2 2 tcyc 23 12 1 2 tSTD3 2 tcyc 23 12 2 Note VDDQ 3 0 to 3 6 V VDD 1...

Page 1068: ...CKIO A25 A0 CSn BS RD WR CE2A CE2B RAS WEn RD CASn BREQ BACK tBREQH tBREQS tBREQH tBREQS tBACKD tBOFF1 tBON1 tBACKD Figure 23 11 Control Signal Timing tSTD1 CKIO STATUS1 STATUS0 reset or sleep normal normal tSTD2 Normal operation Normal operation Reset or sleep mode Figure 23 12 1 Pin Drive Timing for Reset or Sleep Mode ...

Page 1069: ...CKIO Note These pins can be put into a high impedance state with STBCR PHZ STATUS1 STATUS0 CSn RD RD WR WEn BS RAS CE2A CE2B CASn DACKn DRAKn SCK TXD TXD2 CTS2 RTS2 A25 A0 D31 D0 tBOFF2 software standby normal normal tSTD2 Normal operation Normal operation Reset or sleep mode Figure 23 12 2 Pin Drive Timing for Software Standby Mode ...

Page 1070: ... hold time tRDH 1 5 1 5 1 5 1 5 ns WE delay time falling edge tWEDF 5 3 5 3 6 6 ns Relative to CKIO falling edge WE delay time tWED1 1 5 5 3 1 5 5 3 1 5 6 1 5 6 ns Write data delay time tWDD 1 5 5 3 1 5 5 3 1 5 6 1 5 6 ns RDY setup time tRDYS 2 0 2 5 3 5 3 5 ns RDY hold time tRDYH 1 5 1 5 1 5 1 5 ns RAS delay time tRASD 1 5 5 3 1 5 5 3 1 5 6 1 5 6 ns CAS delay time 1 tCASD1 1 5 5 3 1 5 5 3 1 5 6 1...

Page 1071: ... 1 5 6 1 5 6 ns Relative to CKIO falling edge DTR setup time tDTRS 2 0 2 5 3 5 3 5 ns DTR hold time tDTRH 1 5 1 5 1 5 1 5 ns DBREQ setup time tDBQS 2 0 2 5 3 5 3 5 ns DBREQ hold time tDBQH 1 5 1 5 1 5 1 5 ns TR setup time tTRS 2 0 2 5 3 5 3 5 ns TR hold time tTRH 1 5 1 5 1 5 1 5 ns BAVL delay time tBAVD 1 5 5 3 1 5 5 3 1 5 6 1 5 6 ns TDACK delay time tTDAD 1 5 5 3 1 5 5 3 1 5 6 1 5 6 ns ID1 ID0 de...

Page 1072: ...tive to CKIO falling edge WE delay time tWED1 1 0 8 ns Write data delay time tWDD 1 0 8 ns RDY setup time tRDYS 3 5 ns RDY hold time tRDYH 1 5 ns RAS delay time tRASD 1 0 8 ns CAS delay time 1 tCASD1 1 0 8 ns DRAM CAS delay time 2 tCASD2 1 0 8 ns SDRAM CKE delay time tCKED 1 0 8 ns SDRAM DQM delay time tDQMD 1 0 8 ns SDRAM FRAME delay time tFMD 1 0 8 ns MPX IOIS16 setup time tIO16S 3 5 ns PCMCIA I...

Page 1073: ...6417751F167 V Item Symbol Min Max Unit Notes DTR hold time tDTRH 1 5 ns DBREQ setup time tDBQS 3 5 ns DBREQ hold time tDBQH 1 5 ns TR setup time tTRS 3 5 ns TR hold time tTRH 1 5 ns BAVL delay time tBAVD 1 0 8 ns TDACK delay time tTDAD 1 0 8 ns ID1 ID0 delay time tIDD 1 0 8 ns Note VDDQ 3 0 to 3 6 V VDD 1 8 V Ta 20 to 75 C CL 30 pF PLL2 on ...

Page 1074: ... read D31 D0 write BS DACKn DA tWDD tWDD tWDD tRDH tRDS tCSD tCSD tRWD tRWD tRSD tRSD tRSD tWED1 tWEDF tWEDF tBSD tBSD tDACD tDACD tDACD tDACD tDACDF tDACDF tDACD RDY WEn DACKn SA IO memory DACKn SA IO memory Legend IO DACK device SA Single address DMA transfer DA Dual address DMA transfer DACK set to active high Figure 23 13 SRAM Bus Cycle Basic Bus Cycle No Wait ...

Page 1075: ... D0 read D31 D0 write BS DACKn DA RDY WEn T1 tAD Tw T2 tAD tRDH tRDS tCSD tRWD tRWD tCSD tRSD tRSD tRSD tWED1 tWEDF tWEDF tRDYH tRDYS tBSD tBSD tDACD tDACD tDACD tDACD tDACD DACKn SA IO memory DACKn SA IO memory Legend IO DACK device SA Single address DMA transfer DA Dual address DMA transfer DACK set to active high Figure 23 14 SRAM Bus Cycle Basic Bus Cycle One Internal Wait ...

Page 1076: ...rite BS DACKn DA RDY WEn T1 tAD Tw Twe T2 tAD tRDH tRDS tCSD tRWD tRWD tCSD tRSD tRSD tRSD tWED1 tWEDF tWEDF tRDYH tRDYS tRDYH tRDYS tBSD tBSD tDACD tDACD tDACD tDACD tDACD DACKn SA IO memory DACKn SA IO memory Legend IO DACK device SA Single address DMA transfer DA Dual address DMA transfer DACK set to active high Figure 23 15 SRAM Bus Cycle Basic Bus Cycle One Internal Wait One External Wait ...

Page 1077: ...H tRDS tCSD tRWD tRWD tCSD tRSD tRSD tRSD tWED1 tWEDF tWEDF tBSD tBSD tDACD tDACD CKIO A25 A0 CSn RD WR RD D31 D0 read D31 D0 write BS DACKn SA IO memory DACKn SA IO memory DACKn DA RDY WEn Legend IO DACK device SA Single address DMA transfer DA Dual address DMA transfer DACK set to active high Figure 23 16 SRAM Bus Cycle Basic Bus Cycle No Wait Address Setup Hold Time Insertion AnS 1 AnH 1 ...

Page 1078: ...n RD WR RD D31 D0 read BS RDY A4 A0 TB2 TB1 TB2 TB1 TB2 TB1 tCSD tAD tRWD tBSD tRDS tBSD tRSD tRSD tRDH tAD tAD tCSD tRWD tRDH tRSD tRDS DACKn SA IO memory DACKn DA tDACD tDACD tDACD tDACD tDACD Legend IO DACK device SA Single address DMA transfer DA Dual address DMA transfer DACK set to active high Figure 23 17 Burst ROM Bus Cycle No Wait ...

Page 1079: ...D t RDH t RSD t RDS t AD t CSD t RDYH t RDYS t RDYH t RDYS t RDYH t RDYS t DACD t DACD t DACD t DACD t RWD t RWD CKIO A25 A5 CSn RD WR RD D31 D0 read BS RDY A4 A0 DACKn SA IO memory DACKn DA Legend IO DACK device SA Single address DMA transfer DA Dual address DMA transfer DACK set to active high Figure 23 18 Burst ROM Bus Cycle 1st Data One Internal Wait One External Wait 2nd 3rd 4th Data One Inte...

Page 1080: ... t AD t RDH t DACD t DACD TB1 TB2 T2 TB1 t AD t CSD t RWD t RDH t RSD t RDS TH1 TS1 TH1 TS1 TH1 TS1 TH1 CKIO A25 A5 CSn RD WR RD D31 D0 read BS RDY A4 A0 DACKn SA IO memory DACKn DA t DACD t DACD Legend IO DACK device SA Single address DMA transfer DA Dual address DMA transfer DACK set to active high Figure 23 19 Burst ROM Bus Cycle No Wait Address Setup Hold Time Insertion AnS 1 AnH 1 ...

Page 1081: ... AD t AD t AD t RDH t RDS t RDH t RDS BS RDY DACKn DA RD t DACD t DACD t DACD t BSD t BSD t BSD t BSD t RSD t RSD CSn t RWD t CSD t RWD t CSD t DACD t DACD t RSD RD WR t RDYH t RDYS t RDYH t RDYS t RDYH t RDYS t RDYH t RDYS DACKn SA IO memory Legend IO DACK device SA Single address DMA transfer DA Dual address DMA transfer DACK set to active high Figure 23 20 Burst ROM Bus Cycle One Internal Wait ...

Page 1082: ...ress Row Row Row H L t AD t AD t AD t RDH c1 t RDS DQMn BS CKE RAS t CASD2 t CASD2 CASS t DACD t DACD t RASD t RASD t DQMD t DQMD CSn t RWD t RWD t BSD t BSD RD WR t CSD t CSD DACKn SA IO memory column Legend IO DACK device SA Single address DMA transfer DA Dual address DMA transfer DACK set to active high Figure 23 21 Synchronous DRAM Auto Precharge Read Bus Cycle Single RCD 1 0 01 CAS Latency 3 ...

Page 1083: ... AD Row Row H L c5 Row t AD t AD t RDH c1 c2 c3 c4 c5 c6 c7 c8 t RDS DQMn BS CKE RAS t CASD2 t CASD2 CASS t DACD t DACD t RASD t RASD t DQMD t DQMD CSn t RWD t RWD t BSD t BSD RD WR t CSD t CSD t AD H L c1 DACKn SA IO memory Legend IO DACK device SA Single address DMA transfer DA Dual address DMA transfer DACK set to active high Figure 23 22 Synchronous DRAM Auto Precharge Read Bus Cycle Burst RCD...

Page 1084: ...Mn BS CKE t AD Row Row H L Row c5 t AD H L c1 t AD t AD t RDH t RDS c1 c2 c3 c4 c5 c6 c7 c8 t CSD t CSD t RWD t RWD t RASD t RASD t BSD t BSD t DQMD t DQMD t DACD t DACD t CASD2 t CASD2 D31 D0 read DACKn SA IO memory Legend IO DACK device SA Single address DMA transfer DA Dual address DMA transfer DACK set to active high Figure 23 23 Synchronous DRAM Normal Read Bus Cycle ACT READ Commands Burst R...

Page 1085: ... t AD Row Row H L Row H L c1 c5 t AD t AD H L t AD t AD t RDH t RDS c1 c2 c3 c4 c5 c6 c7 c8 t CSD t CSD t RWD t RWD t RASD t RASD t BSD t BSD t DQMD t DACD t DACD t CASD2 t CASD2 t DQMD D31 D0 read DACKn SA IO memory Legend IO DACK device SA Single address DMA transfer DA Dual address DMA transfer DACK set to active high Figure 23 24 Synchronous DRAM Normal Read Bus Cycle PRE ACT READ Commands Bur...

Page 1086: ...R RAS CASS DQMn BS CKE t AD t AD H L c1 H L c5 t RDH t RDS c1 c2 c3 c4 c5 c6 c7 c8 t AD t CSD t RWD t CSD t RWD t RASD t RASD t BSD t BSD t DQMD t DQMD t CASD2 t CASD2 t DACD t DACD D31 D0 read DACKn SA IO memory Legend IO DACK device SA Single address DMA transfer DA Dual address DMA transfer DACK set to active high Figure 23 25 Synchronous DRAM Normal Read Bus Cycle READ Command Burst RASD 1 CAS...

Page 1087: ... tAD tAD H L c1 Row Row Row tWDD c1 tWDD DQMn BS CKE RAS tCASD2 tCASD2 CASS tDACD tDACD tRWD tRWD tRASD tRASD tDQMD tDQMD CSn tBSD tBSD RD WR tCSD tCSD D31 D0 write DACKn SA IO memory Legend IO DACK device SA Single address DMA transfer DA Dual address DMA transfer DACK set to active high Figure 23 26 Synchronous DRAM Auto Precharge Write Bus Cycle Single RCD 1 0 01 TPC 2 0 001 TRWL 2 0 010 ...

Page 1088: ...w Row Row t AD H L c5 t WDD c1 t WDD c2 c3 c4 c5 c6 c7 c8 DQMn BS CKE RAS t CASD2 t CASD2 t CASD2 CASS t DACD t DACD t RWD t RWD t RASD t RASD t DQMD CSn t BSD t BSD RD WR t CSD t CSD D31 D0 write DACKn SA IO memory t DQMD Legend IO DACK device SA Single address DMA transfer DA Dual address DMA transfer DACK set to active high Figure 23 27 Synchronous DRAM Auto Precharge Write Bus Cycle Burst RCD ...

Page 1089: ... c1 Row Row Row t AD t WDD c1 t WDD c2 c3 c4 c5 c6 c7 c8 DQMn BS CKE RAS t CASD2 t CASD2 CASS t DACD t DACD t RWD t RWD t RASD t RASD t DQMD t DQMD CSn t BSD t BSD RD WR t CSD t CSD D31 D0 write DACKn SA IO memory Legend IO DACK device SA Single address DMA transfer DA Dual address DMA transfer DACK set to active high Figure 23 28 Synchronous DRAM Normal Write Bus Cycle ACT WRITE Commands Burst RA...

Page 1090: ...ow Row Row t AD t AD t WDD c1 t WDD c2 c3 c4 c5 c6 c7 c8 DQMn BS CKE RAS t CASD2 t CASD2 CASS t DQMD t DQMD t DACD t RWD t RWD t RASD t RASD t DACD CSn t BSD t BSD RD WR t CSD t CSD D31 D0 write DACKn SA IO memory Legend IO DACK device SA Single address DMA transfer DA Dual address DMA transfer DACK set to active high Figure 23 29 Synchronous DRAM Normal Write Bus Cycle PRE ACT WRITE Commands Burs...

Page 1091: ...ank Precharge sel Address DQMn BS CKE RAS CASS CSn RD WR D31 D0 write DACKn SA IO memory Normal write Single address DMA Legend IO DACK device SA Single address DMA transfer DA Dual address DMA transfer DACK set to active high Note In the case of SA DMA only the Tnop cycle is inserted and the DACKn signal is output as shown by the solid line In a normal write the Tnop cycle is omitted and the DACK...

Page 1092: ...harge sel Address tAD tAD H L Row DQMn BS CKE RAS tCASD2 tCASD2 CASS tDQMD tDQMD tRWD tRWD DACKn tRASD tRASD tDACD tDACD CSn tBSD tWDD tWDD RD WR tCSD tCSD D31 D0 write Legend IO DACK device SA Single address DMA transfer DA Dual address DMA transfer DACK set to active high Figure 23 31 Synchronous DRAM Bus Cycle Precharge Command TPC 2 0 001 ...

Page 1093: ...echarge sel Address CSn RD WR RAS CASS DQMn BS DACKn CKE tAD tAD tRWD tRWD tDQMD tDQMD tBSD tDACD tWDD tWDD tCASD2 tCASD2 tCASD2 tCASD2 tRASD tRASD tRASD tRASD tCSD tCSD tCSD tCSD tDACD D31 D0 write Legend IO DACK device SA Single address DMA transfer DA Dual address DMA transfer DACK set to active high Figure 23 32 Synchronous DRAM Bus Cycle Auto Refresh TRAS 1 TRC 2 0 001 ...

Page 1094: ...n BS DACKn CKE TRs1 TRs2 TRs3 TRs4 TRs5 Trc Trc Trc tAD tAD tRWD tRWD tDQMD tDQMD tBSD tDACD tDACD tWDD tWDD tCASD2 tCASD2 tCASD2 tCKED tCKED tCASD2 tRASD tRASD tRASD tRASD tCSD tCSD tCSD tCSD D31 D0 write Legend IO DACK device SA Single address DMA transfer DA Dual address DMA transfer DACK set to active high Figure 23 33 Synchronous DRAM Bus Cycle Self Refresh TRC 2 0 001 ...

Page 1095: ... Precharge sel Address CSn RD WR RAS CASS DQMn BS DACKn CKE tAD tAD tAD tRWD tRWD tRWD tCSD tCSD tCSD tBSD tDQMD tDACD tWDD tWDD tDACD tCASD2 tCASD2 tCASD2 tCASD2 tRASD tRASD tRASD tDQMD D31 D0 write Legend IO DACK device SA Single address DMA transfer DA Dual address DMA transfer DACK set to active high Figure 23 34 a Synchronous DRAM Bus Cycle Mode Register Setting PALL ...

Page 1096: ...k Precharge sel Address CSn RD WR RAS CASS DQMn BS DACKn CKE tAD tAD tAD tRWD tRWD tRWD tCSD tCSD tCSD tBSD tDQMD tDACD tWDD tWDD tDACD tCASD2 tCASD2 tCASD2 tCASD2 tRASD tRASD tRASD tDQMD D31 D0 write Legend IO DACK device SA Single address DMA transfer DA Dual address DMA transfer DACK set to active high Figure 23 34 b Synchronous DRAM Bus Cycle Mode Register Setting SET ...

Page 1097: ...t RDH t RDS CKIO A25 A0 BS RAS CASn CSn RD WR Tr2 Tr1 Tc1 Tc2 Tpc t AD t AD t AD Row column t WDD t WDD t WDD t CASD1 t CASD1 t CASD1 t BSD t BSD t DACD t DACD t DACD t CSD t CSD t DACD t DACD t DACD t RWD t RWD t RASD t RASD t RASD t RDH t RDS 1 2 DACKn SA IO memory DACKn SA IO memory D31 D0 read D31 D0 write Legend IO DACK device SA Single address DMA transfer DA Dual address DMA transfer DACK s...

Page 1098: ... CASn CSn RD WR Address DACKn SA IO memory D31 D0 read t AD t CSD t AD t RASD t RWD t RASD t CASD1 t CASD1 t DACD t DACD t BSD t BSD t RDH t RDS t CASD1 t RASD t RWD t CSD t AD column Legend IO DACK device SA Single address DMA transfer DA Dual address DMA transfer DACK set to active high Figure 23 36 DRAM Bus Cycle EDO Mode RCD 1 0 00 AnW 2 0 000 TRC 2 0 001 ...

Page 1099: ... c2 c8 BS RAS t RASD t RASD t RASD CASn CSn t RWD t CASD1 t CASD1 t CASD1 t CASD1 t CASD1 t BSD t BSD RD WR t CSD t CSD t DACD t DACD t DACD t RWD t RDH t RDS Address DACKn SA IO memory D31 D0 read d1 t RDH t RDS d8 d2 Legend IO DACK device SA Single address DMA transfer DA Dual address DMA transfer DACK set to active high Figure 23 37 DRAM Bus Cycle EDO Mode RCD 1 0 00 AnW 2 0 000 TPC 2 0 001 ...

Page 1100: ...DH d1 t RDS t RDH d8 d7 t RDS BS RAS t RASD t RASD CSn CASn Row c1 c2 c8 RD WR t CSD t CSD t CASD1 t CASD1 t CASD1 t CASD1 t RASD t CASD1 t CASD1 t BSD t BSD t DACD t DACD t DACD t RWD t RWD Address DACKn SA IO memory D31 D0 read Legend IO DACK device SA Single address DMA transfer DA Dual address DMA transfer DACK set to active high Figure 23 38 DRAM Burst Bus Cycle EDO Mode RCD 1 0 01 AnW 2 0 00...

Page 1101: ... d1 t RDS t RDH d8 d2 t RDS BS RAS t RASD t RASD CSn CASn Row c1 c2 c8 RD WR t CSD t CSD t CASD1 t CASD1 t CASD1 t RASD t CASD1 t CASD1 t BSD t BSD t DACD t DACD t DACD t RWD t RWD Address DACKn SA IO memory D31 D0 read Legend IO DACK device SA Single address DMA transfer DA Dual address DMA transfer DACK set to active high Figure 23 39 DRAM Burst Bus Cycle EDO Mode RCD 1 0 01 AnW 2 0 001 TPC 2 0 ...

Page 1102: ...t AD t RDH t RDS t RDH t RDS t CSD t RWD t RWD t CSD t CASD1 t RASD t RASD t CASD1 t CASD1 t CASD1 t CASD1 d8 d2 d1 t BSD t BSD t DACD t DACD t DACD Tc1 Tc1 Tc2 Tce Tc2 Address DACKn SA IO memory D31 D0 read Legend IO DACK device SA Single address DMA transfer DA Dual address DMA transfer DACK set to active high Figure 23 40 DRAM Burst Bus Cycle RAS Down Mode State EDO Mode RCD 1 0 00 AnW 2 0 000 ...

Page 1103: ...t AD t AD t RDH t RDS t RDH t RDS t CSD t RWD t RWD t RASD RAS down mode ended t CSD t CASD1 t CASD1 t CASD1 t CASD1 d8 d2 d1 t BSD t BSD t DACD t DACD Tc2 T2 Tc1 Tce DACKn SA IO memory D31 D0 read Legend IO DACK device SA Single address DMA transfer DA Dual address DMA transfer DACK set to active high Figure 23 41 DRAM Burst Bus Cycle RAS Down Mode Continuation EDO Mode RCD 1 0 00 AnW 2 0 000 ...

Page 1104: ...y DACKn SA IO memory t AD c1 Row c2 c8 t AD t AD t RWD t RWD t RDH t RDS d1 t WDD d1 d2 d8 t BSD t BSD t WDD d2 t RDH t WDD t RDS d8 t WDD t CSD t CSD t DACD t DACD t DACD t CASD1 t CASD1 t CASD1 t CASD1 t CASD1 t RASD t RASD t RASD t DACD t DACD t DACD Legend IO DACK device SA Single address DMA transfer DA Dual address DMA transfer DACK set to active high Figure 23 42 DRAM Burst Bus Cycle Fast P...

Page 1105: ... d1 d2 d8 t BSD t BSD t WDD d2 t RDH t WDD t RDS d3 t WDD t CSD t CSD t DACD t DACD t DACD t CASD1 t CASD1 t CASD1 t CASD1 t CASD1 t RASD t RASD t RASD t DACD t DACD t DACD Tc1 Tc2 Tc2 Tcw Tpc Address D31 D0 read D31 D0 write DACKn SA IO memory DACKn SA IO memory Legend IO DACK device SA Single address DMA transfer DA Dual address DMA transfer DACK set to active high Figure 23 43 DRAM Burst Bus Cy...

Page 1106: ...WDD d2 t RDH t WDD t RDS d8 t WDD t CSD t CSD t DACD t DACD t DACD t CASD1 t CASD1 t CASD1 t CASD1 t CASD1 t RASD t RASD t RASD t DACD t DACD t DACD Tcw Tc1 Tcnw Tc2 Tc1 Tpc Tc2 Tcnw Tcw Address D31 D0 read D31 D0 write DACKn SA IO memory DACKn SA IO memory Legend IO DACK device SA Single address DMA transfer DA Dual address DMA transfer DACK set to active high Figure 23 44 DRAM Burst Bus Cycle Fa...

Page 1107: ...Kn SA IO memory DACKn SA IO memory tAD c1 Row c2 c8 tAD tAD tRWD tRWD tRDH tRDS d1 tWDD tWDD d1 d2 d8 tBSD tBSD tWDD d2 tRDH tWDD tRDS d8 tCSD tCSD tDACD tDACD tDACD tCASD1 tCASD1 tCASD1 tCASD1 tCASD1 tDACD tDACD tDACD tRASD tRASD Legend IO DACK device SA Single address DMA transfer DA Dual address DMA transfer DACK set to active high Figure 23 45 DRAM Burst Bus Cycle RAS Down Mode State Fast Page...

Page 1108: ... tWDD tRDS d8 tWDD tCSD tRASD tDACD tDACD tCASD1 tCASD1 tCASD1 tCASD1 tDACD tDACD Tnop Tc1 Tc2 Tc1 Tc1 Tc2 Tc2 Tc1 Tc2 Address D31 D0 read D31 D0 write DACKn SA IO memory DACKn SA IO memory RAS down mode ended Legend IO DACK device SA Single address DMA transfer DA Dual address DMA transfer DACK set to active high Figure 23 46 DRAM Burst Bus Cycle RAS Down Mode Continuation Fast Page Mode RCD 1 0 ...

Page 1109: ... Trc Trc CKIO A25 A0 CSn RD WR RAS CASn D31 D0 write BS DACKn SA IO memory DACKn SA IO memory tAD tWDD tDACD tDACD tCSD tRWD tRASD tRASD tRASD tCASD1 tCASD1 tCASD1 Legend IO DACK device SA Single address DMA transfer DA Dual address DMA transfer DACK set to active high Figure 23 47 DRAM Bus Cycle DRAM CAS Before RAS Refresh TRAS 2 0 000 TRC 2 0 001 ...

Page 1110: ...Trc Trc Trc CKIO CSn RD WR RAS CASn BS tAD tWDD tDACD tDACD tCSD tRWD tRASD tRASD tRASD tCASD1 tCASD1 tCASD1 A25 A0 D31 D0 write DACKn SA IO memory DACKn SA IO memory Legend IO DACK device SA Single address DMA transfer DA Dual address DMA transfer DACK set to active high Figure 23 48 DRAM Bus Cycle DRAM CAS Before RAS Refresh TRAS 2 0 001 TRC 2 0 001 ...

Page 1111: ...r4 TRr5 Trc Trc Trc CKIO CSn RD WR RAS CASn BS tAD tWDD tDACD tDACD tCSD tRWD tRASD tRASD tRASD tCASD1 tCASD1 tCASD1 A25 A0 D31 D0 write DACKn SA IO memory DACKn SA IO memory Legend IO DACK device SA Single address DMA transfer DA Dual address DMA transfer DACK set to active high Figure 23 49 DRAM Bus Cycle DRAM Self Refresh TRC 2 0 001 ...

Page 1112: ...DD t RWD t CSD t CSD t RWD t RSD t RSD t RSD t WEDF t WED1 t WEDF t DACD t RDH t RDS t RDYH t RDYS t RDYH t RDYS t DACD t AD t AD t WDD t WDD t WDD t RWD t CSD t CSD t RWD t RSD t RSD t RSD t WEDF t WED1 t WEDF t DACD TED TEH t RDH t RDS t DACD 1 2 A25 A0 Legend IO DACK device SA Single address DMA transfer DA Dual address DMA transfer DACK set to active high Figure 23 50 PCMCIA Memory Bus Cycle 1...

Page 1113: ...RSD t ICRSD t ICWSDF t ICWSDF t DACD t RDH t RDS t RDYH t RDYS t RDYH t RDYS t IO16H t IO16S t IO16H t IO16S t DACD t AD t AD t WDD t WDD t WDD t RWD t CSD t CSD t RWD t ICRSD t ICRSD t ICRSD t ICWSDF t ICWSDF t ICWSDF t DACD t RDH t RDS t DACD D15 D0 read D15 D0 write 1 2 A25 A0 Legend IO DACK device SA Single address DMA transfer DA Dual address DMA transfer DACK set to active high Figure 23 51 ...

Page 1114: ...D15 D0 write BS RDY IOIS16 ICIOWR WE3 t BSD t BSD t AD t AD t WDD t WDD t WDD t WDD t WDD t RWD t RWD t AD t CSD t CSD t CSD t ICRSD t ICRSD t ICRSD t ICWSDF t ICWSDF t ICWSDF t ICWSDF t ICWSDF t RDH t RDS t RDYS t RDYH t IO16S t IO16H t RDYS t RDYH Legend IO DACK device SA Single address DMA transfer DA Dual address DMA transfer DACK set to active high Figure 23 52 PCMCIA I O Bus Cycle TED 2 0 00...

Page 1115: ...t WDD t RWD t RWD t WED1 t WED1 t DACD t DACD t RDYH t RDYS t RDYH t RDYS 1st data bus cycle information D31 D29 Access size 000 Byte 001 Word 2 bytes 010 Long 4 bytes 011 Quad 8 bytes 1xx Burst 32 bytes D25 D0 Address 1st data bus cycle information D31 D29 Access size 000 Byte 001 Word 2 bytes 010 Long 4 bytes 011 Quad 8 bytes 1xx Burst 32 bytes D25 D0 Address 1 2 Legend IO DACK device SA Single ...

Page 1116: ...D1 t WED1 D0 t RWD t RWD A t WDD t WDD t WDD 1 2 3 1st data bus cycle information D31 D29 Access size 000 Byte 001 Word 2 bytes 010 Long 4 bytes 011 Quad 8 bytes 1xx Burst 32 bytes D25 D0 Address 1st data bus cycle information D31 D29 Access size 000 Byte 001 Word 2 bytes 010 Long 4 bytes 011 Quad 8 bytes 1xx Burst 32 bytes D25 D0 Address 1st data bus cycle information D31 D29 Access size 000 Byte...

Page 1117: ... RWD t RWD A t WDD D7 D3 D1 D2 t WDD t RDH t RDS t RDYS t RDYH t RDYH 1 2 1st data bus cycle information D31 D29 Access size 000 Byte 001 Word 2 bytes 010 Long 4 bytes 011 Quad 8 bytes 1xx Burst 32 bytes D25 D0 Address 1st data bus cycle information D31 D29 Access size 000 Byte 001 Word 2 bytes 010 Long 4 bytes 011 Quad 8 bytes 1xx Burst 32 bytes D25 D0 Address Legend IO DACK device SA Single addr...

Page 1118: ...D t CSD t RDYS t RDYH t DACD t DACD t RWD t RWD A t WDD t WDD t WDD t RDYS t RDYH 1 1st data bus cycle information D31 D29 Access size 000 Byte 001 Word 2 bytes 010 Long 4 bytes 011 Quad 8 bytes 1xx Burst 32 bytes D25 D0 Address 1st data bus cycle information D31 D29 Access size 000 Byte 001 Word 2 bytes 010 Long 4 bytes 011 Quad 8 bytes 1xx Burst 32 bytes D25 D0 Address 2 Legend IO DACK device SA...

Page 1119: ... t AD t AD T1 Tw Twe T2 t DACD t DACD t RSD t RSD t RSD t RSD t RSD t RSD t RSD t RSD t WED1 t WED1 t WEDF t WED1 t WEDF t WED1 t WEDF t WED1 t CSD t CSD t DACD t BSD t BSD t BSD t BSD t BSD t BSD t DACD t DACD t RWD t RWD t RSD t AD t AD t RDH t RDS t RDH t RDS t RDH t RDS DACKn SA IO memory 2 3 Legend IO DACK device SA Single address DMA transfer DA Dual address DMA transfer DACK set to active h...

Page 1120: ...5 A0 TS1 T1 T2 TH1 tRSD tRSD tWED1 tWEDF tWED1 tCSD tCSD tDACD tBSD tBSD tDACD tRWD tRWD tRSD tAD tAD tRDH tRDS DACKn SA IO memory tDACD tDACD Legend IO DACK device SA Single address DMA transfer DA Dual address DMA transfer DACK set to active high Figure 23 58 Memory Byte Control SRAM Bus Cycle Basic Read Cycle No Wait Address Setup Hold Time Insertion AnS 0 1 AnH 1 0 01 ...

Page 1121: ...ck pulse width low tTCLKWL 4 4 4 4 Pcyc 1 23 59 Timer clock rise time tTCLKr 0 8 0 8 0 8 0 8 Pcyc 1 23 59 Timer clock fall time tTCLKf 0 8 0 8 0 8 0 8 Pcyc 1 23 59 Oscillation settling time tROSC 3 3 3 3 s 23 60 SCI Input clock cycle asyn chronous tScyc 4 4 4 4 Pcyc 1 23 61 Input clock cycle syn chronous tScyc 6 6 6 6 Pcyc 1 23 61 Input clock pulse width tSCKW 0 4 0 6 0 4 0 6 0 4 0 6 0 4 0 6 tScyc...

Page 1122: ... DMAC DREQn setup time tDRQS 2 2 5 3 5 3 5 ns 23 64 DREQn hold time tDRQH 1 5 1 5 1 5 1 5 ns 23 64 DRAKn delay time tDRAKD 1 5 5 3 1 5 5 3 1 5 6 1 5 6 ns 23 64 INTC NMI pulse width high tNMIH 5 5 5 5 tcyc 23 69 Normal or sleep mode 30 30 30 30 ns 23 69 Standby mode NMI pulse width low tNMIL 5 5 5 5 tcyc 23 69 Normal or sleep mode 30 30 30 30 ns 23 69 Standby mode H UDI Input clock cycle tTCKcyc 50...

Page 1123: ...odule Item Symbol Min Max Min Max Min Max Min Max Unit Figure Notes H UDI TDI TMS setup time tTDIS 15 15 15 15 ns 23 67 TDI TMS hold time tTDIH 15 15 15 15 ns 23 67 TDO delay time tTDO 0 10 0 10 0 10 0 10 ns 23 67 ASE PINBRK pulse width tPINBRK 2 2 2 2 Pcyc 1 23 68 Notes 1 Pcyc P clock cycles 2 VDDQ 3 0 to 3 6 V VDD 1 5 V Ta 20 to 75 C 4 CL 30 pF PLL2 on 3 This is the case when the device in use i...

Page 1124: ... time tROSC 3 s 23 60 SCI Input clock cycle asynchronous tScyc 4 Pcyc 1 23 61 Input clock cycle synchronous tScyc 6 Pcyc 1 23 61 Input clock pulse width tSCKW 0 4 0 6 tScyc 23 61 Input clock rise time tSCKr 0 8 Pcyc 1 23 61 Input clock fall time tSCKf 0 8 Pcyc 1 23 61 Transfer data delay time tTXD 30 ns 23 62 Receive data setup time synchronous tRXS 0 8 Pcyc 1 23 62 Receive data hold time synchron...

Page 1125: ...69 Standby mode Input clock cycle tTCKcyc 50 ns 23 65 23 67 Input clock pulse width high tTCKH 15 ns 23 65 Input clock pulse width low tTCKL 15 ns 23 65 Input clock rise time tTCKr 10 ns 23 65 Input clock fall time tTCKf 10 ns 23 65 ASEBRK setup time tASEBRKS 10 tcyc 23 66 ASEBRK hold time tASEBRKH 10 tcyc 23 66 TDI TMS setup time tTDIS 15 ns 23 67 TDI TMS hold time tTDIH 15 ns 23 67 H UDI TDO del...

Page 1126: ...457EJ0301 Rev 3 01 Sep 24 2013 TCLK tTCLKf tTCLKWH tTCLKWL tTCLKr Figure 23 59 TCLK Input Timing RTC internal clock VDD RTC Oscillation settling time tROSC VDD RTC min Figure 23 60 RTC Oscillation Settling Time at Power On SCK SCK2 tSCKf tScyc tSCKW tSCKr Figure 23 61 SCK Input Clock Timing ...

Page 1127: ...73 of 1128 Sep 24 2013 tTXD SCK TXD RXD tTXD tRXS tRXH tScyc Figure 23 62 SCI I O Synchronous Mode Clock Timing tPORTD tPORTD CKIO Ports 31 0 read Ports 31 0 write tPORTS tPORTH Figure 23 63 I O Port Input Output Timing tDRAKD tDRQH tDRQH tDRQS tDRQS CKIO DREQn DRAKn Figure 23 64 a DREQ DRAK Timing ...

Page 1128: ... D0 READ DBREQ BAVL TR tBAVD tBAVD tTRH 2 tTRS tDTRH tDTRS 1 1 2CKIO cycle tDTRS 18 ns 100 MHz 2 DTR 1CKIO cycle 10 ns 100 MHz tDTRS tDTRH DTR 10 ns Figure 23 64 b DBREQ TR Input Timing and BAVL Output Timing tTCKcyc tTCKH tTCKL tTCKr tTCKf 1 2VDDQ VIH VIH VIL VIL VIH 1 2VDDQ Note When clock is input from TCK pin Figure 23 65 TCK Input Timing ...

Page 1129: ...1 Rev 3 01 Page 1075 of 1128 Sep 24 2013 ASEBRK BRKACK RESET tASEBRKH tASEBRKS Figure 23 66 RESET Hold Timing TDI TMS TCK TDO tTCKcyc tTDO tTDIH tTDIS Figure 23 67 H UDI Data Transfer Timing ASEBRK tPINBRK Figure 23 68 Pin Break Timing NMI tNMIL tNMIH Figure 23 69 NMI Input Timing ...

Page 1130: ... ns 23 72 IDSEL Input setup time tPCISU 3 0 3 5 1 3 0 3 5 1 ns 23 72 Output data delay time tPCIVAL 10 8 ns 23 71 Tri state drive delay time tPCION 10 10 ns 23 71 Tri state high impedance delay time tPCIOFF 12 12 ns 23 71 Input hold time tPCIH 1 5 1 5 ns 23 72 AD31 AD0 C BE3 C BE0 PAR PCIFRAME IRDY TRDY PCISTOP PCILOCK DEVSEL PERR Input setup time tPCISU 3 0 3 5 1 3 0 3 5 1 ns 23 72 Output data de...

Page 1131: ...72 IDSEL Input setup time tPCISU 3 0 3 5 3 0 3 5 ns 23 72 Output data delay time tPCIVAL 10 10 ns 23 71 Tri state drive delay time tPCION 10 10 ns 23 71 Tri state high impedance delay time tPCIOFF 12 12 ns 23 71 Input hold time tPCIH 1 1 ns 23 72 AD31 AD0 C BE3 C BE0 PAR PCIFRAME IRDY TRDY PCISTOP PCILOCK DEVSEL PERR Input setup time tPCISU 3 0 3 5 3 0 3 5 ns 23 72 Output data delay time tPCIVAL 1...

Page 1132: ...Page 1078 of 1128 R01UH0457EJ0301 Rev 3 01 Sep 24 2013 0 5VDDQ VH VH tPCIf tPCIr VL VL 0 5VDDQ VH tPCILOW tPCIHIGH tPCICYC Figure 23 70 PCI Clock Input Timing PCICLK 0 4VDDQ 0 4VDDQ tPCION tPCIOFF tPCIVAL Output delay 3 state output Figure 23 71 Output Signal Timing ...

Page 1133: ... Figure Output data delay time tPCIPORTD 10 ns 23 73 Input hold time tPCIPORTH 1 5 ns 23 73 PCIREQ2 MD9 PCIREQ3 MD10 PCIREQ4 Input setup time tPCIPORTS 3 5 ns 23 73 PCIGNT4 PCIGNT1 Output data delay time tPCIPORTD 10 ns 23 73 Note Ta 40 to 85 C for the HD6417751RBA240HV Table 23 28 PCIC Signal Timing With PCIREQ PCIGNT Port Settings in Non Host Mode 2 HD6417751BP167 V HD6417751F167 V VDDQ 3 0 to 3...

Page 1134: ...l Characteristics SH7751 Group SH7751R Group Page 1080 of 1128 R01UH0457EJ0301 Rev 3 01 Sep 24 2013 CKIO PCIREQn read PCIREQn PCIGNTn write tPCIPORTH tPCIPORTD tPCIPORTD tPCIPORTS Figure 23 73 I O Port Input Output Timing ...

Page 1135: ... 1 5 V VDDQ 3 3 0 3 V Input pulse level VSSQ to 3 0 V VSSQ to VDDQ for RESET TRST NMI and ASEBRK BRKACK Input rise fall time 1 ns The output load circuit is shown in figure 23 74 IOL IOH CL VREF LSI output pin DUT output Notes 1 2 CL is the total value including the capacitance of the test jig etc The capacitance of each pin is set to 30 pF IOL and IOH values are as shown in table 23 10 Permissibl...

Page 1136: ...e equal to or larger than the stipulated value 30 pF is connected to the LSI pins When connecting an external device with a load capacitance exceeding the regulation use the chart in figure 23 75 as reference for system design Note that if the load capacitance to be connected exceeds the range shown in figure 23 75 the graph will not be a straight line 4 0 ns 3 0 ns 2 0 ns 1 0 ns 0 0 ns 0 pF 25 pF...

Page 1137: ...E0A 0008 H 1E0A 0008 32 Write only Pck TMU TSTR2 H FE10 0004 H 1E10 0004 8 H 00 Held Held Held Pck TMU TCOR3 H FE10 0008 H 1E10 0008 32 H FFFF FFFF Held Held Held Pck TMU TCNT3 H FE10 000C H 1E10 000C 32 H FFFF FFFF Held Held Held Pck TMU TCR3 H FE10 0010 H 1E10 0010 16 H 0000 Held Held Held Pck TMU TCOR4 H FE10 0014 H 1E10 0014 32 H FFFF FFFF Held Held Held Pck TMU TCNT4 H FE10 0018 H 1E10 0018 3...

Page 1138: ...44 H 1E20 0044 32 H 00000000 Held Held Held Pck PCIC PCICR H FE20 0100 H 1E20 0100 2 32 H 00000000 Held Held Held Pck PCIC PCILSR0 H FE20 0104 H 1E20 0104 32 H 00000000 Held Held Held Pck PCIC PCILSR1 H FE20 0108 H 1E20 0108 32 H 00000000 Held Held Held Pck PCIC PCILAR0 H FE20 010C H 1E20 010C 32 H 00000000 Held Held Held Pck PCIC PCILAR1 H FE20 0110 H 1E20 0110 32 H 00000000 Held Held Held Pck PC...

Page 1139: ...0 Held Held Held Pck PCIC PCIPAR H FE20 01C0 H 1E20 01C0 32 Undefined Held Held Held Pck PCIC PCIMBR H FE20 01C4 H 1E20 01C4 32 Undefined Held Held Held Pck PCIC PCIIOBR H FE20 01C8 H 1E20 01C8 32 Undefined Held Held Held Pck PCIC PCIPINT H FE20 01CC H 1E20 01CC 32 H 00000000 Held Held Held Pck PCIC PCIPINTM H FE20 01D0 H 1E20 01D0 32 H 00000000 Held Held Held Pck PCIC PCICLKR H FE20 01D4 H 1E20 0...

Page 1140: ...Ick CCN PTEA H FF00 0034 H 1F00 0034 32 Undefined Undefined Held Held Ick CCN QACR0 H FF00 0038 H 1F00 0038 32 Undefined Undefined Held Held Ick CCN QACR1 H FF00 003C H 1F00 003C 32 Undefined Undefined Held Held Ick UBC BARA H FF20 0000 H 1F20 0000 32 Undefined Held Held Held Ick UBC BAMRA H FF20 0004 H 1F20 0004 8 Undefined Held Held Held Ick UBC BBRA H FF20 0008 H 1F20 0008 16 H 0000 Held Held H...

Page 1141: ...F94 xxxx 8 Write only Bck DMAC SAR0 H FFA0 0000 H 1FA0 0000 32 Undefined Undefined Held Held Bck DMAC DAR0 H FFA0 0004 H 1FA0 0004 32 Undefined Undefined Held Held Bck DMAC DMATCR0 H FFA0 0008 H 1FA0 0008 32 Undefined Undefined Held Held Bck DMAC CHCR0 H FFA0 000C H 1FA0 000C 32 H 0000 0000 H 0000 0000 Held Held Bck DMAC SAR1 H FFA0 0010 H 1FA0 0010 32 Undefined Undefined Held Held Bck DMAC DAR1 H...

Page 1142: ...ed Undefined Held Held Bck DMAC CHCR6 H FFA0 007C H 1FA0 007C 32 H 0000 0000 H 0000 0000 Held Held Bck DMAC SAR7 H FFA0 0080 H 1FA0 0080 32 Undefined Undefined Held Held Bck DMAC DAR7 H FFA0 0084 H 1FA0 0084 32 Undefined Undefined Held Held Bck DMAC DMATCR7 H FFA0 0088 H 1FA0 0088 32 Undefined Undefined Held Held Bck DMAC CHCR7 H FFA0 008C H 1FA0 008C 32 H 0000 0000 H 0000 0000 Held Held Bck CPG F...

Page 1143: ... H 1FD0 0000 16 H 0000 2 H 0000 2 Held Held Pck INTC IPRA H FFD0 0004 H 1FD0 0004 16 H 0000 H 0000 Held Held Pck INTC IPRB H FFD0 0008 H 1FD0 0008 16 H 0000 H 0000 Held Held Pck INTC IPRC H FFD0 000C H 1FD0 000C 16 H 0000 H 0000 Held Held Pck INTC IPRD H FFD0 0010 H 1FD0 0010 16 H DA74 H DA74 Held Held Pck TMU TOCR H FFD8 0000 H 1FD8 0000 8 H 00 H 00 Held Held Pck TMU TSTR H FFD8 0004 H 1FD8 0004 ...

Page 1144: ...Held Held Pck SCIF SCFTDR2 H FFE8 000C H 1FE8 000C 8 Undefined Undefined Held Held Pck SCIF SCFSR2 H FFE8 0010 H 1FE8 0010 16 H 0060 H 0060 Held Held Pck SCIF SCFRDR2 H FFE8 0014 H 1FE8 0014 8 Undefined Undefined Held Held Pck SCIF SCFCR2 H FFE8 0018 H 1FE8 0018 16 H 0000 H 0000 Held Held Pck SCIF SCFDR2 H FFE8 001C H 1FE8 001C 16 H 0000 H 0000 Held Held Pck SCIF SCSPTR2 H FFE8 0020 H 1FE8 0020 16...

Page 1145: ... 28 0 16 0 15 0 3 0 5 0 7 0 11 30 8 30 6 30 4 1 40 Reference Symbol Dimension in Millimeters Min Nom Max L1 ZE ZD y x c b1 bp A HD A2 E D A1 c1 e e L HE 1 2 3 129 128 192 193 65 64 1 256 F x M y D E D E p Z Z b H D H E Detail F 1 1 2 c L A L A A 1 p 1 Terminal cross section b c c b θ θ NOTE 1 DIMENSIONS 1 AND 2 DO NOT INCLUDE MOLD FLASH 2 DIMENSION 3 DOES NOT INCLUDE TRIM OFFSET P HQFP256 28x28 0 ...

Page 1146: ...S y v S y1 S A B S A A PRBG0256DE B P BGA256 27x27 1 27 D E SD SE ZD ZE MASS Typ 3 0g BP 256A BP 256AV RENESAS Code JEITA Package Code Previous Code 0 20 0 35 y1 0 635 0 635 w v 0 30 27 0 2 5 0 7 0 6 0 5 0 90 0 75 0 60 1 27 0 20 27 0 y x b A Reference Symbol Dimension in Millimeters Min Nom Max A1 e e e φ b φ M M φ0 10 4 E D S S D E Figure B 2 Package Dimensions 256 pin BGA Devices Other than HD64...

Page 1147: ...45 0 50 0 40 0 40 0 55 0 35 0 40 0 45 2 00 17 00 0 08 v w 0 9 0 9 y1 0 20 0 20 0 15 Previous Code JEITA Package Code RENESAS Code 0 9g MASS Typ ZE ZD Z D ZE S D SE SE SD E D P FBGA292 17x17 0 80 PRBG0292GA A 1 1 A B A S S y S w B S w A v S y1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 B C D E F G H J K L M N P R T U V W Y A A e e B A S φ b φ M 4 E D Figure B 3 Package Dimensions 292 pin BGA ...

Page 1148: ...6 5 4 3 2 1 S A B A 1 A M v y S 4 E 1 E D1 D e 0 20 0 30 0 35 y1 1 435 1 435 w v 0 15 27 0 2 6 0 70 0 60 0 50 0 85 0 75 0 65 1 27 0 20 27 0 24 0 24 0 y x b A Reference Symbol Dimension in Millimeters Min Nom Max A1 e E1 D1 ZE ZD E D MASS Typ 2 8g RENESAS Code JEITA Package Code Previous Code P BGA256 27x27 1 27 PRBG0256DM A y1 S S w A S w B φb φ Figure B 4 Package Dimensions 256 pin BGA HD6417751R...

Page 1149: ...er PLL1 PLL2 CPU Clock Bus Clock Peripheral Module Clock FRQCR Initial Value 0 0 Off On On 6 3 2 3 2 H 0E1A 1 0 1 Off On On 6 1 1 H 0E23 2 0 On On On 3 1 1 2 H 0E13 3 0 1 1 Off On On 6 2 1 H 0E13 4 1 0 0 On On On 3 3 2 3 4 H 0E0A 5 1 Off On On 6 3 3 2 H 0E0A 6 1 0 Off Off Off 1 1 2 1 2 H 0808 Notes 1 The multiplication factor of 1 2 frequency divider is solely determined by the clock operating mod...

Page 1150: ... The multiplication factor of PLL1 is solely determined by the clock operating mode 2 For the ranges input clock frequency see the description of the EXTAL clock input frequency fEX and the CKIO clock output fOP in section 23 3 1 Clock and Control Signal Timing Table C 3 Area 0 Memory Map and Bus Width Pin Value MD6 MD4 MD3 Memory Type Bus Width 0 0 0 Reserved Cannot be used Reserved Cannot be use...

Page 1151: ...Clock Input Pin Value MD8 Clock Input 0 External input clock 1 Crystal resonator Table C 7 PCI Mode Pin Value Mode MD10 MD9 Mode 0 0 0 PCI host with external clock input 1 0 1 PCI host with feedback input clock from CKIO 2 1 0 PCI non host with external clock input 3 1 1 PCI disabled Note When exiting standby mode or hardware standby mode using a power on reset do not change the PCI mode ...

Page 1152: ...Appendix C Mode Pin Settings SH7751 Group SH7751R Group Page 1098 of 1128 R01UH0457EJ0301 Rev 3 01 Sep 24 2013 ...

Page 1153: ... O H H O 4 H L O 4 Z CS6 CS0 O H PZ H Z 13 Z 13 H 5 Z 13 Z RAS O H PZ O 4 Z 13 Z 13 O 3 Z 13 O 3 Z RD CASS FRAME O H PZ O 4 Z Z 13 O 3 Z 13 O 3 Z RD WR O H PZ H Z 13 Z 13 H 5 Z 13 Z RDY I PI PI I 12 I 12 I 12 I 12 I CAS3 DQM3 O H PZ O 4 Z 13 Z 13 O 3 Z 13 O 3 Z CAS2 DQM2 O H PZ O 4 Z 13 Z 13 O 3 Z 13 O 3 Z CAS1 DQM1 O H PZ O 4 Z 13 Z 13 O 3 Z 13 O 3 Z CAS0 DQM0 O H PZ O 4 Z 13 Z 13 O 3 Z 13 O 3 Z ...

Page 1154: ... I 11 I 11 I 11 I 11 I DMAC DRAK1 DRAK0 O L L L L Z 11 O 6 O Z DMAC MD0 SCK2 I O I 17 I 17 I 11 I 11 I 11 Z 11 O 6 I 11 O I SCIF RXD I PI PI I 11 I 11 I 11 I 11 I SCI SCK I O PI PI I 11 I 11 I 11 Z 11 O 6 I 11 O Z SCI MD1 TXD2 I O I 17 I 17 Z 11 Z 11 Z 11 O 6 Z 11 O Z SCIF MD2 RXD2 I I 17 I 17 I 11 I 11 I 11 I 11 I SCIF TxD I O PI PI Z 11 O Z 11 O Z 11 O 6 O Z SCI MD8 RTS2 I O I 17 I 17 I 11 I 11 ...

Page 1155: ...Z SERR I O PZ PZ IOZ 1 0 IOZ 10 Z 10 Z 10 PZ PZ Z PERR I O PZ PZ IOZ 1 0 IOZ 10 Z 10 Z 10 PZ PZ Z PCILOCK I O PZ PZ IZ 10 IZ 10 Z 10 Z 10 PZ PZ Z PCISTOP I O PZ PZ IOZ 1 0 IOZ 10 Z 10 Z 10 PZ PZ Z DEVSEL I O PZ PZ IOZ 1 0 IOZ 10 Z 10 Z 10 PZ PZ Z TRDY I O PZ PZ IOZ 1 0 IOZ 10 Z 10 Z 10 PZ PZ Z IRDY I O PZ PZ IOZ 1 0 IOZ 10 Z 10 Z 10 PZ PZ Z PCIFRAME I O PZ PZ IOZ 1 0 IOZ 10 Z 10 Z 10 PZ PZ Z PCIRE...

Page 1156: ...tandby Notes PCIREQ3 MD10 I O I 17 I 17 Z 10 Z 10 IO 11 16 I 10 Z 10 IO 10 16 PI PZ IO 10 16 Z Values in paren thesis are when using PORT PCIREQ1 GNTIN I PI PI I 10 I 10 I 10 I 10 PI PI Z PCIGNT4 PCIGNT2 O Z Z O Z K K Z K Z Z K Z Values in paren thesis are when using PORT PCIGNT1 REQOUT O Z Z O O K K Z H Z PCICLK I I I I I I I I I Z PCIRST O L L K K K K L L Z IDSEL I PI I PI I PI I PI I Z INTA O P...

Page 1157: ...ues in paren thesis are when using PORT CBE3 CBE0 Z Z Z Z Z Z Z PAR O Z Z Z Z Z Z Z SERR Z Z Z Z Z Z Z PERR Z Z Z Z Z Z Z PCILOCK Z Z Z Z Z Z Z PCISTOP Z Z Z Z Z Z Z DEVSEL Z Z Z Z Z Z Z TRDY Z Z Z Z Z Z Z IRDY Z Z Z Z Z Z Z PCIFRAME Z Z Z Z Z Z Z PCIREQ4 Z Z Z Z Z Z Z PCIREQ2 MD9 I O I 17 I 17 Z Z Z Z Z PCIREQ3 MD10 I O I 17 I 17 Z Z Z Z Z PCIREQ1 Z Z Z Z Z Z Z PCIGNT4 PCIGNT2 O Z Z Z Z Z Z Z PCI...

Page 1158: ...O depending on register setting FRQCR CKOEN 9 Z or O depending on register setting STBCR STHZ 10 Pullup depending on register setting PCICR PCIPUP 11 Pullup depending on register setting STBCR PPU 12 Pullup depending on register setting BCR1 IPUP 13 Pullup depending on register setting BCR1 OPUP 14 Pullup depending on register setting BCR1 DPUP 15 Pullup depending on register setting BCR2 PORTEN 1...

Page 1159: ...l up to 3 3 V PCILOCK I O Pull up to 3 3 V PCISTOP I O Pull up to 3 3 V DEVSEL I O Pull up to 3 3 V TRDY I O Pull up to 3 3 V IRDY I O Pull up to 3 3 V PCIFRAME I O Pull up to 3 3 V PCIREQ4 PCIREQ2 I O Pull up to 3 3 V PCIREQ1 I Pull up to 3 3 V PCIGNT4 PCIGNT2 O Pull up to 3 3 V PCIGNT1 O Pull up to 3 3 V PCICLK I Pull up to 3 3 V PCIRST O Leave unconnected IDSEL I Pull down to low level when IDS...

Page 1160: ...Appendix E Synchronous DRAM Address Multiplexing Tables SH7751 Group SH7751R Group Page 1106 of 1128 R01UH0457EJ0301 Rev 3 01 Sep 24 2013 ...

Page 1161: ...s 1 BUS 32 16M 512k 16b 2 2 AMX 0 AMXEXT 0 16M column addr 8bit 4MB LSI Address Pins RAS Cycle CAS Cycle Synchronous DRAM Address Pins Function A14 A13 A21 A21 A11 BANK selects bank address A12 A20 H L A10 Address precharge setting A11 A19 0 A9 A10 A18 0 A8 A9 A17 A9 A7 A8 A16 A8 A6 A7 A15 A7 A5 A6 A14 A6 A4 A5 A13 A5 A3 A4 A12 A4 A2 A3 A11 A3 A1 A2 A10 A2 A0 Address A1 Not used A0 Not used ...

Page 1162: ...AMX 0 AMXEXT 1 16M column addr 8bit 4MB LSI Address Pins RAS Cycle CAS Cycle Synchronous DRAM Address Pins Function A14 A13 A20 A20 A11 BANK selects bank address A12 A21 H L A10 Address precharge setting A11 A19 0 A9 A10 A18 0 A8 A9 A17 A9 A7 A8 A16 A8 A6 A7 A15 A7 A5 A6 A14 A6 A4 A5 A13 A5 A3 A4 A12 A4 A2 A3 A11 A3 A1 A2 A10 A2 A0 Address A1 Not used A0 Not used ...

Page 1163: ...X 1 AMXEXT 0 16M column addr 9bit 8MB LSI Address Pins RAS Cycle CAS Cycle Synchronous DRAM Address Pins Function A14 A13 A22 A22 A11 BANK selects bank address A12 A21 H L A10 Address precharge setting A11 A20 0 A9 A10 A19 A10 A8 A9 A18 A9 A7 A8 A17 A8 A6 A7 A16 A7 A5 A6 A15 A6 A4 A5 A14 A5 A3 A4 A13 A4 A2 A3 A12 A3 A1 A2 A11 A2 A0 Address A1 Not used A0 Not used ...

Page 1164: ...X 1 AMXEXT 1 16M column addr 9bit 8MB LSI Address Pins RAS Cycle CAS Cycle Synchronous DRAM Address Pins Function A14 A13 A21 A21 A11 BANK selects bank address A12 A22 H L A10 Address precharge setting A11 A20 0 A9 A10 A19 A10 A8 A9 A18 A9 A7 A8 A17 A8 A6 A7 A16 A7 A5 A6 A15 A6 A4 A5 A14 A5 A3 A4 A13 A4 A2 A3 A12 A3 A1 A2 A11 A2 A0 Address A1 Not used A0 Not used ...

Page 1165: ...lumn addr 8bit 16MB LSI Address Pins RAS Cycle CAS Cycle Synchronous DRAM Address Pins Function A16 A15 A23 A23 A13 A14 A22 A22 A12 BANK selects bank address A13 A21 0 A11 A12 A20 H L A10 Address precharge setting A11 A19 0 A9 A10 A18 0 A8 A9 A17 A9 A7 A8 A16 A8 A6 A7 A15 A7 A5 A6 A14 A6 A4 A5 A13 A5 A3 A4 A12 A4 A2 A3 A11 A3 A1 A2 A10 A2 A0 Address A1 Not used A0 Not used ...

Page 1166: ...umn addr 9bit 32MB LSI Address Pins RAS Cycle CAS Cycle Synchronous DRAM Address Pins Function A16 A15 A24 A24 A13 A14 A23 A23 A12 BANK selects bank address A13 A22 0 A11 A12 A21 H L A10 Address precharge setting A11 A20 0 A9 A10 A19 A10 A8 A9 A18 A9 A7 A8 A17 A8 A6 A7 A16 A7 A5 A6 A15 A6 A4 A5 A14 A5 A3 A4 A13 A4 A2 A3 A12 A3 A1 A2 A11 A2 A0 Address A1 Not used A0 Not used ...

Page 1167: ... 4 64M column addr 8bit 8MB LSI Address Pins RAS Cycle CAS Cycle Synchronous DRAM Address Pins Function A15 A14 A22 A22 A12 A13 A21 A21 A11 BANK selects bank address A12 A20 H L A10 Address precharge setting A11 A19 0 A9 A10 A18 0 A8 A9 A17 A9 A7 A8 A16 A8 A6 A7 A15 A7 A5 A6 A14 A6 A4 A5 A13 A5 A3 A4 A12 A4 A2 A3 A11 A3 A1 A2 A10 A2 A0 Address A1 Not used A0 Not used ...

Page 1168: ... 5 64M column addr 8bit 8MB LSI Address Pins RAS Cycle CAS Cycle Synchronous DRAM Address Pins Function A15 A14 A22 A22 A12 BANK selects bank address A13 A21 0 A11 A12 A20 H L A10 Address precharge setting A11 A19 0 A9 A10 A18 0 A8 A9 A17 A9 A7 A8 A16 A8 A6 A7 A15 A7 A5 A6 A14 A6 A4 A5 A13 A5 A3 A4 A12 A4 A2 A3 A11 A3 A1 A2 A10 A2 A0 Address A1 Not used A0 Not used ...

Page 1169: ... 64M column addr 10bit 64MB LSI Address Pins RAS Cycle CAS Cycle Synchronous DRAM Address Pins Function A15 A25 A25 A13 A14 A24 A24 A12 BANK selects bank address A13 A23 0 A11 A12 A22 H L A10 Address precharge setting A11 A21 A11 A9 A10 A20 A10 A8 A9 A19 A9 A7 A8 A18 A8 A6 A7 A17 A7 A5 A6 A16 A6 A4 A5 A15 A5 A3 A4 A14 A4 A2 A3 A13 A3 A1 A2 A12 A2 A0 Address A1 Not used A0 Not used ...

Page 1170: ...lumn addr 9bit 64MB LSI Address Pins RAS Cycle CAS Cycle Synchronous DRAM Address Pins Function A16 A25 A25 A14 A15 A24 A24 A13 BANK selects bank address A14 A23 0 A12 A13 A22 0 A11 A12 A21 H L A10 Address precharge setting A11 A20 0 A9 A10 A19 A10 A8 A9 A18 A9 A7 A8 A17 A8 A6 A7 A16 A7 A5 A6 A15 A6 A4 A5 A14 A5 A3 A4 A13 A4 A2 A3 A12 A3 A1 A2 A11 A2 A0 Address A1 Not used A0 Not used ...

Page 1171: ...lumn addr 8bit 2MB LSI Address Pins RAS Cycle CAS Cycle Synchronous DRAM Address Pins Function A13 A12 A20 A20 A10 BANK selects bank address A11 A19 H L A9 Address precharge setting A10 A18 0 A8 A9 A17 A9 A7 A8 A16 A8 A6 A7 A15 A7 A5 A6 A14 A6 A4 A5 A13 A5 A3 A4 A12 A4 A2 A3 A11 A3 A1 A2 A10 A2 A0 Address A1 Not used A0 Not used Note Example configurations of synchronous DRAM ...

Page 1172: ...Appendix E Synchronous DRAM Address Multiplexing Tables SH7751 Group SH7751R Group Page 1118 of 1128 R01UH0457EJ0301 Rev 3 01 Sep 24 2013 ...

Page 1173: ...Figure F 1 Instruction Prefetch Figure F 1 presupposes a case in which the instruction ADD indicated by the program counter PC and the address H 04000002 instruction prefetch are executed simultaneously It is also assumed that the program branches to an area other than area 1 after executing the following JMP instruction and delay slot instruction In this case the program flow is unpredictable and...

Page 1174: ...Appendix E Synchronous DRAM Address Multiplexing Tables SH7751 Group SH7751R Group Page 1120 of 1128 R01UH0457EJ0301 Rev 3 01 Sep 24 2013 ...

Page 1175: ...t is recommended that the power on sequence be completed in as short a time as possible When the LSI is mounted on a board and connected to other elements ensure that 0 3 V Vin VDDQ 0 3 V In addition the time limit for the rise of either power supply VDDQ or power supply VDD from VDDQ 1 0 V or VDD 0 5 V respectively to above the minimum values in the LSI s guaranteed operation voltage range VDDQ m...

Page 1176: ...methods 1 to 3 below may be used to avoid the problem by stopping PLL2 oscillation temporarily 1 As shown in figure G 1 select mode 6 1 immediately after power on select the desired clock mode once the above conditions A are satisfied and cancel the power on reset 2 After starting with clock operation mode 6 1 selected change FRQCR to specify the desired frequency clock Note It is not possible to ...

Page 1177: ...ination MD0 low MD1 high MD2 high 2 Frequency dividers 1 and 2 off PLL1 off PLL2 off 3 Frequencies relative to input clock CPU clock 1 Bus clock 1 2 Peripheral module clock 1 2 4 Input clock frequency range 1 to 66 7 MHz II SH7751R 1 External pin combination MD0 low MD1 high MD2 high 2 PLL1 off 6 PLL2 off 3 Frequencies relative to input clock CPU clock 1 Bus clock 1 2 Peripheral module clock 1 2 4...

Page 1178: ...that 0 3 V VDD VDDQ 0 3 V 3 Ensure that VSS VSSQ VSS PLL1 2 VSS CPG VSS RTC GND 0 V The product may be damaged if conditions 1 2 and 3 above are not satisfied Power supply VDDQ Power supply VDD 0 3 V max 0 3 V max GND V t Power on Power off Figure G 2 Power On Procedure 1 VDD min VDDQ min GND 0 5 V 1 2 V 1 0 V 2 0 V tpwu tpwu 100 ms max tpwd 150 ms max tpwd V t Power supply VDDQ Power supply VDD P...

Page 1179: ...751RBP240 V 256 pin BGA HD6417751RF240 V 256 pin QFP 240 MHz 20 to 75 C HD6417751RBG240 V 292 pin BGA HD6417751RBP200 V 256 pin BGA SH7751R 1 5 V 200 MHz HD6417751RF200 V 256 pin QFP HD6417751RBG200 V 292 pin BGA Notes 1 Contact a Renesas sales office regarding product versions with specifications for a wider temperature range 40 to 85 C The wide temperature range 40 to 85 C is the standard specif...

Page 1180: ...Appendix E Synchronous DRAM Address Multiplexing Tables SH7751 Group SH7751R Group Page 1126 of 1128 R01UH0457EJ0301 Rev 3 01 Sep 24 2013 ...

Page 1181: ...PVR R H FF000030 H 1F000030 32 Product register PRR R H FF000044 H 1F000044 32 Note Refer to table below PVR and PRR Initial Values Product Name PVR PRR SH7751 H 041100xx H xxxxxxxx SH7751R H 040500xx H 0000011x Legend x Undefined 1 Processor Version Register PVR Initial Value Example for SH7751R Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Version information Initial value 0 0 0 0 0 1 0 0 ...

Page 1182: ... 2 Product Register PRR Initial Value Example for SH7751R Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Version information Initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 R W R R R R R R R R R R R R R R R R Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Version information Initial value 0 0 0 0 0 0 0 1 0 0 0 1 R W R R R R R R R R R R R R ...

Page 1183: ...Renesas 32 Bit RISC Microcomputer SH7751 Group SH7751R Group User s Manual Hardware Publication Date 1st Edition April 2000 Rev 3 01 September 24 2013 Published by Renesas Electronics Corporation ...

Page 1184: ...iChunLu Haidian District Beijing 100083 P R China Tel 86 10 8235 1155 Fax 86 10 8235 7679 Arcadiastrasse 10 40472 D Tel 49 211 65030 Fax 49 211 6503 1327 üsseldorf Germany Dukes Meadow Millboard Road Bourne End Buckinghamshire SL8 5FH U K Tel 44 1628 651 700 Fax 44 1628 651 804 1101 Nicholson Road Newmarket Ontario L3Y 9C3 Canada Tel 1 905 898 5441 Fax 1 905 898 3220 2880 Scott Boulevard Santa Cla...

Page 1185: ......

Page 1186: ... SH7751 Group SH7751R Group User s Manual Hardware R01UH0457EJ0301 Previous Number REJ09B0370 0400 ...

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