-
55
-
You
can
apply
an
input
filter
to
the
ORG
input
signal
by
setting
the
FLTR
bit
in
the
RENV2
register.
To
enable
the
EZ
input
signal,
set
the
EINF
bit
in
the
RENV1
register.
Selection
of
the
zero
return
operation
mode
<ORM
(bit
29)
in
RENV2>
0:
Use
only
the
ORG
signal.
1:
Use
the
ORG
signal
and
EZ
signals.
[RENV1]
(WRITE)
31
24
-
-
n
-
-
-
-
-
Reading
the
ORG
signal
<SORG
(bit
14)
in
SSTSW>
0:
Turn
OFF
the
ORG
signal.
1:
Turn
ON
the
ORG
signal.
[SSTSW]
(READ)
15
8
-
n
-
-
-
-
-
-
Select
input
logic
of
the
ORG
signal
<ORGL
(bit
7)
in
RENV1>
0:
Negative
logic.
1:
Positive
logic.
[RENV1]
(WRITE)
7
0
n
-
-
-
-
-
-
-
Set
the
ORG,
SD
input
filter
<FLTR
(bit
26)
in
RENV1>
1:
Apply
a
noise
filter
to
the
±EL,
SD,
ORG,
ALM,
and
INP
inputs.
When
the
filter
is
applied,
signals
which
are
shorter
than
the
FTM
pulse
length
will
be
ignored.
[RENV1]
(WRITE)
31
24
-
-
-
-
-
n
-
-
Specify
a
time
constant
for
the
input
filter
<FLM
(bit
20,
21)
in
RENV1>
00:
3.2
µs
10:
200
µs
01:
25
µs
11:
1.6
ms
[RENV1]
(WRITE)
23
16
-
-
n
n
-
-
-
-
Reading
the
EZ
signal
<SEZ
(bit
10)
in
RSTS>
0:
Turn
OFF
the
EZ
signal.
1:
Turn
ON
the
EZ
signal.
[RSTS]
(READ)
15
8
-
-
-
-
-
n
-
-
Set
the
input
logic
for
the
EZ
signal
<EZL
(bit
28)
in
RENV2>
0:
Rising
edge.
1:
Falling
edge.
[RENV2]
(WRITE)
31
24
0
-
-
n
-
-
-
-
Apply
an
input
filter
to
EA,
EB,
and
EZ
<EINF
(bit
18)
in
RENV2>
1:
Apply
a
noise
filter
to
these
inputs.
Signals
that
are
shorter
than
a
CLK
3
cycle
will
be
ignored.
[RENV2]
(WRITE)
23
16
-
-
-
-
-
n
-
-
Specify
an
EZ
count
amount
<EZD0
to
3
(bits
24
to
27)
in
RENV2>
Specify
the
number
of
EZ
pulses
needed
to
qualify
for
a
zero
return
completion.
Specify
the
value
(Number
of
pulses-1)
in
bits
EZD0
to
3.
Enter
a
number
from
0
to
15.
[RENV2]
(WRITE)
31
24
0
-
-
-
n
n
n
n
When
a
zero
return
is
complete,
the
LSI
can
latch
(and
reset)
the
counter
and
output
an
ERC
(deflection
counter
clear)
signal.
The
RENV3
register
is
used
to
set
the
basic
zero
return
method.
That
is,
whether
or
not
to
reset
the
counter
when
the
zero
return
is
complete.
Specify
whether
or
not
to
output
the
ERC
signal
in
the
RENV1
register.
For
details
about
the
ERC
signal,
see
11-5-2,
"ERC
signal."
Summary of Contents for PCL6113
Page 1: ...User s Manual For PCL6113 6123 6143 Pulse Control LSI Nippon Pulse Motor Co Ltd...
Page 11: ...5 3 Terminal Assignment Diagram 3 1 PCL6113 3 2 PCL6123...
Page 20: ...14 5 Block Diagram...
Page 115: ...109 11 Stop timing by error...
Page 116: ...110 13 External Dimensions 13 1 PCL6113...
Page 117: ...111 13 2 PCL6123...
Page 118: ...112 13 3 PCL6143...
