-
90
-
11-9-2.
Counter
reset
The
following
three
methods
allow
all
the
counters
to
latch
their
count
value
using
the
RENV3
(environment
setting
3)
register.
The
latched
values
can
read
from
the
RLTC1/2
registers.
1)
When
the
LTC
signal
turns
ON.
2)
When
the
ORG
signal
turns
ON.
3)
When
a
command
is
written.
The
input
timing
of
the
LTC
can
be
set
in
the
RENV1
(environment
setting
1)
register.
An
signal
can
be
output
as
an
event
interrupt
factor
when
the
PCL
latches
the
count
value
by
turning
ON
the
LTC
and
ORG
signals.
Write
a
command
to
reset
the
counters.
There
is
no
external
input
terminal
to
reset
the
counters.
However,
the
PCL
has
a
function
that
will
clear
a
counter
soon
after
the
count
value
has
been
latched.
An
external
latch
signal
can
be
input
so
that
you
can
use
the
LTC
input
to
reset
a
counter
from
the
outside.
The
function
used
to
reset
a
counter
soon
after
the
counter
value
is
latched
is
referred
to
as
the
"latch
&
clear
function."
The
latch
timing
can
be
set
in
RENV3
(environment
setting
3)
register.
The
signal
can
be
output
to
interrupt
an
event
when
it
is
latched
by
the
LTC
and
ORG
inputs.
Specify
the
LTC
signal
mode
<Set
LTCL
(bit
23)
in
RENV1>
0:
Latch
on
the
falling
edge.
1:
Latch
on
the
rising
edge.
[RENV1]
(WRITE)
23
16
n
-
-
-
-
-
-
-
Read
the
LTC
signal
<SLTC
(bit
13)
in
RSTS>
0:
The
LTC
signal
is
OFF
1:
The
LTC
signal
is
ON
[RSTS]
(READ)
15
8
-
-
n
-
-
-
-
-
Set
the
COUNTER1
latch
&
clear
function
<Set
CU1L
(bit
4)
in
RENV3>
0:
COUNTER1
is
not
cleared
after
it
is
latched.
1:
COUNTER1
is
cleared
soon
after
it
is
latched.
[RENV3]
(WRITE)
7
0
-
-
-
n
-
-
-
-
Set
the
COUNTER2
latch
&
clear
function
<Set
CU2L
(bit
8)
in
RENV3>
0:
COUNTER2
is
not
cleared
after
it
is
latched.
1:
COUNTER2
is
cleared
soon
after
it
is
latched.
[RENV3]
(WRITE)
15
8
-
-
-
-
-
-
-
n
Set
COUNTER1
to
latch
on
an
external
input
<Set
LOF1
(bit
5)
in
RENV3>
0:
Latch
COUNTER1
on
an
LTC
input
signal.
1:
Do
not
latch
COUNTER1.
[RENV3]
(WRITE)
7
0
-
-
n
-
-
-
-
-
Set
COUNTER2
to
latch
on
an
external
input
<Set
LOF2
(bit
9)
in
RENV3>
0:
Latch
COUNTER2
on
an
LTC
input
signal.
1:
Do
not
latch
COUNTER2.
[RENV3]
(WRITE)
15
8
-
-
-
-
-
-
n
-
Set
COUNTER1
to
latch
on
a
zero
return
<Set
CU1R
(bit
6)
in
RENV3>
0:
Do
not
latch
COUNTER1
at
the
zero
position.
1:
Latch
COUNTER1
at
the
zero
position.
[RENV3]
(WRITE)
7
0
-
n
-
-
-
-
-
-
Set
COUNTER2
to
latch
on
a
zero
return
<Set
CU2R
(bit
10)
in
RENV3>
0:
Do
not
latch
COUNTER2
at
the
zero
position.
1:
Latch
COUNTER2
at
the
zero
position.
[RENV3]
(WRITE)
15
8
-
-
-
-
-
n
-
-
Set
an
event
interrupt
cause
<Set
IRLT
(bit
8)
and
IROL
(bit
9)
in
RIRQ>
IRLT
=
1:
Output
an
signal
when
the
counter
value
is
latched
by
the
LTC
signal
being
turned
ON.
IROL
=
1:
Output
an
signal
when
the
counter
value
is
latched
by
the
ORG
signal
being
turned
ON.
[RIRQ]
(WRITE)
15
8
-
-
-
-
-
-
n
n
Read
the
event
interrupt
cause
<ISLT
(bit
8),
ISOL
(bit
9)
in
RIST>
ISLT
=
1:
Latch
the
counter
value
when
the
LTC
signal
turns
ON.
ISOL
=
1:
Latch
the
counter
value
when
the
ORG
signal
turns
ON.
[RIST]
(READ)
15
8
-
-
-
-
-
-
n
n
Counter
latch
command
<LTCH:
Bit
control
command>
Latch
the
contents
of
the
counters
(COUNTER1
to
2).
[Bit
control
command]
29h
Summary of Contents for PCL6113
Page 1: ...User s Manual For PCL6113 6123 6143 Pulse Control LSI Nippon Pulse Motor Co Ltd...
Page 11: ...5 3 Terminal Assignment Diagram 3 1 PCL6113 3 2 PCL6123...
Page 20: ...14 5 Block Diagram...
Page 115: ...109 11 Stop timing by error...
Page 116: ...110 13 External Dimensions 13 1 PCL6113...
Page 117: ...111 13 2 PCL6123...
Page 118: ...112 13 3 PCL6143...
