NPM PCL6113, User Manual

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INDEX
1. Outline and Features................................................................................................................................. 1
1-1. Outline............................................................................................................................................... 1
1-2. Features ............................................................................................................................................ 1
2. Specifications ............................................................................................................................................ 4
3. Terminal Assignment Diagram .................................................................................................................. 5
3-1. PCL6113............................................................................................................................................ 5
3-2. PCL6123 ........................................................................................................................................... 5
3-3. PCL6143 ........................................................................................................................................... 6
4. Function of Terminals ................................................................................................................................ 7
5. Block Diagram ......................................................................................................................................... 14
6. CPU Interface.......................................................................................................................................... 15
6-1. Setting the CPU interface type........................................................................................................ 15
6-2. Hardware design precautions ......................................................................................................... 15
6-3. Examples of CPU interfaces ........................................................................................................... 16
6-4. Address map ................................................................................................................................... 18
6-4-1. Axis arrangement map ............................................................................................................. 18
6-4-2. Internal map of each axis ......................................................................................................... 18
6-5. Description of the map details......................................................................................................... 20
6-5-1. Write the command code and axis selection (COMB0, COMB1)............................................. 20
6-5-2. Write to an output port (OTPW, OTPB) .................................................................................... 21
6-5-3. Write/read the input/output buffer (BUFW, BUFB).................................................................... 21
6-5-4. Reading the main status (MSTSW, MSTSB)............................................................................ 22
6-5-5. Reading the sub status and input/output port (SSTSW, SSTSB, IOPB) .................................. 23
7. Commands (Operation and Control Commands) ................................................................................... 24
7-1. Operation commands...................................................................................................................... 24
7-1-1. Procedure for writing an operation command .......................................................................... 24
7-1-2. Start command ......................................................................................................................... 24
7-1-3. Speed change command.......................................................................................................... 25
7-1-4. Stop command.......................................................................................................................... 25
7-1-5. NOP (do nothing) command..................................................................................................... 25
7-2. General-purpose output bit control commands............................................................................... 26
7-3. Control command............................................................................................................................ 27
7-3-1. Software reset command.......................................................................................................... 27
7-3-2. Counter reset command ........................................................................................................... 27
7-3-3. ERC output control command .................................................................................................. 27
7-3-4. Pre-register control command .................................................................................................. 27
7-3-5. PCS input command................................................................................................................. 27
7-3-6. LTCH input (counter latch) command....................................................................................... 27
7-4. Register control command .............................................................................................................. 28
7-4-1. Procedure for writing data to a register .................................................................................... 28
7-4-2. Procedure for reading data from a register .............................................................................. 28
7-4-3. Table of register control commands.......................................................................................... 29
7-5. General-purpose output port control command .............................................................................. 30
7-5-1. Command writing procedures................................................................................................... 30
7-5-2. Command bit allocation ............................................................................................................ 30