LAPIS Semiconductor ML610421, User Manual, Page: 99 / 437

ML610Q421/ML610Q422/ML610421 User’s Manual
Chapter 6 Clock Generation Circuit
6 – 6
6.3 Description of Operation
6.3.1 Low-Speed Clock
6.3.1.1 Low-Speed Clock Generation Circuit
Figure 6-2 shows the configuration of the low-speed clock generation circuit.
A low-speed clock generation circuit is provided with an external 32.768 kHz crystal. To match the oscillation
frequency by using a trimmer capacitor, connect external capacitors (C
GL
and C
DL
) as required.
In STOP mode, V
DDX
is powered off to stop low-speed oscillation, and the XT0 and XT1 pins become Hiz (Hi
Impedance state).
When the ENMLT bit of FCON1 is set to “1”, the 2
×
low-speed clock circuit starts to generate the LSCLK
×
2(64kHz)
Figure 6-2 Circuit Configuration of 32.768 kHz Crystal Oscillation Mode
Notes:
−
Install a crystal as close to the LSI as possible and make sure that signals causing noise and power supply wiring are
not near the crystal and its wiring.
−
Note that oscillation may stop due to condensation.
− The internal loading capacitance CG=CD=12pF (Typ.) exist in the low-speed clock generation circuit.
XT0
V
SS
C
DL
C
GL
32.768 kHz
crystal
XT1
V
DDX
STOP mode
Low-speed clock
(LSCLK)
R
F
C
D
C
G
V
SS
V
SS
2
×
low-speed clock
(LSCLK
×
2)
ENMLT
2
×
clock
circuit
Control Circuit