LAPIS Semiconductor ML610421, User Manual, Page: 179 / 437

ML610Q421/ML610Q422/ML610421 User’s Manual
Chapter 13 Watchdog Timer
12 – 7
12.3.1 Handling example when you do not want to use the watch dog timer
WDT counter is a free-run counter that starts count-up automatically after the system reset released and the
low-speed clock (LSCLK) starts oscillating. If the WDT counter gets overflow, the WDT non-maskable interrupt
occurs and then a system reset occurs. Therefore, it is needed to clear the WDT counter even if you do not want
to use the WDT as a fale-safe function.
See following example programming codes to clear the WDT counter in the interrupt routine.
Example programming code:
__DI(); // Disable multi-interrupts
do
{
WDTCON = 0x5a;
} while(WDP != 1)
WDTCON = 0xa5;
__EI();