LAPIS Semiconductor ML610421, User Manual, Page: 366 / 437

ML610Q421/ML610Q422/ML610421 User’s Manual
Chapter 26 LCD Drivers
26 – 28
In display allocation register A (DSmCnA: m = 0 to 49, n = 0 to 8), set the lower 8 bits (00H to 71H) of the addresses of
the display registers (DSPR00 to DSPR71) that are output to common n of segment n. In display allocation register B
(DSmCnB: m = 0 to 49, n = 0 to 8), set the bits of the display registers (DSPR00 to DSPR71) that are output to common n
of segment m.
For instance, to display bit 6 of display register 23 to common 3 of segment 16, set as follows.
b7 b6 b5 b4 b3 b2 b1 b0 b7 b6 b5 b4 b3 b2 b1 b0
DS16C3A 0 0 1 0 0 0 1 1 DS16C3B * * * * * 1 1 0
(0F4D0H) (0F6D0H)
Address specification of display register Bit specification of display register
"*" indicates an arbitrary value.
Note:
- Set display allocation data to display allocation registers A and B when the DASN bit of display control register 0
(DSPMOD1) is “0”. When the DASN bit is “1”, access from the CPU is invalid.
- Select type 3 for the display register segment map (Set DADM1 bit of DSPMOD1 register to “1”) when using the
programmable allocation function.