LAPIS Semiconductor ML610421, User Manual, Page: 7 / 437

ML610Q421/ML610Q422/ML610421 User’s Manual
Contents
Contents – 3
6.1.3 List of Pins .......................................................................................................................................... 6-2
6.2 Description of Registers .............................................................................................................................. 6-2
6.2.1 List of Registers .................................................................................................................................. 6-2
6.2.2 Frequency Control Register 0 (FCON0) ............................................................................................. 6-3
6.2.3 Frequency Control Register 1 (FCON1) ............................................................................................. 6-5
6.3 Description of Operation............................................................................................................................. 6-6
6.3.1 Low-Speed Clock................................................................................................................................ 6-6
6.3.1.1 Low-Speed Clock Generation Circuit.............................................................................................. 6-6
6.3.1.2 Operation of Low-Speed Clock Generation Circuit ........................................................................ 6-7
6.3.2 High-Speed Clock ............................................................................................................................... 6-8
6.3.2.1 500 kHz RC Oscillation ................................................................................................................... 6-8
6.3.2.2 Crystal/Ceramic Oscillation Mode .................................................................................................. 6-9
6.3.2.3 Built-in PLL Oscillation Mode ...................................................................................................... 6-10
6.3.2.4 External Clock Input Mode ........................................................................................................... 6-10
6.3.2.5 Operation of High-Speed Clock Generation Circuit ...................................................................... 6-11
6.3.3 Switching of System Clock ............................................................................................................... 6-13
6.4 Specifying port registers ........................................................................................................................... 6-15
6.4.1 Functioning P21 (OUTCLK) as the high speed clock output ........................................................... 6-15
6.4.2 Functioning P20 (LSCLK) as the low speed clock output ................................................................ 6-16
Chapter 7
7. Time Base Counter ......................................................................................................................................... 7-1
7.1 Overview..................................................................................................................................................... 7-1
7.1.1 Features ............................................................................................................................................... 7-1
7.1.2 Configuration ...................................................................................................................................... 7-1
7.2 Description of Registers .............................................................................................................................. 7-3
7.2.1 List of Registers .................................................................................................................................. 7-3
7.2.2 Low-Speed Time Base Counter (LTBR) ............................................................................................ 7-4
7.2.3 High-Speed Time Base Counter Divide Register (HTBDR) .............................................................. 7-5
7.2.4 Low-Speed Time Base Counter Frequency Adjustment Registers L and H
(LTBADJL, LTBADJH) ..................................................................................................................... 7-6
7.3 Description of Operation............................................................................................................................. 7-7
7.3.1 Low-Speed Time Base Counter .......................................................................................................... 7-7
7.3.2 High-Speed Time Base Counter ......................................................................................................... 7-8
7.3.3 Low-Speed Time Base Counter Frequency Adjustment Function ...................................................... 7-9
7.3.4 A signal generation for 16bit timer 2-3 frequency measurement mode ............................................ 7-10
Chapter 8
8. Capture ............................................................................................................................................................ 8-1
8.1 Overview..................................................................................................................................................... 8-1
8.1.1 Features ............................................................................................................................................... 8-1
8.1.2 Configuration ...................................................................................................................................... 8-1
8.1.3 List of Pins .......................................................................................................................................... 8-1
8.2 Description of Registers .............................................................................................................................. 8-2
8.2.1 List of Registers .................................................................................................................................. 8-2
8.2.2 Capture Control Register (CAPCON) ................................................................................................. 8-3
8.2.3 Capture Status Register (CAPSTAT).................................................................................................. 8-4
8.2.4 Capture Data Register 0 (CAPR0) ...................................................................................................... 8-5
8.2.5 Capture Data Register 1 (CAPR1) ...................................................................................................... 8-6
8.3 Description of Operation............................................................................................................................. 8-7
Chapter 9
9. 1 kHz Timer (1kHzTM) .................................................................................................................................. 9-1
9.1 Overview..................................................................................................................................................... 9-1
9.1.1 Features ............................................................................................................................................... 9-1
9.1.2 Configuration ...................................................................................................................................... 9-1