LAPIS Semiconductor ML610421, User Manual, Page: 165 / 437

ML610Q421/ML610Q422/ML610421 User’s Manual
Chapter 11 PWM
11 – 5
11.2.4 PWM0 Counter Registers (PW0CH, PW0CL)
7 6 5 4 3 2 1 0
PW0CL P0C7 P0C6 P0C5 P0C4 P0C3 P0C2 P0C1 P0C0
R/W R/W R/W R/W R/W R/W R/W R/W R/W
At reset 0 0 0 0 0 0 0 0
Address: 0F0A4H
Access: R/W
Access size: 8 bits
Initial value: 00H
7 6 5 4 3 2 1 0
PW0DH P0C15 P0C14 P0C13 P0C12 P0C11 P0C10 P0C9 P0C8
R/W R/W R/W R/W R/W R/W R/W R/W R/W
At reset 0 0 0 0 0 0 0 0
Address: 0F0A5H
Access: R/W
Access size: 8 bits
Initial value: 00H
PW0CL and PW0CH are special function registers (SFRs) that function as 16-bit binary counters.
When data is written to either PW0CL or PW0CH, PW0CL and PW0CH is set to “0000H”. The data that is written is
meaningless.
When data is read from PW0CL, the value of PW0CH is latched. When reading PW0CH and PW0CL, use a word type
instruction or pre-read PW0CL.
The contents of PW0CH and PW0CL during PWM operation cannot be read depending on the combination of the
PWM clock and system clock. Table 11-1 shows PW0CH and PW0CL read enable/disable for each combination of the
PWM clock and system clock.
Table 11-1 PW0CH and PW0CL Read Enable/Disable during PWM0 Operation
PWM clock
P0CK
System clock
SYSCLK
PW0CH and PW0CL read enable/disable
LSCLK LSCLK
Read enabled
LSCLK HSCLK
Read enabled. However, to prevent the reading of undefined
data during counting, read consecutively PW0CH or PW0CL
twice until the last data coincides the previous data.
HTBCLK LSCLK Read disabled
HTBCLK HSCLK
Read enabled
External clock
LSCLK
Read disabled
HSCLK