LAPIS Semiconductor ML610421, User Manual, Page: 226 / 437

ML610Q421/ML610Q422/ML610421 User’s Manual
Chapter 15 I
2
C Bus Interface
15 – 10
When “1” is written to the I20ST bit in the control register setting wait state, the LSI shifts to the data transmit or
receive mode. When “1” is written to the I20SP bit, the LSI shifts to the stop condition. When “1” is written to the
I20RS bit and I20ST bit, the operation shifts to the repeated start condition.
15.3.1.7 Stop Condition
In the stop condition, the stop condition waveform is output to the SDA and SCL pins. After the stop condition
waveform is output, an I
2
C bus interface interrupt (I2C0INT) is generated.