LAPIS Semiconductor ML610421, User Manual, Page: 285 / 437

ML610Q421/ML610Q422/ML610421User’s Manual
Chapter 22 Port A
22 – 3
22.2.2 Port A Data Register (PAD)
Address: 0F250H
Access: R/W
Access size: 8 bits
Initial value: 00H
7 6 5 4 3 2 1 0
PAD PA7D PA6D PA5D PA4D PA3D PA2D PA1D PA0D
R/W R/W R/W R/W R/W R/W R/W R/W R/W
Initial value 0 0 0 0 0 0 0 0
PAD is a special function register (SFR) to set the value to be output to the Port A pin or to read the input level of the
Port A. In output mode, the value of this register is output to the Port A pin. The value written to PAD is readable.
In input mode, the input level of the Port A pin is read when PAD is read. Output mode or input mode is selected by
using the port direction register (PADIR) described later.
[Description of Bits]
•
PA7D-PA0D (bits 7-0)
The PA7D to PA0D bits are used to set the output value of the Port A pin in output mode and to read the pin level of
the Port A pin in input mode.
PA7D Description
0 Output or input level of the PA7 pin: ”L”
1 Output or input level of the PA7 pin: ”H”
PA6D Description
0 Output or input level of the PA6 pin: ”L”
1 Output or input level of the PA6 pin: ”H”
PA5D Description
0 Output or input level of the PA5 pin: ”L”
1 Output or input level of the PA5 pin: ”H”
PA4D Description
0 Output or input level of the PA4 pin: ”L”
1 Output or input level of the PA4 pin: ”H”
PA3D Description
0 Output or input level of the PA3 pin: ”L”
1 Output or input level of the PA3 pin: ”H”
PA2D Description
0 Output or input level of the PA2 pin: ”L”
1 Output or input level of the PA2 pin: ”H”
PA1D Description
0 Output or input level of the PA1 pin: ”L”
1 Output or input level of the PA1 pin: ”H”
PA0D Description
0 Output or input level of the PA0 pin: ”L”
1 Output or input level of the PA0 pin: ”H”