LAPIS Semiconductor ML610421, User Manual, Page: 356 / 437

ML610Q421/ML610Q422/ML610421 User’s Manual
Chapter 26 LCD Drivers
26 – 18
26.2.8 Display Allocation Register B (DS0C0B to DS49C7B)
Address: 0F600H to 0F7FFH
Access: R/W
Access size: 8 bits
Initial value: Undefined
7 6 5 4 3 2 1 0
DSmCnB b7 b6 b5 b4 b3 b2 b1 b0
R/W R/W R/W R/W R/W R/W R/W R/W R/W
Initial value x x x x x x x x
DSmCnB (m= 0 to 49, n = 0 to 7) are special function registers (SFRs) to store segment allocation data.
Each valid bit of DSmCnB becomes undefined at system reset.
When the programmable display allocation function is not used (DASN bit of DSPMOD1 reigster is reset to “0”),
DSmCnB can be used as data memory space (512-byte RAM).
Table 26-3 shows a list of display allocation register B.
[Description of Bits]
•
b2-b0 (bits 2-0)
The b2 to b0 bits of DSmCnB (m= 0 to 49, n = 0 to 7) are used to set the bits of the display registers (DSPR00 to 71)
that are output to common n of segment m.
Set DSmCnB when the DASN bit of the display control register 0 (DSPCON0) is “0”.
When the DASN bit is “1”, access from the CPU is invalid.
b2 b1 b0 Description
0 0 0 Selects bit 0
0 0 1 Selects bit 1
0 1 0 Selects bit 2
0 1 1 Selects bit 3
1 0 0 Selects bit 4
1 0 1 Selects bit 5
1 1 0 Selects bit 6
1 1 1 Selects bit 7