LAPIS Semiconductor ML610421, User Manual, Page: 101 / 437

ML610Q421/ML610Q422/ML610421 User’s Manual
Chapter 6 Clock Generation Circuit
6 – 8
6.3.2 High-Speed Clock
Setting of the OSCM1 and OSCM0 bits of the frequency control register 0 (FCON0) allows selection of the 500 kHz
RC oscillation mode, crysta/ceramic oscillation mode, built-in PLL (Phase Locked Loop) oscillation mode, or external
clock input mode for the high-speed clock generation circuit.
6.3.2.1 500 kHz RC Oscillation
In RC oscillation mode (OSCM0 = “0”, OSCM1 = “0”), supply of OSCLK (high-speed oscillation clock) is started
when RC oscillation clock pulse count reaches 128 after oscillation is enabled (ENOSC is set to “1”).
In 500 kHz RC oscillation mode, both the P10/OSC0 pin and the P11/OSC1 pin can be used as general-purpose input
ports.
Figure 6-4 shows the circuit configuration in RC oscillation mode.
Figure 6-4 Circuit Configuration in RC Oscillation Mode
Notes:
−
The RC oscillation mode is allowed within the range of V
DD
= 1.3 V to 3.6 V.
−
After system reset mode is released, supply of OSCLK starts after the RC oscillation clock pulse count reaches 8192.
After release of a STOP mode, supply of OSCLK starts.
STOP mode
ENOSC (Enables oscillation)
OSCLK (High-speed oscillation clock)
V
DDL
RC oscillation
circuit
Count: 128