LAPIS Semiconductor ML610421, User Manual, Page: 238 / 437

ML610Q421/ML610Q422/ML610421User’s Manual
Chapter 17 Port 0
17 – 1
17. Port 0
17.1 Overview
This LSI includes Port 0 (P00 to P03) which is a 4-bit input port.
17.1.1 Features
•
All bits support a maskable interrupt function.
•
Allows selection of interrupt disabled mode, falling-edge interrupt mode, rising-edge interrupt mode, or both-edge
interrupt mode for each bit.
•
Allows selection of with/without interrupt sampling for each bit.(Sampling frequency: T16KHZ)
•
Allows selection of high-impedance input mode, input mode with a pull-down resistor, or input mode with a pull-up
resistor for each bit.
•
The P00 and P01 pins can be used as the trigger input pins of the capture circuit and the P02 pin can be used as the
RXD0 input pin of UART0.
17.1.2 Configuration
Figure 17-1 shows the configuration of Port 0.
P0D : Port 0 data register
P0CON0 : Port 0 control register 0
P0CON1 : Port 0 control register 1
EXICON0 : External interrupt control register 0
EXICON1 : External interrupt control register 1
EXICON2 : External interrupt control register 2
Figure 17-1 Configuration of Port 0
17.1.3 List of Pins
Pin name I/O Description
P00/EXI0/CAP0 I Input port, External 0 interrupt, Capture 0 trigger signal input
P01/EXI1/CAP1 I Input port, External 1 interrupt, Capture 1 trigger signal input
P02/EXI2/RXD0 I Input port, External 2 interrupt, UART0 data input (RXD0)
P03/EXI3 I Input port, External 3 interrupt
Data bus
P00INT to P03INT
P00 to P03
P0CON0
P0CON1
Interrupt
Controller
V
DD
V
DD
V
SS
V
SS 4
4
Sampling clock
T16KHZ
CAP0, CAP1
2
RXD0
1
Pull-up
Pull-down
Controller
P0D
EXICON0
EXICON1
EXICON2