LAPIS Semiconductor ML610421, User Manual, Page: 106 / 437

ML610Q421/ML610Q422/ML610421 User’s Manual
Chapter 6 Clock Generation Circuit
6 – 13
6.3.3 Switching of System Clock
The system clock can be switched between high-speed clock (HSCLK) and low-speed clock (LSCLK) by using the
frequency control registers (FCON0, FCON1).
Figure 6-10 shows a flow of system clock switching processing (HSCLK
→
LSCLK) and Figure 6-11 shows a flow of
system clock switching processing (LSCLK
→
HSCLK).
Figure 6-10 Flow of System Clock Switching Processing (HSCLK
→
LSCLK)
Note:
After the power is turned on or if the system clock is switched from HSCLK to LSCLK immediately following return
from the STOP mode, the CPU becomes inactive until LSCLK starts clock supply to the peripheral circuits. Therefore,
It is recommended to switch to LSCLK after confirming that the LSCLK is oscillating by checking that the time base
counter interrupt request bit (Q128H) is “1”.
System clock switching (High-speed clock
→
Low-speed clock)
System clock switching
Low-speed operation mode
Stop of high-speed oscillation
(* do not need to stop the oscillation if the high-speed clock is used
for any peripheral)
SYSCLK
←
”0”
ENOSC
←
”0”