LAPIS Semiconductor ML610421, User Manual, Page: 225 / 437

ML610Q421/ML610Q422/ML610421 User’s Manual
Chapter 15 I
2
C Bus Interface
15 – 9
15.3 Description of Operation
15.3.1 Communication Operating Mode
Communication is started when communication mode is selected by using the I
2
C bus 0 mode register (I2C0MOD), the
I
2
C function is enabled by using the I20EN bit, a slave address and a data communication direction are set in the I
2
C
bus 0 slave address register, and “1” is written to the I20ST bit of the I2C bus 0 control register (I2C0CON).
15.3.1.1 Start Condition
When “1” is written to the I20ST bit of the I
2
C bus 0 control register ((I2C0CON) while communication is stopped (the
I20ST bit is “0”), communication is started and the start condition waveform is output to the SDA and SCL pins.
After execution of the start condition, the LSI shifts to slave address transmit mode.
15.3.1.2 Repeated Start Condition
When “1” is written to the I20RS and I20ST bits of the I
2
C bus 0 control register ((I2C0CON) during communication
(the I20ST bit is “0”), the repeated start condition waveform is output to the SDA and SCL pins. If you want to
continue the communication without making the stop condition, executing the repeated start condition enables to
specify another slave addresses or change the data direction (transmit or receive) See Figure 15-4.
After execution of the repeated start condition, the LSI shifts to slave address transmit mode.
15.3.1.3 Slave Address Transmit Mode
In slave address transmit mode, the values (slave address and data communication direction) of the I
2
C bus 0 slave
address register (I2C0SA) are transmitted in MSB first, and finally, the acknowledgment signal is received in the
I20ACR bit of the I
2
C bus 0 status register (I2CSTAT). The I20ACR bit is reset to “0” when receving an
acknowledgment “0” and set to “1” when receving an acknowledgment “1”.
At completion of acknowledgment reception, the LSI shifts to the I
2
C bus 0 control register (I2C0CON) setting wait
state (control register setting wait state).
The value of I2C0SA output from the SDA pin is stored in I2C0RD during aftermentioned Control Register Setting
Wait State.
15.3.1.4 Data Transmit Mode
In data transmit mode, the value of I2C0TD is transmitted in MSB first, and finally, the acknowledgment signal is
received in the I20ACR bit of the I
2
C bus 0 status register (I2CSTAT). The I20ACR bit is reset to “0” when receving an
acknowledgment “0” and set to “1” when receving an acknowledgment “1”.
At completion of acknowledgment reception, the LSI shifts to the I
2
C bus 0 control register (I2C0CON) setting wait
state (control register setting wait state).
The value of I2C0TD output from the SDA pin is stored in I2C0RD.
15.3.1.5 Data Receive Mode
In data receive mode, the value input in the SDA pin is received synchronously with the rising edge of the serial clock
output to the SCL pin, and finally, the value of the I20ACT bit of the I2C bus 0 control register (I2C0CON) is output as
an acknowledge signal. For example, as shown in Figure 15-3 and Figure 15-4, the acknowlege slot after I20ACT bit is
reset to “0” (I2CON=”01H”) will have the acknowlege “0” (Shown as “A” in the Figure). In the same way, the
acknowlege slot after I20ACT bit is set to “1” (I2CON=”81H”) will have the non-acknowlege “1” (Shown as “A” in the
Figure).
At completion of acknowledgment transmission, the LSI shifts to the I
2
C bus 0 control register (I2C0CON) setting wait
state (control register setting wait state).
The data received is stored in I2C0RD after the acknowledgment signal is output. The acknowledgment signal output
is received in the I20ACR bit of the I
2
C bus 0 status register (I2CSTAT).
15.3.1.6 Control Register Setting Wait State
When the LSI shifts to the control register setting wait state, an I
2
C bus interface interrupt (I2C0INT) is generated.
In the control register setting wait state, the transmit flag (I20ER) of the I
2
C bus 0 status register (I2C0STAT) and
acknowledgment receive data (I20ACR) are confirmed and at data reception, the contents of I2C0RD are read in the
CPU and the next operation mode is selected.