LAPIS Semiconductor ML610421, User Manual, Page: 109 / 437

ML610Q421/ML610Q422/ML610421 User’s Manual
Chapter 6 Clock Generation Circuit
6 – 16
6.4.2 Functioning P20 (LSCLK) as the low speed clock output
Set P20MD bit (bit0 of P2MOD register) to “1” for specifying the low speed clock output as the secondary function of
P20.
Reg. name P2MOD register (Address: 0F214H)
Bit 7 6 5 4 3 2 1 0
Bit name
- - - - - P22MD P21MD P20MD
Data - - - - - * * 1
Set P20C1 bit (bit0 of P2CON1 register) to “1” and P20C0 bit (bit0 of P2CON0 register), for specifying P20 as
CMOS output.
Reg. name P2CON1 register (Address: 0F213H)
Bit 7 6 5 4 3 2 1 0
Bit name
- - - - - P22C1 P21C1 P20C1
Data - - - - - * * 1
Reg. name P2CON0 register (Address: 0F212H)
Bit 7 6 5 4 3 2 1 0
Bit name
- - - - - P22C0 P21C0 P20C0
Data - - - - - * * 1
Data of P20D bit (bit0 of P2D register) does not affect to the low speed clock output function, so don’t care the data
for the function.
Reg. name P2D register (Address: 0F210H)
Bit 7 6 5 4 3 2 1 0
Bit name
- - - - - P22D P21D P20D
Data - - - - - * * **
- : Bit does not exist.
* : Bit not related to the low speed clock function
** : Don’t care the data.
Note:
P20(Port2) is an output-only port, does not have an register to select the data direction(i.e. input or output).