LAPIS Semiconductor ML610421, User Manual, Page: 363 / 437

ML610Q421/ML610Q422/ML610421 User’s Manual
Chapter 26 LCD Drivers
26 – 25
26.3 Description of Operation
26.3.1 Operation of LCD Drivers and Bias Generation Circuit
Figure 26-6 shows the operation of the LCD drivers and the bias generation circuit.
Figure 26-6 Operation of LCD Drivers and Bias Generation Circuit

System reset causes the bias generation circuit and the LCD drivers to stop operation and Vss level to be output to
each of the common and segment pins.

By using the bias circuit control register (BIASCON), select 1/3 bias or 1/4 bias and lock of bias voltage multiplying,
and set the bias generation circuit to on (BSON = “1”).

When the programmable display allocation function is used, set LCD allocation data in the display allocation registers
A and B (DS0C0A to DS49C7A and DS0C0B to DS49C7B).

Set a frame frequency and a duty by using the display mode register 0 (DSPMOD0). When using the programmable
display allocation function, set the DASN bit of DSPMOD1 register to “1” and set DADM1 bit to “1” to select type 3
for the display register segment map. When not using the programmable display allocation function, set the DASN bit
to “0” and select a type of segment map for display registers.

Set display data in the display registers (DSPR00 to DSPR71).

After elapse of the bias activation time (T
BIAS
) or longer, set the mode to display mode by using the LMD1 and LMD0
bits of the display control register (DSPCON). (Display waveform is output to each segment pin.)
For the bias activation time (T
BIAS
), see the “Electrical Characteristics” Section in Appendix C.
Reset
RESET_N
BIASCON.BSON
LMD1, LMD0
LCD bias voltage
V
L1
to V
L4
Common output
COM0 to COM7/15
Segment output
SEG0 to SEG49
V
SS
V
SS
Generation of LCD bias voltage
Common output waveform
Segment output waveform
BIAS activation time (T
BIAS
)
   