LAPIS Semiconductor ML610421, User Manual, Page: 46 / 437

ML610Q421/ML610Q422/ML610421 User’s Manual
Chapter 2 CPU and Memory Space
2 – 2
2.3 Data Memory Space
The data memory space of this LSI consists of the ROM window area, 1KByte RAM area and SFR area of Segment 0
and the ROM reference areas of the Segment 1 and Segment 8.
The data memory stores 8-bit data and is specified by 20 bits consisting of higher 4 bits as DSR and lower 16 bits as
addressing specified by each instruction.
Figure 2-2 shows the configuration of the data memory space.
DSR: Data address Segment 0 DSR: Data address Segment 8
0:0000H
ROM Window
Area
8:0000H
ROM Reference
Area
0:7DFFH 8:7DFFH
0:7E00H
Unused Area
8:7E00H
Test Data Area
8:7FFFH
8:8000H
Unused Area
0:0DFFFH
0:0E000H
RAM Area
1KByte
0:0E3FFH
0:0E400H
Unused Area
0:0F000H
SFR Area
0:0FFFFH 8:0FFFFH
8bit 8bit
Figure 2-2 Configuration of Data Memory Space
Notes:
−
The contents of the 1-Kbyte RAM area are undefined at system reset. Initialize this area by software.
−
The contents of Segment 0 of the program memory space is read from the ROM reference area of Segment 8.
2.4 Instruction Length
The length of a instruction is 16 bits.
2.5 Data Type
The data types supported include byte (8 bits) and word (16 bits).