LAPIS Semiconductor ML610421, User Manual, Page: 217 / 437

ML610Q421/ML610Q422/ML610421 User’s Manual
Chapter 15 I
2
C Bus Interface
15 – 1
15. I
2
C Bus Interface
15.1 Overview
This LSI includes 1 channel of I
2
C bus interface (master).
The secondary functions of Port 4 are assigned to the I
2
C bus interface data input/output pin and the I
2
C bus interface
clock input/output pin. For Port4, see Chapter 21, “Port 4”.
15.1.1 Features
•
Master function
•
Communication speeds supported include standard mode (100 kbps@4MHz HSCLK, 50kbps@500kHz HSCLK) and
fast mode (400kbps
＠４
MH
ｚ
HSCLK).
•
7-bit address format (10-bit address can be supported)
Note:
This LSI does not support arbitration function (multi-master) and clock synchronization (handshake).
15.1.2 Configuration
Figure 15-1 shows the configuration of the I
2
C bus interface.
I2C0RD : I
2
C bus 0 receive register
I2C0SA : I
2
C bus 0 slave address register
I2C0TD : I
2
C bus 0 transmit data register
I2C0CON : I
2
C bus 0 control register
I2C0MOD : I
2
C bus 0 mode register
I2C0STAT : I
2
C bus 0 status register
Figure 15-1 Configuration of I
2
C Bus Interface
15.1.3 List of Pins
Pin name I/O Description
P40/SDA I/O
I
2
C bus interface data input/output pin.
Used for the secondary function of the P40 pin.
P41/SCL I/O
I
2
C bus interface clock input/output pin.
Used for the secondary function of the P41 pin.
Clock
Generator
Shift Register
Data bus
I2C0INT
I2C0MOD
HSCLK
I2C0TD
I2C0RD, I2C0STAT
SCL
SDA
Controller
I2C0CON
P41/SCL
P40/SDA
I2C0SA
I2C
Controller